drivers/watchdog/at91sam9_wdt.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * drivers/watchdog/at91sam9_wdt.h
0004  *
0005  * Copyright (C) 2007 Andrew Victor
0006  * Copyright (C) 2007 Atmel Corporation.
0007  * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
0008  *
0009  * Watchdog Timer (WDT) - System peripherals regsters.
0010  * Based on AT91SAM9261 datasheet revision D.
0011  * Based on SAM9X60 datasheet.
0012  *
0013  */
0014
0015 #ifndef AT91_WDT_H
0016 #define AT91_WDT_H
0017
0018 #include <linux/bits.h>
0019
0020 #define AT91_WDT_CR     0x00            /* Watchdog Control Register */
0021 #define  AT91_WDT_WDRSTT    BIT(0)          /* Restart */
0022 #define  AT91_WDT_KEY       (0xa5UL << 24)      /* KEY Password */
0023
0024 #define AT91_WDT_MR     0x04            /* Watchdog Mode Register */
0025 #define  AT91_WDT_WDV       (0xfffUL << 0)      /* Counter Value */
0026 #define  AT91_WDT_SET_WDV(x)    ((x) & AT91_WDT_WDV)
0027 #define  AT91_SAM9X60_PERIODRST BIT(4)      /* Period Reset */
0028 #define  AT91_SAM9X60_RPTHRST   BIT(5)      /* Minimum Restart Period */
0029 #define  AT91_WDT_WDFIEN    BIT(12)     /* Fault Interrupt Enable */
0030 #define  AT91_SAM9X60_WDDIS BIT(12)     /* Watchdog Disable */
0031 #define  AT91_WDT_WDRSTEN   BIT(13)     /* Reset Processor */
0032 #define  AT91_WDT_WDRPROC   BIT(14)     /* Timer Restart */
0033 #define  AT91_WDT_WDDIS     BIT(15)     /* Watchdog Disable */
0034 #define  AT91_WDT_WDD       (0xfffUL << 16)     /* Delta Value */
0035 #define  AT91_WDT_SET_WDD(x)    (((x) << 16) & AT91_WDT_WDD)
0036 #define  AT91_WDT_WDDBGHLT  BIT(28)     /* Debug Halt */
0037 #define  AT91_WDT_WDIDLEHLT BIT(29)     /* Idle Halt */
0038
0039 #define AT91_WDT_SR     0x08        /* Watchdog Status Register */
0040 #define  AT91_WDT_WDUNF     BIT(0)      /* Watchdog Underflow */
0041 #define  AT91_WDT_WDERR     BIT(1)      /* Watchdog Error */
0042
0043 /* Watchdog Timer Value Register */
0044 #define AT91_SAM9X60_VR     0x08
0045
0046 /* Watchdog Window Level Register */
0047 #define AT91_SAM9X60_WLR    0x0c
0048 /* Watchdog Period Value */
0049 #define  AT91_SAM9X60_COUNTER   (0xfffUL << 0)
0050 #define  AT91_SAM9X60_SET_COUNTER(x)    ((x) & AT91_SAM9X60_COUNTER)
0051
0052 /* Interrupt Enable Register */
0053 #define AT91_SAM9X60_IER    0x14
0054 /* Period Interrupt Enable */
0055 #define  AT91_SAM9X60_PERINT    BIT(0)
0056 /* Interrupt Disable Register */
0057 #define AT91_SAM9X60_IDR    0x18
0058 /* Interrupt Status Register */
0059 #define AT91_SAM9X60_ISR    0x1c
0060
0061 #endif