drivers/watchdog/armada_37xx_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Watchdog driver for Marvell Armada 37xx SoCs
0004  *
0005  * Author: Marek Behún <kabel@kernel.org>
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/err.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/module.h>
0015 #include <linux/moduleparam.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regmap.h>
0020 #include <linux/types.h>
0021 #include <linux/watchdog.h>
0022
0023 /*
0024  * There are four counters that can be used for watchdog on Armada 37xx.
0025  * The addresses for counter control registers are register base plus ID*0x10,
0026  * where ID is 0, 1, 2 or 3.
0027  *
0028  * In this driver we use IDs 0 and 1. Counter ID 1 is used as watchdog counter,
0029  * while counter ID 0 is used to implement pinging the watchdog: counter ID 1 is
0030  * set to restart counting from initial value on counter ID 0 end count event.
0031  * Pinging is done by forcing immediate end count event on counter ID 0.
0032  * If only one counter was used, pinging would have to be implemented by
0033  * disabling and enabling the counter, leaving the system in a vulnerable state
0034  * for a (really) short period of time.
0035  *
0036  * Counters ID 2 and 3 are enabled by default even before U-Boot loads,
0037  * therefore this driver does not provide a way to use them, eg. by setting a
0038  * property in device tree.
0039  */
0040
0041 #define CNTR_ID_RETRIGGER       0
0042 #define CNTR_ID_WDOG            1
0043
0044 /* relative to cpu_misc */
0045 #define WDT_TIMER_SELECT        0x64
0046 #define WDT_TIMER_SELECT_MASK       0xf
0047 #define WDT_TIMER_SELECT_VAL        BIT(CNTR_ID_WDOG)
0048
0049 /* relative to reg */
0050 #define CNTR_CTRL(id)           ((id) * 0x10)
0051 #define CNTR_CTRL_ENABLE        0x0001
0052 #define CNTR_CTRL_ACTIVE        0x0002
0053 #define CNTR_CTRL_MODE_MASK     0x000c
0054 #define CNTR_CTRL_MODE_ONESHOT      0x0000
0055 #define CNTR_CTRL_MODE_HWSIG        0x000c
0056 #define CNTR_CTRL_TRIG_SRC_MASK     0x00f0
0057 #define CNTR_CTRL_TRIG_SRC_PREV_CNTR    0x0050
0058 #define CNTR_CTRL_PRESCALE_MASK     0xff00
0059 #define CNTR_CTRL_PRESCALE_MIN      2
0060 #define CNTR_CTRL_PRESCALE_SHIFT    8
0061
0062 #define CNTR_COUNT_LOW(id)      (CNTR_CTRL(id) + 0x4)
0063 #define CNTR_COUNT_HIGH(id)     (CNTR_CTRL(id) + 0x8)
0064
0065 #define WATCHDOG_TIMEOUT        120
0066
0067 static unsigned int timeout;
0068 module_param(timeout, int, 0);
0069 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
0070
0071 static bool nowayout = WATCHDOG_NOWAYOUT;
0072 module_param(nowayout, bool, 0);
0073 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
0074                __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
0075
0076 struct armada_37xx_watchdog {
0077     struct watchdog_device wdt;
0078     struct regmap *cpu_misc;
0079     void __iomem *reg;
0080     u64 timeout; /* in clock ticks */
0081     unsigned long clk_rate;
0082     struct clk *clk;
0083 };
0084
0085 static u64 get_counter_value(struct armada_37xx_watchdog *dev, int id)
0086 {
0087     u64 val;
0088
0089     /*
0090      * when low is read, high is latched into flip-flops so that it can be
0091      * read consistently without using software debouncing
0092      */
0093     val = readl(dev->reg + CNTR_COUNT_LOW(id));
0094     val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32;
0095
0096     return val;
0097 }
0098
0099 static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val)
0100 {
0101     writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id));
0102     writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id));
0103 }
0104
0105 static void counter_enable(struct armada_37xx_watchdog *dev, int id)
0106 {
0107     u32 reg;
0108
0109     reg = readl(dev->reg + CNTR_CTRL(id));
0110     reg |= CNTR_CTRL_ENABLE;
0111     writel(reg, dev->reg + CNTR_CTRL(id));
0112 }
0113
0114 static void counter_disable(struct armada_37xx_watchdog *dev, int id)
0115 {
0116     u32 reg;
0117
0118     reg = readl(dev->reg + CNTR_CTRL(id));
0119     reg &= ~CNTR_CTRL_ENABLE;
0120     writel(reg, dev->reg + CNTR_CTRL(id));
0121 }
0122
0123 static void init_counter(struct armada_37xx_watchdog *dev, int id, u32 mode,
0124              u32 trig_src)
0125 {
0126     u32 reg;
0127
0128     reg = readl(dev->reg + CNTR_CTRL(id));
0129
0130     reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
0131          CNTR_CTRL_TRIG_SRC_MASK);
0132
0133     /* set mode */
0134     reg |= mode & CNTR_CTRL_MODE_MASK;
0135
0136     /* set prescaler to the min value */
0137     reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
0138
0139     /* set trigger source */
0140     reg |= trig_src & CNTR_CTRL_TRIG_SRC_MASK;
0141
0142     writel(reg, dev->reg + CNTR_CTRL(id));
0143 }
0144
0145 static int armada_37xx_wdt_ping(struct watchdog_device *wdt)
0146 {
0147     struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
0148
0149     /* counter 1 is retriggered by forcing end count on counter 0 */
0150     counter_disable(dev, CNTR_ID_RETRIGGER);
0151     counter_enable(dev, CNTR_ID_RETRIGGER);
0152
0153     return 0;
0154 }
0155
0156 static unsigned int armada_37xx_wdt_get_timeleft(struct watchdog_device *wdt)
0157 {
0158     struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
0159     u64 res;
0160
0161     res = get_counter_value(dev, CNTR_ID_WDOG) * CNTR_CTRL_PRESCALE_MIN;
0162     do_div(res, dev->clk_rate);
0163
0164     return res;
0165 }
0166
0167 static int armada_37xx_wdt_set_timeout(struct watchdog_device *wdt,
0168                        unsigned int timeout)
0169 {
0170     struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
0171
0172     wdt->timeout = timeout;
0173
0174     /*
0175      * Compute the timeout in clock rate. We use smallest possible
0176      * prescaler, which divides the clock rate by 2
0177      * (CNTR_CTRL_PRESCALE_MIN).
0178      */
0179     dev->timeout = (u64)dev->clk_rate * timeout;
0180     do_div(dev->timeout, CNTR_CTRL_PRESCALE_MIN);
0181
0182     return 0;
0183 }
0184
0185 static bool armada_37xx_wdt_is_running(struct armada_37xx_watchdog *dev)
0186 {
0187     u32 reg;
0188
0189     regmap_read(dev->cpu_misc, WDT_TIMER_SELECT, &reg);
0190     if ((reg & WDT_TIMER_SELECT_MASK) != WDT_TIMER_SELECT_VAL)
0191         return false;
0192
0193     reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG));
0194     return !!(reg & CNTR_CTRL_ACTIVE);
0195 }
0196
0197 static int armada_37xx_wdt_start(struct watchdog_device *wdt)
0198 {
0199     struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
0200
0201     /* select counter 1 as watchdog counter */
0202     regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, WDT_TIMER_SELECT_VAL);
0203
0204     /* init counter 0 as retrigger counter for counter 1 */
0205     init_counter(dev, CNTR_ID_RETRIGGER, CNTR_CTRL_MODE_ONESHOT, 0);
0206     set_counter_value(dev, CNTR_ID_RETRIGGER, 0);
0207
0208     /* init counter 1 to be retriggerable by counter 0 end count */
0209     init_counter(dev, CNTR_ID_WDOG, CNTR_CTRL_MODE_HWSIG,
0210              CNTR_CTRL_TRIG_SRC_PREV_CNTR);
0211     set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
0212
0213     /* enable counter 1 */
0214     counter_enable(dev, CNTR_ID_WDOG);
0215
0216     /* start counter 1 by forcing immediate end count on counter 0 */
0217     counter_enable(dev, CNTR_ID_RETRIGGER);
0218
0219     return 0;
0220 }
0221
0222 static int armada_37xx_wdt_stop(struct watchdog_device *wdt)
0223 {
0224     struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
0225
0226     counter_disable(dev, CNTR_ID_WDOG);
0227     counter_disable(dev, CNTR_ID_RETRIGGER);
0228     regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, 0);
0229
0230     return 0;
0231 }
0232
0233 static const struct watchdog_info armada_37xx_wdt_info = {
0234     .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
0235     .identity = "Armada 37xx Watchdog",
0236 };
0237
0238 static const struct watchdog_ops armada_37xx_wdt_ops = {
0239     .owner = THIS_MODULE,
0240     .start = armada_37xx_wdt_start,
0241     .stop = armada_37xx_wdt_stop,
0242     .ping = armada_37xx_wdt_ping,
0243     .set_timeout = armada_37xx_wdt_set_timeout,
0244     .get_timeleft = armada_37xx_wdt_get_timeleft,
0245 };
0246
0247 static void armada_clk_disable_unprepare(void *data)
0248 {
0249     clk_disable_unprepare(data);
0250 }
0251
0252 static int armada_37xx_wdt_probe(struct platform_device *pdev)
0253 {
0254     struct armada_37xx_watchdog *dev;
0255     struct resource *res;
0256     struct regmap *regmap;
0257     int ret;
0258
0259     dev = devm_kzalloc(&pdev->dev, sizeof(struct armada_37xx_watchdog),
0260                GFP_KERNEL);
0261     if (!dev)
0262         return -ENOMEM;
0263
0264     dev->wdt.info = &armada_37xx_wdt_info;
0265     dev->wdt.ops = &armada_37xx_wdt_ops;
0266
0267     regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
0268                          "marvell,system-controller");
0269     if (IS_ERR(regmap))
0270         return PTR_ERR(regmap);
0271     dev->cpu_misc = regmap;
0272
0273     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0274     if (!res)
0275         return -ENODEV;
0276     dev->reg = devm_ioremap(&pdev->dev, res->start, resource_size(res));
0277     if (!dev->reg)
0278         return -ENOMEM;
0279
0280     /* init clock */
0281     dev->clk = devm_clk_get(&pdev->dev, NULL);
0282     if (IS_ERR(dev->clk))
0283         return PTR_ERR(dev->clk);
0284
0285     ret = clk_prepare_enable(dev->clk);
0286     if (ret)
0287         return ret;
0288     ret = devm_add_action_or_reset(&pdev->dev,
0289                        armada_clk_disable_unprepare, dev->clk);
0290     if (ret)
0291         return ret;
0292
0293     dev->clk_rate = clk_get_rate(dev->clk);
0294     if (!dev->clk_rate)
0295         return -EINVAL;
0296
0297     /*
0298      * Since the timeout in seconds is given as 32 bit unsigned int, and
0299      * the counters hold 64 bit values, even after multiplication by clock
0300      * rate the counter can hold timeout of UINT_MAX seconds.
0301      */
0302     dev->wdt.min_timeout = 1;
0303     dev->wdt.max_timeout = UINT_MAX;
0304     dev->wdt.parent = &pdev->dev;
0305
0306     /* default value, possibly override by module parameter or dtb */
0307     dev->wdt.timeout = WATCHDOG_TIMEOUT;
0308     watchdog_init_timeout(&dev->wdt, timeout, &pdev->dev);
0309
0310     platform_set_drvdata(pdev, &dev->wdt);
0311     watchdog_set_drvdata(&dev->wdt, dev);
0312
0313     armada_37xx_wdt_set_timeout(&dev->wdt, dev->wdt.timeout);
0314
0315     if (armada_37xx_wdt_is_running(dev))
0316         set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
0317
0318     watchdog_set_nowayout(&dev->wdt, nowayout);
0319     watchdog_stop_on_reboot(&dev->wdt);
0320     ret = devm_watchdog_register_device(&pdev->dev, &dev->wdt);
0321     if (ret)
0322         return ret;
0323
0324     dev_info(&pdev->dev, "Initial timeout %d sec%s\n",
0325          dev->wdt.timeout, nowayout ? ", nowayout" : "");
0326
0327     return 0;
0328 }
0329
0330 static int __maybe_unused armada_37xx_wdt_suspend(struct device *dev)
0331 {
0332     struct watchdog_device *wdt = dev_get_drvdata(dev);
0333
0334     return armada_37xx_wdt_stop(wdt);
0335 }
0336
0337 static int __maybe_unused armada_37xx_wdt_resume(struct device *dev)
0338 {
0339     struct watchdog_device *wdt = dev_get_drvdata(dev);
0340
0341     if (watchdog_active(wdt))
0342         return armada_37xx_wdt_start(wdt);
0343
0344     return 0;
0345 }
0346
0347 static const struct dev_pm_ops armada_37xx_wdt_dev_pm_ops = {
0348     SET_SYSTEM_SLEEP_PM_OPS(armada_37xx_wdt_suspend,
0349                 armada_37xx_wdt_resume)
0350 };
0351
0352 #ifdef CONFIG_OF
0353 static const struct of_device_id armada_37xx_wdt_match[] = {
0354     { .compatible = "marvell,armada-3700-wdt", },
0355     {},
0356 };
0357 MODULE_DEVICE_TABLE(of, armada_37xx_wdt_match);
0358 #endif
0359
0360 static struct platform_driver armada_37xx_wdt_driver = {
0361     .probe      = armada_37xx_wdt_probe,
0362     .driver     = {
0363         .name   = "armada_37xx_wdt",
0364         .of_match_table = of_match_ptr(armada_37xx_wdt_match),
0365         .pm = &armada_37xx_wdt_dev_pm_ops,
0366     },
0367 };
0368
0369 module_platform_driver(armada_37xx_wdt_driver);
0370
0371 MODULE_AUTHOR("Marek Behun <kabel@kernel.org>");
0372 MODULE_DESCRIPTION("Armada 37xx CPU Watchdog");
0373
0374 MODULE_LICENSE("GPL v2");
0375 MODULE_ALIAS("platform:armada_37xx_wdt");