drivers/watchdog/apple_wdt.c

0001 // SPDX-License-Identifier: GPL-2.0-only OR MIT
0002 /*
0003  * Apple SoC Watchdog driver
0004  *
0005  * Copyright (C) The Asahi Linux Contributors
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/limits.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/watchdog.h>
0018
0019 /*
0020  * Apple Watchdog MMIO registers
0021  *
0022  * This HW block has three separate watchdogs. WD0 resets the machine
0023  * to recovery mode and is not very useful for us. WD1 and WD2 trigger a normal
0024  * machine reset. WD0 additionally supports a configurable interrupt.
0025  * This information can be used to implement pretimeout support at a later time.
0026  *
0027  * APPLE_WDT_WDx_CUR_TIME is a simple counter incremented for each tick of the
0028  * reference clock. It can also be overwritten to any value.
0029  * Whenever APPLE_WDT_CTRL_RESET_EN is set in APPLE_WDT_WDx_CTRL and
0030  * APPLE_WDT_WDx_CUR_TIME >= APPLE_WDT_WDx_BITE_TIME the entire machine is
0031  * reset.
0032  * Whenever APPLE_WDT_CTRL_IRQ_EN is set and APPLE_WDTx_WD1_CUR_TIME >=
0033  * APPLE_WDTx_WD1_BARK_TIME an interrupt is triggered and
0034  * APPLE_WDT_CTRL_IRQ_STATUS is set. The interrupt can be cleared by writing
0035  * 1 to APPLE_WDT_CTRL_IRQ_STATUS.
0036  */
0037 #define APPLE_WDT_WD0_CUR_TIME      0x00
0038 #define APPLE_WDT_WD0_BITE_TIME     0x04
0039 #define APPLE_WDT_WD0_BARK_TIME     0x08
0040 #define APPLE_WDT_WD0_CTRL      0x0c
0041
0042 #define APPLE_WDT_WD1_CUR_TIME      0x10
0043 #define APPLE_WDT_WD1_BITE_TIME     0x14
0044 #define APPLE_WDT_WD1_CTRL      0x1c
0045
0046 #define APPLE_WDT_WD2_CUR_TIME      0x20
0047 #define APPLE_WDT_WD2_BITE_TIME     0x24
0048 #define APPLE_WDT_WD2_CTRL      0x2c
0049
0050 #define APPLE_WDT_CTRL_IRQ_EN       BIT(0)
0051 #define APPLE_WDT_CTRL_IRQ_STATUS   BIT(1)
0052 #define APPLE_WDT_CTRL_RESET_EN     BIT(2)
0053
0054 #define APPLE_WDT_TIMEOUT_DEFAULT   30
0055
0056 struct apple_wdt {
0057     struct watchdog_device wdd;
0058     void __iomem *regs;
0059     unsigned long clk_rate;
0060 };
0061
0062 static struct apple_wdt *to_apple_wdt(struct watchdog_device *wdd)
0063 {
0064     return container_of(wdd, struct apple_wdt, wdd);
0065 }
0066
0067 static int apple_wdt_start(struct watchdog_device *wdd)
0068 {
0069     struct apple_wdt *wdt = to_apple_wdt(wdd);
0070
0071     writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
0072     writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
0073
0074     return 0;
0075 }
0076
0077 static int apple_wdt_stop(struct watchdog_device *wdd)
0078 {
0079     struct apple_wdt *wdt = to_apple_wdt(wdd);
0080
0081     writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CTRL);
0082
0083     return 0;
0084 }
0085
0086 static int apple_wdt_ping(struct watchdog_device *wdd)
0087 {
0088     struct apple_wdt *wdt = to_apple_wdt(wdd);
0089
0090     writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
0091
0092     return 0;
0093 }
0094
0095 static int apple_wdt_set_timeout(struct watchdog_device *wdd, unsigned int s)
0096 {
0097     struct apple_wdt *wdt = to_apple_wdt(wdd);
0098
0099     writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
0100     writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
0101
0102     wdd->timeout = s;
0103
0104     return 0;
0105 }
0106
0107 static unsigned int apple_wdt_get_timeleft(struct watchdog_device *wdd)
0108 {
0109     struct apple_wdt *wdt = to_apple_wdt(wdd);
0110     u32 cur_time, reset_time;
0111
0112     cur_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
0113     reset_time = readl_relaxed(wdt->regs + APPLE_WDT_WD1_BITE_TIME);
0114
0115     return (reset_time - cur_time) / wdt->clk_rate;
0116 }
0117
0118 static int apple_wdt_restart(struct watchdog_device *wdd, unsigned long mode,
0119                  void *cmd)
0120 {
0121     struct apple_wdt *wdt = to_apple_wdt(wdd);
0122
0123     writel_relaxed(APPLE_WDT_CTRL_RESET_EN, wdt->regs + APPLE_WDT_WD1_CTRL);
0124     writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_BITE_TIME);
0125     writel_relaxed(0, wdt->regs + APPLE_WDT_WD1_CUR_TIME);
0126
0127     /*
0128      * Flush writes and then wait for the SoC to reset. Even though the
0129      * reset is queued almost immediately experiments have shown that it
0130      * can take up to ~20-25ms until the SoC is actually reset. Just wait
0131      * 50ms here to be safe.
0132      */
0133     (void)readl_relaxed(wdt->regs + APPLE_WDT_WD1_CUR_TIME);
0134     mdelay(50);
0135
0136     return 0;
0137 }
0138
0139 static void apple_wdt_clk_disable_unprepare(void *data)
0140 {
0141     clk_disable_unprepare(data);
0142 }
0143
0144 static struct watchdog_ops apple_wdt_ops = {
0145     .owner = THIS_MODULE,
0146     .start = apple_wdt_start,
0147     .stop = apple_wdt_stop,
0148     .ping = apple_wdt_ping,
0149     .set_timeout = apple_wdt_set_timeout,
0150     .get_timeleft = apple_wdt_get_timeleft,
0151     .restart = apple_wdt_restart,
0152 };
0153
0154 static struct watchdog_info apple_wdt_info = {
0155     .identity = "Apple SoC Watchdog",
0156     .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
0157 };
0158
0159 static int apple_wdt_probe(struct platform_device *pdev)
0160 {
0161     struct device *dev = &pdev->dev;
0162     struct apple_wdt *wdt;
0163     struct clk *clk;
0164     u32 wdt_ctrl;
0165     int ret;
0166
0167     wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
0168     if (!wdt)
0169         return -ENOMEM;
0170
0171     wdt->regs = devm_platform_ioremap_resource(pdev, 0);
0172     if (IS_ERR(wdt->regs))
0173         return PTR_ERR(wdt->regs);
0174
0175     clk = devm_clk_get(dev, NULL);
0176     if (IS_ERR(clk))
0177         return PTR_ERR(clk);
0178
0179     ret = clk_prepare_enable(clk);
0180     if (ret)
0181         return ret;
0182
0183     ret = devm_add_action_or_reset(dev, apple_wdt_clk_disable_unprepare,
0184                        clk);
0185     if (ret)
0186         return ret;
0187
0188     wdt->clk_rate = clk_get_rate(clk);
0189     if (!wdt->clk_rate)
0190         return -EINVAL;
0191
0192     wdt->wdd.ops = &apple_wdt_ops;
0193     wdt->wdd.info = &apple_wdt_info;
0194     wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate;
0195     wdt->wdd.timeout = APPLE_WDT_TIMEOUT_DEFAULT;
0196
0197     wdt_ctrl = readl_relaxed(wdt->regs + APPLE_WDT_WD1_CTRL);
0198     if (wdt_ctrl & APPLE_WDT_CTRL_RESET_EN)
0199         set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
0200
0201     watchdog_init_timeout(&wdt->wdd, 0, dev);
0202     apple_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
0203     watchdog_stop_on_unregister(&wdt->wdd);
0204     watchdog_set_restart_priority(&wdt->wdd, 128);
0205
0206     return devm_watchdog_register_device(dev, &wdt->wdd);
0207 }
0208
0209 static const struct of_device_id apple_wdt_of_match[] = {
0210     { .compatible = "apple,wdt" },
0211     {},
0212 };
0213 MODULE_DEVICE_TABLE(of, apple_wdt_of_match);
0214
0215 static struct platform_driver apple_wdt_driver = {
0216     .driver = {
0217         .name = "apple-watchdog",
0218         .of_match_table = apple_wdt_of_match,
0219     },
0220     .probe = apple_wdt_probe,
0221 };
0222 module_platform_driver(apple_wdt_driver);
0223
0224 MODULE_DESCRIPTION("Apple SoC watchdog driver");
0225 MODULE_AUTHOR("Sven Peter <sven@svenpeter.dev>");
0226 MODULE_LICENSE("Dual MIT/GPL");