w1/slaves/w1_ds2780.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * 1-Wire implementation for the ds2780 chip
0004  *
0005  * Copyright (C) 2010 Indesign, LLC
0006  *
0007  * Author: Clifton Barnes <cabarnes@indesign-llc.com>
0008  *
0009  * Based on w1-ds2760 driver
0010  */
0011
0012 #ifndef _W1_DS2780_H
0013 #define _W1_DS2780_H
0014
0015 /* Function commands */
0016 #define W1_DS2780_READ_DATA     0x69
0017 #define W1_DS2780_WRITE_DATA        0x6C
0018 #define W1_DS2780_COPY_DATA     0x48
0019 #define W1_DS2780_RECALL_DATA       0xB8
0020 #define W1_DS2780_LOCK          0x6A
0021
0022 /* Register map */
0023 /* Register 0x00 Reserved */
0024 #define DS2780_STATUS_REG       0x01
0025 #define DS2780_RAAC_MSB_REG     0x02
0026 #define DS2780_RAAC_LSB_REG     0x03
0027 #define DS2780_RSAC_MSB_REG     0x04
0028 #define DS2780_RSAC_LSB_REG     0x05
0029 #define DS2780_RARC_REG         0x06
0030 #define DS2780_RSRC_REG         0x07
0031 #define DS2780_IAVG_MSB_REG     0x08
0032 #define DS2780_IAVG_LSB_REG     0x09
0033 #define DS2780_TEMP_MSB_REG     0x0A
0034 #define DS2780_TEMP_LSB_REG     0x0B
0035 #define DS2780_VOLT_MSB_REG     0x0C
0036 #define DS2780_VOLT_LSB_REG     0x0D
0037 #define DS2780_CURRENT_MSB_REG      0x0E
0038 #define DS2780_CURRENT_LSB_REG      0x0F
0039 #define DS2780_ACR_MSB_REG      0x10
0040 #define DS2780_ACR_LSB_REG      0x11
0041 #define DS2780_ACRL_MSB_REG     0x12
0042 #define DS2780_ACRL_LSB_REG     0x13
0043 #define DS2780_AS_REG           0x14
0044 #define DS2780_SFR_REG          0x15
0045 #define DS2780_FULL_MSB_REG     0x16
0046 #define DS2780_FULL_LSB_REG     0x17
0047 #define DS2780_AE_MSB_REG       0x18
0048 #define DS2780_AE_LSB_REG       0x19
0049 #define DS2780_SE_MSB_REG       0x1A
0050 #define DS2780_SE_LSB_REG       0x1B
0051 /* Register 0x1C - 0x1E Reserved */
0052 #define DS2780_EEPROM_REG       0x1F
0053 #define DS2780_EEPROM_BLOCK0_START  0x20
0054 /* Register 0x20 - 0x2F User EEPROM */
0055 #define DS2780_EEPROM_BLOCK0_END    0x2F
0056 /* Register 0x30 - 0x5F Reserved */
0057 #define DS2780_EEPROM_BLOCK1_START  0x60
0058 #define DS2780_CONTROL_REG      0x60
0059 #define DS2780_AB_REG           0x61
0060 #define DS2780_AC_MSB_REG       0x62
0061 #define DS2780_AC_LSB_REG       0x63
0062 #define DS2780_VCHG_REG         0x64
0063 #define DS2780_IMIN_REG         0x65
0064 #define DS2780_VAE_REG          0x66
0065 #define DS2780_IAE_REG          0x67
0066 #define DS2780_AE_40_REG        0x68
0067 #define DS2780_RSNSP_REG        0x69
0068 #define DS2780_FULL_40_MSB_REG      0x6A
0069 #define DS2780_FULL_40_LSB_REG      0x6B
0070 #define DS2780_FULL_3040_SLOPE_REG  0x6C
0071 #define DS2780_FULL_2030_SLOPE_REG  0x6D
0072 #define DS2780_FULL_1020_SLOPE_REG  0x6E
0073 #define DS2780_FULL_0010_SLOPE_REG  0x6F
0074 #define DS2780_AE_3040_SLOPE_REG    0x70
0075 #define DS2780_AE_2030_SLOPE_REG    0x71
0076 #define DS2780_AE_1020_SLOPE_REG    0x72
0077 #define DS2780_AE_0010_SLOPE_REG    0x73
0078 #define DS2780_SE_3040_SLOPE_REG    0x74
0079 #define DS2780_SE_2030_SLOPE_REG    0x75
0080 #define DS2780_SE_1020_SLOPE_REG    0x76
0081 #define DS2780_SE_0010_SLOPE_REG    0x77
0082 #define DS2780_RSGAIN_MSB_REG       0x78
0083 #define DS2780_RSGAIN_LSB_REG       0x79
0084 #define DS2780_RSTC_REG         0x7A
0085 #define DS2780_FRSGAIN_MSB_REG      0x7B
0086 #define DS2780_FRSGAIN_LSB_REG      0x7C
0087 #define DS2780_EEPROM_BLOCK1_END    0x7C
0088 /* Register 0x7D - 0xFF Reserved */
0089
0090 /* Number of valid register addresses */
0091 #define DS2780_DATA_SIZE        0x80
0092
0093 /* Status register bits */
0094 #define DS2780_STATUS_REG_CHGTF     (1 << 7)
0095 #define DS2780_STATUS_REG_AEF       (1 << 6)
0096 #define DS2780_STATUS_REG_SEF       (1 << 5)
0097 #define DS2780_STATUS_REG_LEARNF    (1 << 4)
0098 /* Bit 3 Reserved */
0099 #define DS2780_STATUS_REG_UVF       (1 << 2)
0100 #define DS2780_STATUS_REG_PORF      (1 << 1)
0101 /* Bit 0 Reserved */
0102
0103 /* Control register bits */
0104 /* Bit 7 Reserved */
0105 #define DS2780_CONTROL_REG_UVEN     (1 << 6)
0106 #define DS2780_CONTROL_REG_PMOD     (1 << 5)
0107 #define DS2780_CONTROL_REG_RNAOP    (1 << 4)
0108 /* Bit 0 - 3 Reserved */
0109
0110 /* Special feature register bits */
0111 /* Bit 1 - 7 Reserved */
0112 #define DS2780_SFR_REG_PIOSC        (1 << 0)
0113
0114 /* EEPROM register bits */
0115 #define DS2780_EEPROM_REG_EEC       (1 << 7)
0116 #define DS2780_EEPROM_REG_LOCK      (1 << 6)
0117 /* Bit 2 - 6 Reserved */
0118 #define DS2780_EEPROM_REG_BL1       (1 << 1)
0119 #define DS2780_EEPROM_REG_BL0       (1 << 0)
0120
0121 extern int w1_ds2780_io(struct device *dev, char *buf, int addr, size_t count,
0122             int io);
0123 extern int w1_ds2780_eeprom_cmd(struct device *dev, int addr, int cmd);
0124
0125 #endif /* !_W1_DS2780_H */