w1/masters/ds1wm.c

0001 /*
0002  * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
0003  * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
0004  * like hx4700).
0005  *
0006  * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
0007  * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
0008  *
0009  * Use consistent with the GNU GPL is permitted,
0010  * provided that this copyright notice is
0011  * preserved in its entirety in all copies and derived works.
0012  */
0013
0014 #include <linux/module.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/irq.h>
0018 #include <linux/pm.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/err.h>
0021 #include <linux/delay.h>
0022 #include <linux/mfd/core.h>
0023 #include <linux/mfd/ds1wm.h>
0024 #include <linux/slab.h>
0025
0026 #include <asm/io.h>
0027
0028 #include <linux/w1.h>
0029
0030
0031 #define DS1WM_CMD   0x00    /* R/W 4 bits command */
0032 #define DS1WM_DATA  0x01    /* R/W 8 bits, transmit/receive buffer */
0033 #define DS1WM_INT   0x02    /* R/W interrupt status */
0034 #define DS1WM_INT_EN    0x03    /* R/W interrupt enable */
0035 #define DS1WM_CLKDIV    0x04    /* R/W 5 bits of divisor and pre-scale */
0036 #define DS1WM_CNTRL 0x05    /* R/W master control register (not used yet) */
0037
0038 #define DS1WM_CMD_1W_RESET  (1 << 0)    /* force reset on 1-wire bus */
0039 #define DS1WM_CMD_SRA       (1 << 1)    /* enable Search ROM accelerator mode */
0040 #define DS1WM_CMD_DQ_OUTPUT (1 << 2)    /* write only - forces bus low */
0041 #define DS1WM_CMD_DQ_INPUT  (1 << 3)    /* read only - reflects state of bus */
0042 #define DS1WM_CMD_RST       (1 << 5)    /* software reset */
0043 #define DS1WM_CMD_OD        (1 << 7)    /* overdrive */
0044
0045 #define DS1WM_INT_PD        (1 << 0)    /* presence detect */
0046 #define DS1WM_INT_PDR       (1 << 1)    /* presence detect result */
0047 #define DS1WM_INT_TBE       (1 << 2)    /* tx buffer empty */
0048 #define DS1WM_INT_TSRE      (1 << 3)    /* tx shift register empty */
0049 #define DS1WM_INT_RBF       (1 << 4)    /* rx buffer full */
0050 #define DS1WM_INT_RSRF      (1 << 5)    /* rx shift register full */
0051
0052 #define DS1WM_INTEN_EPD     (1 << 0)    /* enable presence detect int */
0053 #define DS1WM_INTEN_IAS     (1 << 1)    /* INTR active state */
0054 #define DS1WM_INTEN_ETBE    (1 << 2)    /* enable tx buffer empty int */
0055 #define DS1WM_INTEN_ETMT    (1 << 3)    /* enable tx shift register empty int */
0056 #define DS1WM_INTEN_ERBF    (1 << 4)    /* enable rx buffer full int */
0057 #define DS1WM_INTEN_ERSRF   (1 << 5)    /* enable rx shift register full int */
0058 #define DS1WM_INTEN_DQO     (1 << 6)    /* enable direct bus driving ops */
0059
0060 #define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS)  /* all but INTR active state */
0061
0062 #define DS1WM_TIMEOUT (HZ * 5)
0063
0064 static struct {
0065     unsigned long freq;
0066     unsigned long divisor;
0067 } freq[] = {
0068     {   1000000, 0x80 },
0069     {   2000000, 0x84 },
0070     {   3000000, 0x81 },
0071     {   4000000, 0x88 },
0072     {   5000000, 0x82 },
0073     {   6000000, 0x85 },
0074     {   7000000, 0x83 },
0075     {   8000000, 0x8c },
0076     {  10000000, 0x86 },
0077     {  12000000, 0x89 },
0078     {  14000000, 0x87 },
0079     {  16000000, 0x90 },
0080     {  20000000, 0x8a },
0081     {  24000000, 0x8d },
0082     {  28000000, 0x8b },
0083     {  32000000, 0x94 },
0084     {  40000000, 0x8e },
0085     {  48000000, 0x91 },
0086     {  56000000, 0x8f },
0087     {  64000000, 0x98 },
0088     {  80000000, 0x92 },
0089     {  96000000, 0x95 },
0090     { 112000000, 0x93 },
0091     { 128000000, 0x9c },
0092 /* you can continue this table, consult the OPERATION - CLOCK DIVISOR
0093    section of the ds1wm spec sheet. */
0094 };
0095
0096 struct ds1wm_data {
0097     void     __iomem *map;
0098     unsigned int      bus_shift; /* # of shifts to calc register offsets */
0099     bool      is_hw_big_endian;
0100     struct platform_device *pdev;
0101     const struct mfd_cell   *cell;
0102     int      irq;
0103     int      slave_present;
0104     void     *reset_complete;
0105     void     *read_complete;
0106     void     *write_complete;
0107     int      read_error;
0108     /* last byte received */
0109     u8       read_byte;
0110     /* byte to write that makes all intr disabled, */
0111     /* considering active_state (IAS) (optimization) */
0112     u8       int_en_reg_none;
0113     unsigned int reset_recover_delay; /* see ds1wm.h */
0114 };
0115
0116 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
0117                     u8 val)
0118 {
0119     if (ds1wm_data->is_hw_big_endian) {
0120         switch (ds1wm_data->bus_shift) {
0121         case 0:
0122             iowrite8(val, ds1wm_data->map + (reg << 0));
0123             break;
0124         case 1:
0125             iowrite16be((u16)val, ds1wm_data->map + (reg << 1));
0126             break;
0127         case 2:
0128             iowrite32be((u32)val, ds1wm_data->map + (reg << 2));
0129             break;
0130         }
0131     } else {
0132         switch (ds1wm_data->bus_shift) {
0133         case 0:
0134             iowrite8(val, ds1wm_data->map + (reg << 0));
0135             break;
0136         case 1:
0137             iowrite16((u16)val, ds1wm_data->map + (reg << 1));
0138             break;
0139         case 2:
0140             iowrite32((u32)val, ds1wm_data->map + (reg << 2));
0141             break;
0142         }
0143     }
0144 }
0145
0146 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
0147 {
0148     u32 val = 0;
0149
0150     if (ds1wm_data->is_hw_big_endian) {
0151         switch (ds1wm_data->bus_shift) {
0152         case 0:
0153             val = ioread8(ds1wm_data->map + (reg << 0));
0154             break;
0155         case 1:
0156             val = ioread16be(ds1wm_data->map + (reg << 1));
0157             break;
0158         case 2:
0159             val = ioread32be(ds1wm_data->map + (reg << 2));
0160             break;
0161         }
0162     } else {
0163         switch (ds1wm_data->bus_shift) {
0164         case 0:
0165             val = ioread8(ds1wm_data->map + (reg << 0));
0166             break;
0167         case 1:
0168             val = ioread16(ds1wm_data->map + (reg << 1));
0169             break;
0170         case 2:
0171             val = ioread32(ds1wm_data->map + (reg << 2));
0172             break;
0173         }
0174     }
0175     dev_dbg(&ds1wm_data->pdev->dev,
0176         "ds1wm_read_register reg: %d, 32 bit val:%x\n", reg, val);
0177     return (u8)val;
0178 }
0179
0180
0181 static irqreturn_t ds1wm_isr(int isr, void *data)
0182 {
0183     struct ds1wm_data *ds1wm_data = data;
0184     u8 intr;
0185     u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
0186     /* if no bits are set in int enable register (except the IAS)
0187     than go no further, reading the regs below has side effects */
0188     if (!(inten & DS1WM_INTEN_NOT_IAS))
0189         return IRQ_NONE;
0190
0191     ds1wm_write_register(ds1wm_data,
0192         DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
0193
0194     /* this read action clears the INTR and certain flags in ds1wm */
0195     intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
0196
0197     ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
0198
0199     if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
0200         inten &= ~DS1WM_INTEN_ETMT;
0201         complete(ds1wm_data->write_complete);
0202     }
0203     if (intr & DS1WM_INT_RBF) {
0204         /* this read clears the RBF flag */
0205         ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
0206         DS1WM_DATA);
0207         inten &= ~DS1WM_INTEN_ERBF;
0208         if (ds1wm_data->read_complete)
0209             complete(ds1wm_data->read_complete);
0210     }
0211     if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
0212         inten &= ~DS1WM_INTEN_EPD;
0213         complete(ds1wm_data->reset_complete);
0214     }
0215
0216     ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
0217     return IRQ_HANDLED;
0218 }
0219
0220 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
0221 {
0222     unsigned long timeleft;
0223     DECLARE_COMPLETION_ONSTACK(reset_done);
0224
0225     ds1wm_data->reset_complete = &reset_done;
0226
0227     /* enable Presence detect only */
0228     ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
0229     ds1wm_data->int_en_reg_none);
0230
0231     ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
0232
0233     timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
0234     ds1wm_data->reset_complete = NULL;
0235     if (!timeleft) {
0236         dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
0237         return 1;
0238     }
0239
0240     if (!ds1wm_data->slave_present) {
0241         dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
0242         return 1;
0243     }
0244
0245     if (ds1wm_data->reset_recover_delay)
0246         msleep(ds1wm_data->reset_recover_delay);
0247
0248     return 0;
0249 }
0250
0251 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
0252 {
0253     unsigned long timeleft;
0254     DECLARE_COMPLETION_ONSTACK(write_done);
0255     ds1wm_data->write_complete = &write_done;
0256
0257     ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
0258     ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
0259
0260     ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
0261
0262     timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
0263
0264     ds1wm_data->write_complete = NULL;
0265     if (!timeleft) {
0266         dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
0267         return -ETIMEDOUT;
0268     }
0269
0270     return 0;
0271 }
0272
0273 static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
0274 {
0275     unsigned long timeleft;
0276     u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
0277     DECLARE_COMPLETION_ONSTACK(read_done);
0278
0279     ds1wm_read_register(ds1wm_data, DS1WM_DATA);
0280
0281     ds1wm_data->read_complete = &read_done;
0282     ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
0283
0284     ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
0285     timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
0286
0287     ds1wm_data->read_complete = NULL;
0288     if (!timeleft) {
0289         dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
0290         ds1wm_data->read_error = -ETIMEDOUT;
0291         return 0xFF;
0292     }
0293     ds1wm_data->read_error = 0;
0294     return ds1wm_data->read_byte;
0295 }
0296
0297 static int ds1wm_find_divisor(int gclk)
0298 {
0299     int i;
0300
0301     for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
0302         if (gclk >= freq[i].freq)
0303             return freq[i].divisor;
0304
0305     return 0;
0306 }
0307
0308 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
0309 {
0310     int divisor;
0311     struct device *dev = &ds1wm_data->pdev->dev;
0312     struct ds1wm_driver_data *plat = dev_get_platdata(dev);
0313
0314     if (ds1wm_data->cell->enable)
0315         ds1wm_data->cell->enable(ds1wm_data->pdev);
0316
0317     divisor = ds1wm_find_divisor(plat->clock_rate);
0318     dev_dbg(dev, "found divisor 0x%x for clock %d\n",
0319         divisor, plat->clock_rate);
0320     if (divisor == 0) {
0321         dev_err(dev, "no suitable divisor for %dHz clock\n",
0322             plat->clock_rate);
0323         return;
0324     }
0325     ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
0326
0327     /* Let the w1 clock stabilize. */
0328     msleep(1);
0329
0330     ds1wm_reset(ds1wm_data);
0331 }
0332
0333 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
0334 {
0335     ds1wm_reset(ds1wm_data);
0336
0337     /* Disable interrupts. */
0338     ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
0339         ds1wm_data->int_en_reg_none);
0340
0341     if (ds1wm_data->cell->disable)
0342         ds1wm_data->cell->disable(ds1wm_data->pdev);
0343 }
0344
0345 /* --------------------------------------------------------------------- */
0346 /* w1 methods */
0347
0348 static u8 ds1wm_read_byte(void *data)
0349 {
0350     struct ds1wm_data *ds1wm_data = data;
0351
0352     return ds1wm_read(ds1wm_data, 0xff);
0353 }
0354
0355 static void ds1wm_write_byte(void *data, u8 byte)
0356 {
0357     struct ds1wm_data *ds1wm_data = data;
0358
0359     ds1wm_write(ds1wm_data, byte);
0360 }
0361
0362 static u8 ds1wm_reset_bus(void *data)
0363 {
0364     struct ds1wm_data *ds1wm_data = data;
0365
0366     ds1wm_reset(ds1wm_data);
0367
0368     return 0;
0369 }
0370
0371 static void ds1wm_search(void *data, struct w1_master *master_dev,
0372             u8 search_type, w1_slave_found_callback slave_found)
0373 {
0374     struct ds1wm_data *ds1wm_data = data;
0375     int i;
0376     int ms_discrep_bit = -1;
0377     u64 r = 0; /* holds the progress of the search */
0378     u64 r_prime, d;
0379     unsigned slaves_found = 0;
0380     unsigned int pass = 0;
0381
0382     dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
0383     while (true) {
0384         ++pass;
0385         if (pass > 100) {
0386             dev_dbg(&ds1wm_data->pdev->dev,
0387                 "too many attempts (100), search aborted\n");
0388             return;
0389         }
0390
0391         mutex_lock(&master_dev->bus_mutex);
0392         if (ds1wm_reset(ds1wm_data)) {
0393             mutex_unlock(&master_dev->bus_mutex);
0394             dev_dbg(&ds1wm_data->pdev->dev,
0395                 "pass: %d reset error (or no slaves)\n", pass);
0396             break;
0397         }
0398
0399         dev_dbg(&ds1wm_data->pdev->dev,
0400             "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
0401         ds1wm_write(ds1wm_data, search_type);
0402         dev_dbg(&ds1wm_data->pdev->dev,
0403             "pass: %d entering ASM\n", pass);
0404         ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
0405         dev_dbg(&ds1wm_data->pdev->dev,
0406             "pass: %d beginning nibble loop\n", pass);
0407
0408         r_prime = 0;
0409         d = 0;
0410         /* we work one nibble at a time */
0411         /* each nibble is interleaved to form a byte */
0412         for (i = 0; i < 16; i++) {
0413
0414             unsigned char resp, _r, _r_prime, _d;
0415
0416             _r = (r >> (4*i)) & 0xf;
0417             _r = ((_r & 0x1) << 1) |
0418             ((_r & 0x2) << 2) |
0419             ((_r & 0x4) << 3) |
0420             ((_r & 0x8) << 4);
0421
0422             /* writes _r, then reads back: */
0423             resp = ds1wm_read(ds1wm_data, _r);
0424
0425             if (ds1wm_data->read_error) {
0426                 dev_err(&ds1wm_data->pdev->dev,
0427                 "pass: %d nibble: %d read error\n", pass, i);
0428                 break;
0429             }
0430
0431             _r_prime = ((resp & 0x02) >> 1) |
0432             ((resp & 0x08) >> 2) |
0433             ((resp & 0x20) >> 3) |
0434             ((resp & 0x80) >> 4);
0435
0436             _d = ((resp & 0x01) >> 0) |
0437             ((resp & 0x04) >> 1) |
0438             ((resp & 0x10) >> 2) |
0439             ((resp & 0x40) >> 3);
0440
0441             r_prime |= (unsigned long long) _r_prime << (i * 4);
0442             d |= (unsigned long long) _d << (i * 4);
0443
0444         }
0445         if (ds1wm_data->read_error) {
0446             mutex_unlock(&master_dev->bus_mutex);
0447             dev_err(&ds1wm_data->pdev->dev,
0448                 "pass: %d read error, retrying\n", pass);
0449             break;
0450         }
0451         dev_dbg(&ds1wm_data->pdev->dev,
0452             "pass: %d r\': %0#18llx d:%0#18llx\n",
0453             pass, r_prime, d);
0454         dev_dbg(&ds1wm_data->pdev->dev,
0455             "pass: %d nibble loop complete, exiting ASM\n", pass);
0456         ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
0457         dev_dbg(&ds1wm_data->pdev->dev,
0458             "pass: %d resetting bus\n", pass);
0459         ds1wm_reset(ds1wm_data);
0460         mutex_unlock(&master_dev->bus_mutex);
0461         if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
0462             dev_err(&ds1wm_data->pdev->dev,
0463                 "pass: %d bus error, retrying\n", pass);
0464             continue; /* start over */
0465         }
0466
0467
0468         dev_dbg(&ds1wm_data->pdev->dev,
0469             "pass: %d found %0#18llx\n", pass, r_prime);
0470         slave_found(master_dev, r_prime);
0471         ++slaves_found;
0472         dev_dbg(&ds1wm_data->pdev->dev,
0473             "pass: %d complete, preparing next pass\n", pass);
0474
0475         /* any discrepency found which we already choose the
0476            '1' branch is now is now irrelevant we reveal the
0477            next branch with this: */
0478         d &= ~r;
0479         /* find last bit set, i.e. the most signif. bit set */
0480         ms_discrep_bit = fls64(d) - 1;
0481         dev_dbg(&ds1wm_data->pdev->dev,
0482             "pass: %d new d:%0#18llx MS discrep bit:%d\n",
0483             pass, d, ms_discrep_bit);
0484
0485         /* prev_ms_discrep_bit = ms_discrep_bit;
0486            prepare for next ROM search:         */
0487         if (ms_discrep_bit == -1)
0488             break;
0489
0490         r = (r &  ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
0491     } /* end while true */
0492     dev_dbg(&ds1wm_data->pdev->dev,
0493         "pass: %d total: %d search done ms d bit pos: %d\n", pass,
0494         slaves_found, ms_discrep_bit);
0495 }
0496
0497 /* --------------------------------------------------------------------- */
0498
0499 static struct w1_bus_master ds1wm_master = {
0500     .read_byte  = ds1wm_read_byte,
0501     .write_byte = ds1wm_write_byte,
0502     .reset_bus  = ds1wm_reset_bus,
0503     .search     = ds1wm_search,
0504 };
0505
0506 static int ds1wm_probe(struct platform_device *pdev)
0507 {
0508     struct ds1wm_data *ds1wm_data;
0509     struct ds1wm_driver_data *plat;
0510     struct resource *res;
0511     int ret;
0512     u8 inten;
0513
0514     if (!pdev)
0515         return -ENODEV;
0516
0517     ds1wm_data = devm_kzalloc(&pdev->dev, sizeof(*ds1wm_data), GFP_KERNEL);
0518     if (!ds1wm_data)
0519         return -ENOMEM;
0520
0521     platform_set_drvdata(pdev, ds1wm_data);
0522
0523     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0524     if (!res)
0525         return -ENXIO;
0526     ds1wm_data->map = devm_ioremap(&pdev->dev, res->start,
0527                        resource_size(res));
0528     if (!ds1wm_data->map)
0529         return -ENOMEM;
0530
0531     ds1wm_data->pdev = pdev;
0532     ds1wm_data->cell = mfd_get_cell(pdev);
0533     if (!ds1wm_data->cell)
0534         return -ENODEV;
0535     plat = dev_get_platdata(&pdev->dev);
0536     if (!plat)
0537         return -ENODEV;
0538
0539     /* how many bits to shift register number to get register offset */
0540     if (plat->bus_shift > 2) {
0541         dev_err(&ds1wm_data->pdev->dev,
0542             "illegal bus shift %d, not written",
0543             ds1wm_data->bus_shift);
0544         return -EINVAL;
0545     }
0546
0547     ds1wm_data->bus_shift = plat->bus_shift;
0548     /* make sure resource has space for 8 registers */
0549     if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
0550         dev_err(&ds1wm_data->pdev->dev,
0551             "memory resource size %d to small, should be %d\n",
0552             (int)resource_size(res),
0553             8 << ds1wm_data->bus_shift);
0554         return -EINVAL;
0555     }
0556
0557     ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian;
0558
0559     res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
0560     if (!res)
0561         return -ENXIO;
0562     ds1wm_data->irq = res->start;
0563     ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
0564     ds1wm_data->reset_recover_delay = plat->reset_recover_delay;
0565
0566     /* Mask interrupts, set IAS before claiming interrupt */
0567     inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
0568     ds1wm_write_register(ds1wm_data,
0569         DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
0570
0571     if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
0572         irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
0573     if (res->flags & IORESOURCE_IRQ_LOWEDGE)
0574         irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
0575     if (res->flags & IORESOURCE_IRQ_HIGHLEVEL)
0576         irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_HIGH);
0577     if (res->flags & IORESOURCE_IRQ_LOWLEVEL)
0578         irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_LOW);
0579
0580     ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
0581             IRQF_SHARED, "ds1wm", ds1wm_data);
0582     if (ret) {
0583         dev_err(&ds1wm_data->pdev->dev,
0584             "devm_request_irq %d failed with errno %d\n",
0585             ds1wm_data->irq,
0586             ret);
0587
0588         return ret;
0589     }
0590
0591     ds1wm_up(ds1wm_data);
0592
0593     ds1wm_master.data = (void *)ds1wm_data;
0594
0595     ret = w1_add_master_device(&ds1wm_master);
0596     if (ret)
0597         goto err;
0598
0599     dev_dbg(&ds1wm_data->pdev->dev,
0600         "ds1wm: probe successful, IAS: %d, rec.delay: %d, clockrate: %d, bus-shift: %d, is Hw Big Endian: %d\n",
0601         plat->active_high,
0602         plat->reset_recover_delay,
0603         plat->clock_rate,
0604         ds1wm_data->bus_shift,
0605         ds1wm_data->is_hw_big_endian);
0606     return 0;
0607
0608 err:
0609     ds1wm_down(ds1wm_data);
0610
0611     return ret;
0612 }
0613
0614 #ifdef CONFIG_PM
0615 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
0616 {
0617     struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
0618
0619     ds1wm_down(ds1wm_data);
0620
0621     return 0;
0622 }
0623
0624 static int ds1wm_resume(struct platform_device *pdev)
0625 {
0626     struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
0627
0628     ds1wm_up(ds1wm_data);
0629
0630     return 0;
0631 }
0632 #else
0633 #define ds1wm_suspend NULL
0634 #define ds1wm_resume NULL
0635 #endif
0636
0637 static int ds1wm_remove(struct platform_device *pdev)
0638 {
0639     struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
0640
0641     w1_remove_master_device(&ds1wm_master);
0642     ds1wm_down(ds1wm_data);
0643
0644     return 0;
0645 }
0646
0647 static struct platform_driver ds1wm_driver = {
0648     .driver   = {
0649         .name = "ds1wm",
0650     },
0651     .probe    = ds1wm_probe,
0652     .remove   = ds1wm_remove,
0653     .suspend  = ds1wm_suspend,
0654     .resume   = ds1wm_resume
0655 };
0656
0657 static int __init ds1wm_init(void)
0658 {
0659     pr_info("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
0660     return platform_driver_register(&ds1wm_driver);
0661 }
0662
0663 static void __exit ds1wm_exit(void)
0664 {
0665     platform_driver_unregister(&ds1wm_driver);
0666 }
0667
0668 module_init(ds1wm_init);
0669 module_exit(ds1wm_exit);
0670
0671 MODULE_LICENSE("GPL");
0672 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
0673     "Matt Reimer <mreimer@vpop.net>,"
0674     "Jean-Francois Dagenais <dagenaisj@sonatest.com>");
0675 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");