video/fbdev/wm8505fb_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  GOVR registers list for WM8505 chips
0004  *
0005  *  Copyright (C) 2010 Ed Spiridonov <edo.rus@gmail.com>
0006  *   Based on VIA/WonderMedia wm8510-govrh-reg.h
0007  *   http://github.com/projectgus/kernel_wm8505/blob/wm8505_2.6.29/
0008  *         drivers/video/wmt/register/wm8510/wm8510-govrh-reg.h
0009  */
0010
0011 #ifndef _WM8505FB_REGS_H
0012 #define _WM8505FB_REGS_H
0013
0014 /*
0015  * Color space select register, default value 0x1c
0016  *   BIT0 GOVRH_DVO_YUV2RGB_ENABLE
0017  *   BIT1 GOVRH_VGA_YUV2RGB_ENABLE
0018  *   BIT2 GOVRH_RGB_MODE
0019  *   BIT3 GOVRH_DAC_CLKINV
0020  *   BIT4 GOVRH_BLANK_ZERO
0021  */
0022 #define WMT_GOVR_COLORSPACE 0x1e4
0023 /*
0024  * Another colorspace select register, default value 1
0025  *   BIT0 GOVRH_DVO_RGB
0026  *   BIT1 GOVRH_DVO_YUV422
0027  */
0028 #define WMT_GOVR_COLORSPACE1     0x30
0029
0030 #define WMT_GOVR_CONTRAST   0x1b8
0031 #define WMT_GOVR_BRGHTNESS  0x1bc /* incompatible with RGB? */
0032
0033 /* Framubeffer address */
0034 #define WMT_GOVR_FBADDR      0x90
0035 #define WMT_GOVR_FBADDR1     0x94 /* UV offset in YUV mode */
0036
0037 /* Offset of visible window */
0038 #define WMT_GOVR_XPAN        0xa4
0039 #define WMT_GOVR_YPAN        0xa0
0040
0041 #define WMT_GOVR_XRES        0x98
0042 #define WMT_GOVR_XRES_VIRTUAL    0x9c
0043
0044 #define WMT_GOVR_MIF_ENABLE  0x80
0045 #define WMT_GOVR_FHI         0xa8
0046 #define WMT_GOVR_REG_UPDATE  0xe4
0047
0048 /*
0049  *   BIT0 GOVRH_DVO_OUTWIDTH
0050  *   BIT1 GOVRH_DVO_SYNC_POLAR
0051  *   BIT2 GOVRH_DVO_ENABLE
0052  */
0053 #define WMT_GOVR_DVO_SET    0x148
0054
0055 /* Timing generator? */
0056 #define WMT_GOVR_TG     0x100
0057
0058 /* Timings */
0059 #define WMT_GOVR_TIMING_H_ALL   0x108
0060 #define WMT_GOVR_TIMING_V_ALL   0x10c
0061 #define WMT_GOVR_TIMING_V_START 0x110
0062 #define WMT_GOVR_TIMING_V_END   0x114
0063 #define WMT_GOVR_TIMING_H_START 0x118
0064 #define WMT_GOVR_TIMING_H_END   0x11c
0065 #define WMT_GOVR_TIMING_V_SYNC  0x128
0066 #define WMT_GOVR_TIMING_H_SYNC  0x12c
0067
0068 #endif /* _WM8505FB_REGS_H */