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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
0004  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
0005 
0006  */
0007 
0008 #include <linux/via-core.h>
0009 #include "global.h"
0010 
0011 struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
0012 {VIASR, SR15, 0x02, 0x02},
0013 {VIASR, SR16, 0xBF, 0x08},
0014 {VIASR, SR17, 0xFF, 0x1F},
0015 {VIASR, SR18, 0xFF, 0x4E},
0016 {VIASR, SR1A, 0xFB, 0x08},
0017 {VIASR, SR1E, 0x0F, 0x01},
0018 {VIASR, SR2A, 0xFF, 0x00},
0019 {VIACR, CR32, 0xFF, 0x00},
0020 {VIACR, CR33, 0xFF, 0x00},
0021 {VIACR, CR35, 0xFF, 0x00},
0022 {VIACR, CR36, 0x08, 0x00},
0023 {VIACR, CR69, 0xFF, 0x00},
0024 {VIACR, CR6A, 0xFF, 0x40},
0025 {VIACR, CR6B, 0xFF, 0x00},
0026 {VIACR, CR88, 0xFF, 0x40},  /* LCD Panel Type                      */
0027 {VIACR, CR89, 0xFF, 0x00},  /* LCD Timing Control 0                */
0028 {VIACR, CR8A, 0xFF, 0x88},  /* LCD Timing Control 1                */
0029 {VIACR, CR8B, 0xFF, 0x69},  /* LCD Power Sequence Control 0        */
0030 {VIACR, CR8C, 0xFF, 0x57},  /* LCD Power Sequence Control 1        */
0031 {VIACR, CR8D, 0xFF, 0x00},  /* LCD Power Sequence Control 2        */
0032 {VIACR, CR8E, 0xFF, 0x7B},  /* LCD Power Sequence Control 3        */
0033 {VIACR, CR8F, 0xFF, 0x03},  /* LCD Power Sequence Control 4        */
0034 {VIACR, CR90, 0xFF, 0x30},  /* LCD Power Sequence Control 5        */
0035 {VIACR, CR91, 0xFF, 0xA0},  /* 24/12 bit LVDS Data off             */
0036 {VIACR, CR96, 0xFF, 0x00},
0037 {VIACR, CR97, 0xFF, 0x00},
0038 {VIACR, CR99, 0xFF, 0x00},
0039 {VIACR, CR9B, 0xFF, 0x00}
0040 };
0041 
0042 /* Video Mode Table for VT3314 chipset*/
0043 /* Common Setting for Video Mode */
0044 struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
0045 {VIASR, SR15, 0x02, 0x02},
0046 {VIASR, SR16, 0xBF, 0x08},
0047 {VIASR, SR17, 0xFF, 0x1F},
0048 {VIASR, SR18, 0xFF, 0x4E},
0049 {VIASR, SR1A, 0xFB, 0x82},
0050 {VIASR, SR1B, 0xFF, 0xF0},
0051 {VIASR, SR1F, 0xFF, 0x00},
0052 {VIASR, SR1E, 0xFF, 0x01},
0053 {VIASR, SR22, 0xFF, 0x1F},
0054 {VIASR, SR2A, 0x0F, 0x00},
0055 {VIASR, SR2E, 0xFF, 0xFF},
0056 {VIASR, SR3F, 0xFF, 0xFF},
0057 {VIASR, SR40, 0xF7, 0x00},
0058 {VIASR, CR30, 0xFF, 0x04},
0059 {VIACR, CR32, 0xFF, 0x00},
0060 {VIACR, CR33, 0x7F, 0x00},
0061 {VIACR, CR35, 0xFF, 0x00},
0062 {VIACR, CR36, 0xFF, 0x31},
0063 {VIACR, CR41, 0xFF, 0x80},
0064 {VIACR, CR42, 0xFF, 0x00},
0065 {VIACR, CR55, 0x80, 0x00},
0066 {VIACR, CR5D, 0x80, 0x00},  /*Horizontal Retrace Start bit[11] should be 0*/
0067 {VIACR, CR68, 0xFF, 0x67},  /* Default FIFO For IGA2 */
0068 {VIACR, CR69, 0xFF, 0x00},
0069 {VIACR, CR6A, 0xFD, 0x40},
0070 {VIACR, CR6B, 0xFF, 0x00},
0071 {VIACR, CR77, 0xFF, 0x00},  /* LCD scaling Factor */
0072 {VIACR, CR78, 0xFF, 0x00},  /* LCD scaling Factor */
0073 {VIACR, CR79, 0xFF, 0x00},  /* LCD scaling Factor */
0074 {VIACR, CR9F, 0x03, 0x00},  /* LCD scaling Factor */
0075 {VIACR, CR88, 0xFF, 0x40},  /* LCD Panel Type */
0076 {VIACR, CR89, 0xFF, 0x00},  /* LCD Timing Control 0 */
0077 {VIACR, CR8A, 0xFF, 0x88},  /* LCD Timing Control 1 */
0078 {VIACR, CR8B, 0xFF, 0x5D},  /* LCD Power Sequence Control 0 */
0079 {VIACR, CR8C, 0xFF, 0x2B},  /* LCD Power Sequence Control 1 */
0080 {VIACR, CR8D, 0xFF, 0x6F},  /* LCD Power Sequence Control 2 */
0081 {VIACR, CR8E, 0xFF, 0x2B},  /* LCD Power Sequence Control 3 */
0082 {VIACR, CR8F, 0xFF, 0x01},  /* LCD Power Sequence Control 4 */
0083 {VIACR, CR90, 0xFF, 0x01},  /* LCD Power Sequence Control 5 */
0084 {VIACR, CR91, 0xFF, 0xA0},  /* 24/12 bit LVDS Data off */
0085 {VIACR, CR96, 0xFF, 0x00},
0086 {VIACR, CR97, 0xFF, 0x00},
0087 {VIACR, CR99, 0xFF, 0x00},
0088 {VIACR, CR9B, 0xFF, 0x00},
0089 {VIACR, CR9D, 0xFF, 0x80},
0090 {VIACR, CR9E, 0xFF, 0x80}
0091 };
0092 
0093 struct io_reg KM400_ModeXregs[] = {
0094     {VIASR, SR10, 0xFF, 0x01},  /* Unlock Register                 */
0095     {VIASR, SR16, 0xFF, 0x08},  /* Display FIFO threshold Control  */
0096     {VIASR, SR17, 0xFF, 0x1F},  /* Display FIFO Control            */
0097     {VIASR, SR18, 0xFF, 0x4E},  /* GFX PREQ threshold              */
0098     {VIASR, SR1A, 0xFF, 0x0a},  /* GFX PREQ threshold              */
0099     {VIASR, SR1F, 0xFF, 0x00},  /* Memory Control 0                */
0100     {VIASR, SR1B, 0xFF, 0xF0},  /* Power Management Control 0      */
0101     {VIASR, SR1E, 0xFF, 0x01},  /* Power Management Control        */
0102     {VIASR, SR20, 0xFF, 0x00},  /* Sequencer Arbiter Control 0     */
0103     {VIASR, SR21, 0xFF, 0x00},  /* Sequencer Arbiter Control 1     */
0104     {VIASR, SR22, 0xFF, 0x1F},  /* Display Arbiter Control 1       */
0105     {VIASR, SR2A, 0xFF, 0x00},  /* Power Management Control 5      */
0106     {VIASR, SR2D, 0xFF, 0xFF},  /* Power Management Control 1      */
0107     {VIASR, SR2E, 0xFF, 0xFF},  /* Power Management Control 2      */
0108     {VIACR, CR33, 0xFF, 0x00},
0109     {VIACR, CR55, 0x80, 0x00},
0110     {VIACR, CR5D, 0x80, 0x00},
0111     {VIACR, CR36, 0xFF, 0x01},  /* Power Mangement 3                  */
0112     {VIACR, CR68, 0xFF, 0x67},  /* Default FIFO For IGA2              */
0113     {VIACR, CR6A, 0x20, 0x20},  /* Extended FIFO On                   */
0114     {VIACR, CR88, 0xFF, 0x40},  /* LCD Panel Type                     */
0115     {VIACR, CR89, 0xFF, 0x00},  /* LCD Timing Control 0               */
0116     {VIACR, CR8A, 0xFF, 0x88},  /* LCD Timing Control 1               */
0117     {VIACR, CR8B, 0xFF, 0x2D},  /* LCD Power Sequence Control 0       */
0118     {VIACR, CR8C, 0xFF, 0x2D},  /* LCD Power Sequence Control 1       */
0119     {VIACR, CR8D, 0xFF, 0xC8},  /* LCD Power Sequence Control 2       */
0120     {VIACR, CR8E, 0xFF, 0x36},  /* LCD Power Sequence Control 3       */
0121     {VIACR, CR8F, 0xFF, 0x00},  /* LCD Power Sequence Control 4       */
0122     {VIACR, CR90, 0xFF, 0x10},  /* LCD Power Sequence Control 5       */
0123     {VIACR, CR91, 0xFF, 0xA0},  /* 24/12 bit LVDS Data off            */
0124     {VIACR, CR96, 0xFF, 0x03},  /* DVP0        ; DVP0 Clock Skew */
0125     {VIACR, CR97, 0xFF, 0x03},  /* DFP high    ; DFPH Clock Skew */
0126     {VIACR, CR99, 0xFF, 0x03},  /* DFP low           ; DFPL Clock Skew*/
0127     {VIACR, CR9B, 0xFF, 0x07}   /* DVI on DVP1       ; DVP1 Clock Skew*/
0128 };
0129 
0130 /* For VT3324: Common Setting for Video Mode */
0131 struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
0132 {VIASR, SR15, 0x02, 0x02},
0133 {VIASR, SR16, 0xBF, 0x08},
0134 {VIASR, SR17, 0xFF, 0x1F},
0135 {VIASR, SR18, 0xFF, 0x4E},
0136 {VIASR, SR1A, 0xFB, 0x08},
0137 {VIASR, SR1B, 0xFF, 0xF0},
0138 {VIASR, SR1E, 0xFF, 0x01},
0139 {VIASR, SR2A, 0xFF, 0x00},
0140 {VIASR, SR2D, 0xC0, 0xC0},  /* delayed E3_ECK */
0141 {VIACR, CR32, 0xFF, 0x00},
0142 {VIACR, CR33, 0xFF, 0x00},
0143 {VIACR, CR35, 0xFF, 0x00},
0144 {VIACR, CR36, 0x08, 0x00},
0145 {VIACR, CR47, 0xC8, 0x00},  /* Clear VCK Plus. */
0146 {VIACR, CR69, 0xFF, 0x00},
0147 {VIACR, CR6A, 0xFF, 0x40},
0148 {VIACR, CR6B, 0xFF, 0x00},
0149 {VIACR, CR88, 0xFF, 0x40},  /* LCD Panel Type                      */
0150 {VIACR, CR89, 0xFF, 0x00},  /* LCD Timing Control 0                */
0151 {VIACR, CR8A, 0xFF, 0x88},  /* LCD Timing Control 1                */
0152 {VIACR, CRD4, 0xFF, 0x81},  /* Second power sequence control       */
0153 {VIACR, CR8B, 0xFF, 0x5D},  /* LCD Power Sequence Control 0        */
0154 {VIACR, CR8C, 0xFF, 0x2B},  /* LCD Power Sequence Control 1        */
0155 {VIACR, CR8D, 0xFF, 0x6F},  /* LCD Power Sequence Control 2        */
0156 {VIACR, CR8E, 0xFF, 0x2B},  /* LCD Power Sequence Control 3        */
0157 {VIACR, CR8F, 0xFF, 0x01},  /* LCD Power Sequence Control 4        */
0158 {VIACR, CR90, 0xFF, 0x01},  /* LCD Power Sequence Control 5        */
0159 {VIACR, CR91, 0xFF, 0x80},  /* 24/12 bit LVDS Data off             */
0160 {VIACR, CR96, 0xFF, 0x00},
0161 {VIACR, CR97, 0xFF, 0x00},
0162 {VIACR, CR99, 0xFF, 0x00},
0163 {VIACR, CR9B, 0xFF, 0x00}
0164 };
0165 
0166 struct io_reg VX855_ModeXregs[] = {
0167 {VIASR, SR10, 0xFF, 0x01},
0168 {VIASR, SR15, 0x02, 0x02},
0169 {VIASR, SR16, 0xBF, 0x08},
0170 {VIASR, SR17, 0xFF, 0x1F},
0171 {VIASR, SR18, 0xFF, 0x4E},
0172 {VIASR, SR1A, 0xFB, 0x08},
0173 {VIASR, SR1B, 0xFF, 0xF0},
0174 {VIASR, SR1E, 0x07, 0x01},
0175 {VIASR, SR2A, 0xF0, 0x00},
0176 {VIASR, SR58, 0xFF, 0x00},
0177 {VIASR, SR59, 0xFF, 0x00},
0178 {VIASR, SR2D, 0xC0, 0xC0},  /* delayed E3_ECK */
0179 {VIACR, CR32, 0xFF, 0x00},
0180 {VIACR, CR33, 0x7F, 0x00},
0181 {VIACR, CR35, 0xFF, 0x00},
0182 {VIACR, CR36, 0x08, 0x00},
0183 {VIACR, CR69, 0xFF, 0x00},
0184 {VIACR, CR6A, 0xFD, 0x60},
0185 {VIACR, CR6B, 0xFF, 0x00},
0186 {VIACR, CR88, 0xFF, 0x40},          /* LCD Panel Type                      */
0187 {VIACR, CR89, 0xFF, 0x00},          /* LCD Timing Control 0                */
0188 {VIACR, CR8A, 0xFF, 0x88},          /* LCD Timing Control 1                */
0189 {VIACR, CRD4, 0xFF, 0x81},          /* Second power sequence control       */
0190 {VIACR, CR91, 0xFF, 0x80},          /* 24/12 bit LVDS Data off             */
0191 {VIACR, CR96, 0xFF, 0x00},
0192 {VIACR, CR97, 0xFF, 0x00},
0193 {VIACR, CR99, 0xFF, 0x00},
0194 {VIACR, CR9B, 0xFF, 0x00},
0195 {VIACR, CRD2, 0xFF, 0xFF}           /* TMDS/LVDS control register.         */
0196 };
0197 
0198 /* Video Mode Table */
0199 /* Common Setting for Video Mode */
0200 struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
0201 {VIASR, SR2A, 0x0F, 0x00},
0202 {VIASR, SR15, 0x02, 0x02},
0203 {VIASR, SR16, 0xBF, 0x08},
0204 {VIASR, SR17, 0xFF, 0x1F},
0205 {VIASR, SR18, 0xFF, 0x4E},
0206 {VIASR, SR1A, 0xFB, 0x08},
0207 
0208 {VIACR, CR32, 0xFF, 0x00},
0209 {VIACR, CR35, 0xFF, 0x00},
0210 {VIACR, CR36, 0x08, 0x00},
0211 {VIACR, CR6A, 0xFF, 0x80},
0212 {VIACR, CR6A, 0xFF, 0xC0},
0213 
0214 {VIACR, CR55, 0x80, 0x00},
0215 {VIACR, CR5D, 0x80, 0x00},
0216 
0217 {VIAGR, GR20, 0xFF, 0x00},
0218 {VIAGR, GR21, 0xFF, 0x00},
0219 {VIAGR, GR22, 0xFF, 0x00},
0220 
0221 };
0222 
0223 /* Mode:1024X768 */
0224 struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
0225 {VIASR, 0x18, 0xFF, 0x4C}
0226 };
0227 
0228 struct patch_table res_patch_table[] = {
0229     {ARRAY_SIZE(PM1024x768), PM1024x768}
0230 };
0231 
0232 /* struct VPITTable {
0233     unsigned char  Misc;
0234     unsigned char  SR[StdSR];
0235     unsigned char  CR[StdCR];
0236     unsigned char  GR[StdGR];
0237     unsigned char  AR[StdAR];
0238  };*/
0239 
0240 struct VPITTable VPIT = {
0241     /* Msic */
0242     0xC7,
0243     /* Sequencer */
0244     {0x01, 0x0F, 0x00, 0x0E},
0245     /* Graphic Controller */
0246     {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
0247     /* Attribute Controller */
0248     {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0249      0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0250      0x01, 0x00, 0x0F, 0x00}
0251 };
0252 
0253 /********************/
0254 /* Mode Table       */
0255 /********************/
0256 
0257 static const struct fb_videomode viafb_modes[] = {
0258     {NULL, 60, 480, 640, 40285, 72, 24, 19, 1, 48, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0259     {NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 0},
0260     {NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0, 0, 0},
0261     {NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, 0, 0, 0},
0262     {NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0263     {NULL, 120, 640, 480, 19081, 104, 40, 31, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0264     {NULL, 60, 720, 480, 37426, 88, 16, 13, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0265     {NULL, 60, 720, 576, 30611, 96, 24, 17, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0266     {NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0267     {NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0268     {NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0269     {NULL, 100, 800, 600, 14667, 136, 48, 32, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0270     {NULL, 120, 800, 600, 11911, 144, 56, 39, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0271     {NULL, 60, 800, 480, 33602, 96, 24, 10, 3, 72, 7, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0272     {NULL, 60, 848, 480, 31565, 104, 24, 12, 3, 80, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0273     {NULL, 60, 856, 480, 31517, 104, 16, 13, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0274     {NULL, 60, 1024, 512, 24218, 136, 32, 15, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0275     {NULL, 60, 1024, 600, 20423, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0276     {NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, 0, 0, 0},
0277     {NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0278     {NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0279     {NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0280     {NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0281     {NULL, 60, 1280, 768, 12478, 200, 64, 23, 1, 136, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0282     {NULL, 50, 1280, 768, 15342, 184, 56, 19, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0283     {NULL, 60, 960, 600, 21964, 128, 32, 15, 3, 96, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0284     {NULL, 60, 1000, 600, 20803, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0285     {NULL, 60, 1024, 576, 21278, 144, 40, 17, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0286     {NULL, 60, 1088, 612, 18825, 152, 48, 16, 3, 104, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0287     {NULL, 60, 1152, 720, 14974, 168, 56, 19, 3, 112, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0288     {NULL, 60, 1200, 720, 14248, 184, 56, 22, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0289     {NULL, 49, 1200, 900, 17703, 21, 11, 1, 1, 32, 10, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0290     {NULL, 60, 1280, 600, 16259, 184, 56, 18, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0291     {NULL, 60, 1280, 800, 11938, 200, 72, 22, 3, 128, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0292     {NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0293     {NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0294     {NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0295     {NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0296     {NULL, 60, 1360, 768, 11759, 208, 72, 22, 3, 136, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0297     {NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0298     {NULL, 50, 1368, 768, 14301, 200, 56, 19, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0299     {NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0300     {NULL, 60, 1440, 900, 9372, 232, 80, 25, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0301     {NULL, 75, 1440, 900, 7311, 248, 96, 33, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0302     {NULL, 60, 1440, 1040, 7993, 248, 96, 33, 1, 152, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0303     {NULL, 60, 1600, 900, 8449, 256, 88, 26, 3, 168, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0304     {NULL, 60, 1600, 1024, 7333, 272, 104, 32, 1, 168, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0305     {NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0306     {NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
0307     {NULL, 60, 1680, 1050, 6832, 280, 104, 30, 3, 176, 6, 0, 0, 0},
0308     {NULL, 75, 1680, 1050, 5339, 296, 120, 40, 3, 176, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0309     {NULL, 60, 1792, 1344, 4883, 328, 128, 46, 1, 200, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0310     {NULL, 60, 1856, 1392, 4581, 352, 96, 43, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0311     {NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0312     {NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0313     {NULL, 60, 2048, 1536, 3738, 376, 152, 49, 3, 224, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0314     {NULL, 60, 1280, 720, 13484, 216, 112, 20, 5, 40, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0315     {NULL, 50, 1280, 720, 16538, 176, 48, 17, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0316     {NULL, 60, 1920, 1080, 5776, 328, 128, 32, 3, 200, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0317     {NULL, 60, 1920, 1200, 5164, 336, 136, 36, 3, 200, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0318     {NULL, 60, 1400, 1050, 8210, 232, 88, 32, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0},
0319     {NULL, 75, 1400, 1050, 6398, 248, 104, 42, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0} };
0320 
0321 static const struct fb_videomode viafb_rb_modes[] = {
0322     {NULL, 60, 1360, 768, 13879, 80, 48, 14, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
0323     {NULL, 60, 1440, 900, 11249, 80, 48, 17, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0},
0324     {NULL, 60, 1400, 1050, 9892, 80, 48, 23, 3, 32, 4, FB_SYNC_HOR_HIGH_ACT, 0, 0},
0325     {NULL, 60, 1600, 900, 10226, 80, 48, 18, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
0326     {NULL, 60, 1680, 1050, 8387, 80, 48, 21, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0},
0327     {NULL, 60, 1920, 1080, 7212, 80, 48, 23, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
0328     {NULL, 60, 1920, 1200, 6488, 80, 48, 26, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0} };
0329 
0330 int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
0331 int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
0332 int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
0333 int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
0334 int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
0335 int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
0336 int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
0337 
0338 
0339 static const struct fb_videomode *get_best_mode(
0340     const struct fb_videomode *modes, int n,
0341     int hres, int vres, int refresh)
0342 {
0343     const struct fb_videomode *best = NULL;
0344     int i;
0345 
0346     for (i = 0; i < n; i++) {
0347         if (modes[i].xres != hres || modes[i].yres != vres)
0348             continue;
0349 
0350         if (!best || abs(modes[i].refresh - refresh) <
0351             abs(best->refresh - refresh))
0352             best = &modes[i];
0353     }
0354 
0355     return best;
0356 }
0357 
0358 const struct fb_videomode *viafb_get_best_mode(int hres, int vres, int refresh)
0359 {
0360     return get_best_mode(viafb_modes, ARRAY_SIZE(viafb_modes),
0361         hres, vres, refresh);
0362 }
0363 
0364 const struct fb_videomode *viafb_get_best_rb_mode(int hres, int vres,
0365     int refresh)
0366 {
0367     return get_best_mode(viafb_rb_modes, ARRAY_SIZE(viafb_rb_modes),
0368         hres, vres, refresh);
0369 }
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