fbdev/via/via_clock.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
0004  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
0005  * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
0006  */
0007 /*
0008  * clock and PLL management functions
0009  */
0010
0011 #ifndef __VIA_CLOCK_H__
0012 #define __VIA_CLOCK_H__
0013
0014 #include <linux/types.h>
0015
0016 enum via_clksrc {
0017     VIA_CLKSRC_X1 = 0,
0018     VIA_CLKSRC_TVX1,
0019     VIA_CLKSRC_TVPLL,
0020     VIA_CLKSRC_DVP1TVCLKR,
0021     VIA_CLKSRC_CAP0,
0022     VIA_CLKSRC_CAP1,
0023 };
0024
0025 struct via_pll_config {
0026     u16 multiplier;
0027     u8 divisor;
0028     u8 rshift;
0029 };
0030
0031 struct via_clock {
0032     void (*set_primary_clock_state)(u8 state);
0033     void (*set_primary_clock_source)(enum via_clksrc src, bool use_pll);
0034     void (*set_primary_pll_state)(u8 state);
0035     void (*set_primary_pll)(struct via_pll_config config);
0036
0037     void (*set_secondary_clock_state)(u8 state);
0038     void (*set_secondary_clock_source)(enum via_clksrc src, bool use_pll);
0039     void (*set_secondary_pll_state)(u8 state);
0040     void (*set_secondary_pll)(struct via_pll_config config);
0041
0042     void (*set_engine_pll_state)(u8 state);
0043     void (*set_engine_pll)(struct via_pll_config config);
0044 };
0045
0046
0047 static inline u32 get_pll_internal_frequency(u32 ref_freq,
0048     struct via_pll_config pll)
0049 {
0050     return ref_freq / pll.divisor * pll.multiplier;
0051 }
0052
0053 static inline u32 get_pll_output_frequency(u32 ref_freq,
0054     struct via_pll_config pll)
0055 {
0056     return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift;
0057 }
0058
0059 void via_clock_init(struct via_clock *clock, int gfx_chip);
0060
0061 #endif /* __VIA_CLOCK_H__ */