fbdev/via/hw.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
0004  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
0005
0006  */
0007
0008 #ifndef __HW_H__
0009 #define __HW_H__
0010
0011 #include <linux/seq_file.h>
0012
0013 #include "viamode.h"
0014 #include "global.h"
0015 #include "via_modesetting.h"
0016
0017 #define viafb_read_reg(p, i)            via_read_reg(p, i)
0018 #define viafb_write_reg(i, p, d)        via_write_reg(p, i, d)
0019 #define viafb_write_reg_mask(i, p, d, m)    via_write_reg_mask(p, i, d, m)
0020
0021 /* VIA output devices */
0022 #define VIA_LDVP0   0x00000001
0023 #define VIA_LDVP1   0x00000002
0024 #define VIA_DVP0    0x00000004
0025 #define VIA_CRT     0x00000010
0026 #define VIA_DVP1    0x00000020
0027 #define VIA_LVDS1   0x00000040
0028 #define VIA_LVDS2   0x00000080
0029
0030 /* VIA output device power states */
0031 #define VIA_STATE_ON        0
0032 #define VIA_STATE_STANDBY   1
0033 #define VIA_STATE_SUSPEND   2
0034 #define VIA_STATE_OFF       3
0035
0036 /* VIA output device sync polarity */
0037 #define VIA_HSYNC_NEGATIVE  0x01
0038 #define VIA_VSYNC_NEGATIVE  0x02
0039
0040 /**********************************************************/
0041 /* Definition IGA2 Design Method of CRTC Shadow Registers */
0042 /**********************************************************/
0043 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x)           ((x/8)-5)
0044 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y)     (((x+y)/8)-1)
0045 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x)           ((x)-2)
0046 #define IGA2_VER_ADDR_SHADOW_FORMULA(x)            ((x)-1)
0047 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x)     ((x)-1)
0048 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y)     ((x+y)-1)
0049 #define IGA2_VER_SYNC_START_SHADOW_FORMULA(x)      (x)
0050 #define IGA2_VER_SYNC_END_SHADOW_FORMULA(x, y)      (x+y)
0051
0052 /* Define Register Number for IGA2 Shadow CRTC Timing */
0053
0054 /* location: {CR6D,0,7},{CR71,3,3} */
0055 #define IGA2_SHADOW_HOR_TOTAL_REG_NUM       2
0056 /* location: {CR6E,0,7} */
0057 #define IGA2_SHADOW_HOR_BLANK_END_REG_NUM   1
0058 /* location: {CR6F,0,7},{CR71,0,2} */
0059 #define IGA2_SHADOW_VER_TOTAL_REG_NUM       2
0060 /* location: {CR70,0,7},{CR71,4,6} */
0061 #define IGA2_SHADOW_VER_ADDR_REG_NUM        2
0062 /* location: {CR72,0,7},{CR74,4,6} */
0063 #define IGA2_SHADOW_VER_BLANK_START_REG_NUM 2
0064 /* location: {CR73,0,7},{CR74,0,2} */
0065 #define IGA2_SHADOW_VER_BLANK_END_REG_NUM   2
0066 /* location: {CR75,0,7},{CR76,4,6} */
0067 #define IGA2_SHADOW_VER_SYNC_START_REG_NUM  2
0068 /* location: {CR76,0,3} */
0069 #define IGA2_SHADOW_VER_SYNC_END_REG_NUM    1
0070
0071 /* Define Fetch Count Register*/
0072
0073 /* location: {SR1C,0,7},{SR1D,0,1} */
0074 #define IGA1_FETCH_COUNT_REG_NUM        2
0075 /* 16 bytes alignment. */
0076 #define IGA1_FETCH_COUNT_ALIGN_BYTE     16
0077 /* x: H resolution, y: color depth */
0078 #define IGA1_FETCH_COUNT_PATCH_VALUE    4
0079 #define IGA1_FETCH_COUNT_FORMULA(x, y)   \
0080     (((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
0081
0082 /* location: {CR65,0,7},{CR67,2,3} */
0083 #define IGA2_FETCH_COUNT_REG_NUM        2
0084 #define IGA2_FETCH_COUNT_ALIGN_BYTE     16
0085 #define IGA2_FETCH_COUNT_PATCH_VALUE    0
0086 #define IGA2_FETCH_COUNT_FORMULA(x, y)   \
0087     (((x*y)/IGA2_FETCH_COUNT_ALIGN_BYTE) + IGA2_FETCH_COUNT_PATCH_VALUE)
0088
0089 /* Staring Address*/
0090
0091 /* location: {CR0C,0,7},{CR0D,0,7},{CR34,0,7},{CR48,0,1} */
0092 #define IGA1_STARTING_ADDR_REG_NUM      4
0093 /* location: {CR62,1,7},{CR63,0,7},{CR64,0,7} */
0094 #define IGA2_STARTING_ADDR_REG_NUM      3
0095
0096 /* Define Display OFFSET*/
0097 /* These value are by HW suggested value*/
0098 /* location: {SR17,0,7} */
0099 #define K800_IGA1_FIFO_MAX_DEPTH                384
0100 /* location: {SR16,0,5},{SR16,7,7} */
0101 #define K800_IGA1_FIFO_THRESHOLD                328
0102 /* location: {SR18,0,5},{SR18,7,7} */
0103 #define K800_IGA1_FIFO_HIGH_THRESHOLD           296
0104 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
0105                 /* because HW only 5 bits */
0106 #define K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
0107
0108 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0109 #define K800_IGA2_FIFO_MAX_DEPTH                384
0110 /* location: {CR68,0,3},{CR95,4,6} */
0111 #define K800_IGA2_FIFO_THRESHOLD                328
0112 /* location: {CR92,0,3},{CR95,0,2} */
0113 #define K800_IGA2_FIFO_HIGH_THRESHOLD           296
0114 /* location: {CR94,0,6} */
0115 #define K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
0116
0117 /* location: {SR17,0,7} */
0118 #define P880_IGA1_FIFO_MAX_DEPTH                192
0119 /* location: {SR16,0,5},{SR16,7,7} */
0120 #define P880_IGA1_FIFO_THRESHOLD                128
0121 /* location: {SR18,0,5},{SR18,7,7} */
0122 #define P880_IGA1_FIFO_HIGH_THRESHOLD           64
0123 /* location: {SR22,0,4}. (128/4) =64, K800 must be set zero, */
0124                 /* because HW only 5 bits */
0125 #define P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      0
0126
0127 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0128 #define P880_IGA2_FIFO_MAX_DEPTH                96
0129 /* location: {CR68,0,3},{CR95,4,6} */
0130 #define P880_IGA2_FIFO_THRESHOLD                64
0131 /* location: {CR92,0,3},{CR95,0,2} */
0132 #define P880_IGA2_FIFO_HIGH_THRESHOLD           32
0133 /* location: {CR94,0,6} */
0134 #define P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM      128
0135
0136 /* VT3314 chipset*/
0137
0138 /* location: {SR17,0,7} */
0139 #define CN700_IGA1_FIFO_MAX_DEPTH               96
0140 /* location: {SR16,0,5},{SR16,7,7} */
0141 #define CN700_IGA1_FIFO_THRESHOLD               80
0142 /* location: {SR18,0,5},{SR18,7,7} */
0143 #define CN700_IGA1_FIFO_HIGH_THRESHOLD          64
0144 /* location: {SR22,0,4}. (128/4) =64, P800 must be set zero,
0145                 because HW only 5 bits */
0146 #define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     0
0147 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0148 #define CN700_IGA2_FIFO_MAX_DEPTH               96
0149 /* location: {CR68,0,3},{CR95,4,6} */
0150 #define CN700_IGA2_FIFO_THRESHOLD               80
0151 /* location: {CR92,0,3},{CR95,0,2} */
0152 #define CN700_IGA2_FIFO_HIGH_THRESHOLD          32
0153 /* location: {CR94,0,6} */
0154 #define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
0155
0156 /* For VT3324, these values are suggested by HW */
0157 /* location: {SR17,0,7} */
0158 #define CX700_IGA1_FIFO_MAX_DEPTH               192
0159 /* location: {SR16,0,5},{SR16,7,7} */
0160 #define CX700_IGA1_FIFO_THRESHOLD               128
0161 /* location: {SR18,0,5},{SR18,7,7} */
0162 #define CX700_IGA1_FIFO_HIGH_THRESHOLD          128
0163 /* location: {SR22,0,4} */
0164 #define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
0165
0166 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0167 #define CX700_IGA2_FIFO_MAX_DEPTH               96
0168 /* location: {CR68,0,3},{CR95,4,6} */
0169 #define CX700_IGA2_FIFO_THRESHOLD               64
0170 /* location: {CR92,0,3},{CR95,0,2} */
0171 #define CX700_IGA2_FIFO_HIGH_THRESHOLD          32
0172 /* location: {CR94,0,6} */
0173 #define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
0174
0175 /* VT3336 chipset*/
0176 /* location: {SR17,0,7} */
0177 #define K8M890_IGA1_FIFO_MAX_DEPTH               360
0178 /* location: {SR16,0,5},{SR16,7,7} */
0179 #define K8M890_IGA1_FIFO_THRESHOLD               328
0180 /* location: {SR18,0,5},{SR18,7,7} */
0181 #define K8M890_IGA1_FIFO_HIGH_THRESHOLD          296
0182 /* location: {SR22,0,4}. */
0183 #define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     124
0184
0185 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0186 #define K8M890_IGA2_FIFO_MAX_DEPTH               360
0187 /* location: {CR68,0,3},{CR95,4,6} */
0188 #define K8M890_IGA2_FIFO_THRESHOLD               328
0189 /* location: {CR92,0,3},{CR95,0,2} */
0190 #define K8M890_IGA2_FIFO_HIGH_THRESHOLD          296
0191 /* location: {CR94,0,6} */
0192 #define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     124
0193
0194 /* VT3327 chipset*/
0195 /* location: {SR17,0,7} */
0196 #define P4M890_IGA1_FIFO_MAX_DEPTH               96
0197 /* location: {SR16,0,5},{SR16,7,7} */
0198 #define P4M890_IGA1_FIFO_THRESHOLD               76
0199 /* location: {SR18,0,5},{SR18,7,7} */
0200 #define P4M890_IGA1_FIFO_HIGH_THRESHOLD          64
0201 /* location: {SR22,0,4}. (32/4) =8 */
0202 #define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
0203 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0204 #define P4M890_IGA2_FIFO_MAX_DEPTH               96
0205 /* location: {CR68,0,3},{CR95,4,6} */
0206 #define P4M890_IGA2_FIFO_THRESHOLD               76
0207 /* location: {CR92,0,3},{CR95,0,2} */
0208 #define P4M890_IGA2_FIFO_HIGH_THRESHOLD          64
0209 /* location: {CR94,0,6} */
0210 #define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
0211
0212 /* VT3364 chipset*/
0213 /* location: {SR17,0,7} */
0214 #define P4M900_IGA1_FIFO_MAX_DEPTH               96
0215 /* location: {SR16,0,5},{SR16,7,7} */
0216 #define P4M900_IGA1_FIFO_THRESHOLD               76
0217 /* location: {SR18,0,5},{SR18,7,7} */
0218 #define P4M900_IGA1_FIFO_HIGH_THRESHOLD          76
0219 /* location: {SR22,0,4}. */
0220 #define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     32
0221 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0222 #define P4M900_IGA2_FIFO_MAX_DEPTH               96
0223 /* location: {CR68,0,3},{CR95,4,6} */
0224 #define P4M900_IGA2_FIFO_THRESHOLD               76
0225 /* location: {CR92,0,3},{CR95,0,2} */
0226 #define P4M900_IGA2_FIFO_HIGH_THRESHOLD          76
0227 /* location: {CR94,0,6} */
0228 #define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     32
0229
0230 /* For VT3353, these values are suggested by HW */
0231 /* location: {SR17,0,7} */
0232 #define VX800_IGA1_FIFO_MAX_DEPTH               192
0233 /* location: {SR16,0,5},{SR16,7,7} */
0234 #define VX800_IGA1_FIFO_THRESHOLD               152
0235 /* location: {SR18,0,5},{SR18,7,7} */
0236 #define VX800_IGA1_FIFO_HIGH_THRESHOLD          152
0237 /* location: {SR22,0,4} */
0238 #define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM      64
0239 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7} */
0240 #define VX800_IGA2_FIFO_MAX_DEPTH               96
0241 /* location: {CR68,0,3},{CR95,4,6} */
0242 #define VX800_IGA2_FIFO_THRESHOLD               64
0243 /* location: {CR92,0,3},{CR95,0,2} */
0244 #define VX800_IGA2_FIFO_HIGH_THRESHOLD          32
0245 /* location: {CR94,0,6} */
0246 #define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     128
0247
0248 /* For VT3409 */
0249 #define VX855_IGA1_FIFO_MAX_DEPTH               400
0250 #define VX855_IGA1_FIFO_THRESHOLD               320
0251 #define VX855_IGA1_FIFO_HIGH_THRESHOLD          320
0252 #define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
0253
0254 #define VX855_IGA2_FIFO_MAX_DEPTH               200
0255 #define VX855_IGA2_FIFO_THRESHOLD               160
0256 #define VX855_IGA2_FIFO_HIGH_THRESHOLD          160
0257 #define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
0258
0259 /* For VT3410 */
0260 #define VX900_IGA1_FIFO_MAX_DEPTH               400
0261 #define VX900_IGA1_FIFO_THRESHOLD               320
0262 #define VX900_IGA1_FIFO_HIGH_THRESHOLD          320
0263 #define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM     160
0264
0265 #define VX900_IGA2_FIFO_MAX_DEPTH               192
0266 #define VX900_IGA2_FIFO_THRESHOLD               160
0267 #define VX900_IGA2_FIFO_HIGH_THRESHOLD          160
0268 #define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM     320
0269
0270 #define IGA1_FIFO_DEPTH_SELECT_REG_NUM          1
0271 #define IGA1_FIFO_THRESHOLD_REG_NUM             2
0272 #define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM        2
0273 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
0274
0275 #define IGA2_FIFO_DEPTH_SELECT_REG_NUM          3
0276 #define IGA2_FIFO_THRESHOLD_REG_NUM             2
0277 #define IGA2_FIFO_HIGH_THRESHOLD_REG_NUM        2
0278 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM   1
0279
0280 #define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)                   ((x/2)-1)
0281 #define IGA1_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
0282 #define IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
0283 #define IGA1_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
0284 #define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)                   (((x/2)/4)-1)
0285 #define IGA2_FIFO_THRESHOLD_FORMULA(x)                      (x/4)
0286 #define IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(x)            (x/4)
0287 #define IGA2_FIFO_HIGH_THRESHOLD_FORMULA(x)                 (x/4)
0288
0289 /************************************************************************/
0290 /*  LCD Timing                                                          */
0291 /************************************************************************/
0292
0293 /* 500 ms = 500000 us */
0294 #define LCD_POWER_SEQ_TD0               500000
0295 /* 50 ms = 50000 us */
0296 #define LCD_POWER_SEQ_TD1               50000
0297 /* 0 us */
0298 #define LCD_POWER_SEQ_TD2               0
0299 /* 210 ms = 210000 us */
0300 #define LCD_POWER_SEQ_TD3               210000
0301 /* 2^10 * (1/14.31818M) = 71.475 us (K400.revA) */
0302 #define CLE266_POWER_SEQ_UNIT           71
0303 /* 2^11 * (1/14.31818M) = 142.95 us (K400.revB) */
0304 #define K800_POWER_SEQ_UNIT             142
0305 /* 2^13 * (1/14.31818M) = 572.1 us */
0306 #define P880_POWER_SEQ_UNIT             572
0307
0308 #define CLE266_POWER_SEQ_FORMULA(x)     ((x)/CLE266_POWER_SEQ_UNIT)
0309 #define K800_POWER_SEQ_FORMULA(x)       ((x)/K800_POWER_SEQ_UNIT)
0310 #define P880_POWER_SEQ_FORMULA(x)       ((x)/P880_POWER_SEQ_UNIT)
0311
0312 /* location: {CR8B,0,7},{CR8F,0,3} */
0313 #define LCD_POWER_SEQ_TD0_REG_NUM       2
0314 /* location: {CR8C,0,7},{CR8F,4,7} */
0315 #define LCD_POWER_SEQ_TD1_REG_NUM       2
0316 /* location: {CR8D,0,7},{CR90,0,3} */
0317 #define LCD_POWER_SEQ_TD2_REG_NUM       2
0318 /* location: {CR8E,0,7},{CR90,4,7} */
0319 #define LCD_POWER_SEQ_TD3_REG_NUM       2
0320
0321 /* LCD Scaling factor*/
0322 /* x: indicate setting horizontal size*/
0323 /* y: indicate panel horizontal size*/
0324
0325 /* Horizontal scaling factor 10 bits (2^10) */
0326 #define CLE266_LCD_HOR_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
0327 /* Vertical scaling factor 10 bits (2^10) */
0328 #define CLE266_LCD_VER_SCF_FORMULA(x, y)   (((x-1)*1024)/(y-1))
0329 /* Horizontal scaling factor 10 bits (2^12) */
0330 #define K800_LCD_HOR_SCF_FORMULA(x, y)     (((x-1)*4096)/(y-1))
0331 /* Vertical scaling factor 10 bits (2^11) */
0332 #define K800_LCD_VER_SCF_FORMULA(x, y)     (((x-1)*2048)/(y-1))
0333
0334 /* location: {CR9F,0,1},{CR77,0,7},{CR79,4,5} */
0335 #define LCD_HOR_SCALING_FACTOR_REG_NUM  3
0336 /* location: {CR79,3,3},{CR78,0,7},{CR79,6,7} */
0337 #define LCD_VER_SCALING_FACTOR_REG_NUM  3
0338 /* location: {CR77,0,7},{CR79,4,5} */
0339 #define LCD_HOR_SCALING_FACTOR_REG_NUM_CLE  2
0340 /* location: {CR78,0,7},{CR79,6,7} */
0341 #define LCD_VER_SCALING_FACTOR_REG_NUM_CLE  2
0342
0343 struct io_register {
0344     u8 io_addr;
0345     u8 start_bit;
0346     u8 end_bit;
0347 };
0348
0349 /*****************************************************
0350 **      Define IGA2 Shadow Display Timing         ****
0351 *****************************************************/
0352
0353 /* IGA2 Shadow Horizontal Total */
0354 struct iga2_shadow_hor_total {
0355     int reg_num;
0356     struct io_register reg[IGA2_SHADOW_HOR_TOTAL_REG_NUM];
0357 };
0358
0359 /* IGA2 Shadow Horizontal Blank End */
0360 struct iga2_shadow_hor_blank_end {
0361     int reg_num;
0362     struct io_register reg[IGA2_SHADOW_HOR_BLANK_END_REG_NUM];
0363 };
0364
0365 /* IGA2 Shadow Vertical Total */
0366 struct iga2_shadow_ver_total {
0367     int reg_num;
0368     struct io_register reg[IGA2_SHADOW_VER_TOTAL_REG_NUM];
0369 };
0370
0371 /* IGA2 Shadow Vertical Addressable Video */
0372 struct iga2_shadow_ver_addr {
0373     int reg_num;
0374     struct io_register reg[IGA2_SHADOW_VER_ADDR_REG_NUM];
0375 };
0376
0377 /* IGA2 Shadow Vertical Blank Start */
0378 struct iga2_shadow_ver_blank_start {
0379     int reg_num;
0380     struct io_register reg[IGA2_SHADOW_VER_BLANK_START_REG_NUM];
0381 };
0382
0383 /* IGA2 Shadow Vertical Blank End */
0384 struct iga2_shadow_ver_blank_end {
0385     int reg_num;
0386     struct io_register reg[IGA2_SHADOW_VER_BLANK_END_REG_NUM];
0387 };
0388
0389 /* IGA2 Shadow Vertical Sync Start */
0390 struct iga2_shadow_ver_sync_start {
0391     int reg_num;
0392     struct io_register reg[IGA2_SHADOW_VER_SYNC_START_REG_NUM];
0393 };
0394
0395 /* IGA2 Shadow Vertical Sync End */
0396 struct iga2_shadow_ver_sync_end {
0397     int reg_num;
0398     struct io_register reg[IGA2_SHADOW_VER_SYNC_END_REG_NUM];
0399 };
0400
0401 /* IGA1 Fetch Count Register */
0402 struct iga1_fetch_count {
0403     int reg_num;
0404     struct io_register reg[IGA1_FETCH_COUNT_REG_NUM];
0405 };
0406
0407 /* IGA2 Fetch Count Register */
0408 struct iga2_fetch_count {
0409     int reg_num;
0410     struct io_register reg[IGA2_FETCH_COUNT_REG_NUM];
0411 };
0412
0413 struct fetch_count {
0414     struct iga1_fetch_count iga1_fetch_count_reg;
0415     struct iga2_fetch_count iga2_fetch_count_reg;
0416 };
0417
0418 /* Starting Address Register */
0419 struct iga1_starting_addr {
0420     int reg_num;
0421     struct io_register reg[IGA1_STARTING_ADDR_REG_NUM];
0422 };
0423
0424 struct iga2_starting_addr {
0425     int reg_num;
0426     struct io_register reg[IGA2_STARTING_ADDR_REG_NUM];
0427 };
0428
0429 struct starting_addr {
0430     struct iga1_starting_addr iga1_starting_addr_reg;
0431     struct iga2_starting_addr iga2_starting_addr_reg;
0432 };
0433
0434 /* LCD Power Sequence Timer */
0435 struct lcd_pwd_seq_td0 {
0436     int reg_num;
0437     struct io_register reg[LCD_POWER_SEQ_TD0_REG_NUM];
0438 };
0439
0440 struct lcd_pwd_seq_td1 {
0441     int reg_num;
0442     struct io_register reg[LCD_POWER_SEQ_TD1_REG_NUM];
0443 };
0444
0445 struct lcd_pwd_seq_td2 {
0446     int reg_num;
0447     struct io_register reg[LCD_POWER_SEQ_TD2_REG_NUM];
0448 };
0449
0450 struct lcd_pwd_seq_td3 {
0451     int reg_num;
0452     struct io_register reg[LCD_POWER_SEQ_TD3_REG_NUM];
0453 };
0454
0455 struct _lcd_pwd_seq_timer {
0456     struct lcd_pwd_seq_td0 td0;
0457     struct lcd_pwd_seq_td1 td1;
0458     struct lcd_pwd_seq_td2 td2;
0459     struct lcd_pwd_seq_td3 td3;
0460 };
0461
0462 /* LCD Scaling Factor */
0463 struct _lcd_hor_scaling_factor {
0464     int reg_num;
0465     struct io_register reg[LCD_HOR_SCALING_FACTOR_REG_NUM];
0466 };
0467
0468 struct _lcd_ver_scaling_factor {
0469     int reg_num;
0470     struct io_register reg[LCD_VER_SCALING_FACTOR_REG_NUM];
0471 };
0472
0473 struct _lcd_scaling_factor {
0474     struct _lcd_hor_scaling_factor lcd_hor_scaling_factor;
0475     struct _lcd_ver_scaling_factor lcd_ver_scaling_factor;
0476 };
0477
0478 struct pll_limit {
0479     u16 multiplier_min;
0480     u16 multiplier_max;
0481     u8 divisor;
0482     u8 rshift;
0483 };
0484
0485 struct rgbLUT {
0486     u8 red;
0487     u8 green;
0488     u8 blue;
0489 };
0490
0491 struct lcd_pwd_seq_timer {
0492     u16 td0;
0493     u16 td1;
0494     u16 td2;
0495     u16 td3;
0496 };
0497
0498 /* Display FIFO Relation Registers*/
0499 struct iga1_fifo_depth_select {
0500     int reg_num;
0501     struct io_register reg[IGA1_FIFO_DEPTH_SELECT_REG_NUM];
0502 };
0503
0504 struct iga1_fifo_threshold_select {
0505     int reg_num;
0506     struct io_register reg[IGA1_FIFO_THRESHOLD_REG_NUM];
0507 };
0508
0509 struct iga1_fifo_high_threshold_select {
0510     int reg_num;
0511     struct io_register reg[IGA1_FIFO_HIGH_THRESHOLD_REG_NUM];
0512 };
0513
0514 struct iga1_display_queue_expire_num {
0515     int reg_num;
0516     struct io_register reg[IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
0517 };
0518
0519 struct iga2_fifo_depth_select {
0520     int reg_num;
0521     struct io_register reg[IGA2_FIFO_DEPTH_SELECT_REG_NUM];
0522 };
0523
0524 struct iga2_fifo_threshold_select {
0525     int reg_num;
0526     struct io_register reg[IGA2_FIFO_THRESHOLD_REG_NUM];
0527 };
0528
0529 struct iga2_fifo_high_threshold_select {
0530     int reg_num;
0531     struct io_register reg[IGA2_FIFO_HIGH_THRESHOLD_REG_NUM];
0532 };
0533
0534 struct iga2_display_queue_expire_num {
0535     int reg_num;
0536     struct io_register reg[IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM];
0537 };
0538
0539 struct fifo_depth_select {
0540     struct iga1_fifo_depth_select iga1_fifo_depth_select_reg;
0541     struct iga2_fifo_depth_select iga2_fifo_depth_select_reg;
0542 };
0543
0544 struct fifo_threshold_select {
0545     struct iga1_fifo_threshold_select iga1_fifo_threshold_select_reg;
0546     struct iga2_fifo_threshold_select iga2_fifo_threshold_select_reg;
0547 };
0548
0549 struct fifo_high_threshold_select {
0550     struct iga1_fifo_high_threshold_select
0551      iga1_fifo_high_threshold_select_reg;
0552     struct iga2_fifo_high_threshold_select
0553      iga2_fifo_high_threshold_select_reg;
0554 };
0555
0556 struct display_queue_expire_num {
0557     struct iga1_display_queue_expire_num
0558      iga1_display_queue_expire_num_reg;
0559     struct iga2_display_queue_expire_num
0560      iga2_display_queue_expire_num_reg;
0561 };
0562
0563 struct iga2_shadow_crtc_timing {
0564     struct iga2_shadow_hor_total hor_total_shadow;
0565     struct iga2_shadow_hor_blank_end hor_blank_end_shadow;
0566     struct iga2_shadow_ver_total ver_total_shadow;
0567     struct iga2_shadow_ver_addr ver_addr_shadow;
0568     struct iga2_shadow_ver_blank_start ver_blank_start_shadow;
0569     struct iga2_shadow_ver_blank_end ver_blank_end_shadow;
0570     struct iga2_shadow_ver_sync_start ver_sync_start_shadow;
0571     struct iga2_shadow_ver_sync_end ver_sync_end_shadow;
0572 };
0573
0574 /* device ID */
0575 #define CLE266_FUNCTION3    0x3123
0576 #define KM400_FUNCTION3     0x3205
0577 #define CN400_FUNCTION2     0x2259
0578 #define CN400_FUNCTION3     0x3259
0579 /* support VT3314 chipset */
0580 #define CN700_FUNCTION2     0x2314
0581 #define CN700_FUNCTION3     0x3208
0582 /* VT3324 chipset */
0583 #define CX700_FUNCTION2     0x2324
0584 #define CX700_FUNCTION3     0x3324
0585 /* VT3204 chipset*/
0586 #define KM800_FUNCTION3      0x3204
0587 /* VT3336 chipset*/
0588 #define KM890_FUNCTION3      0x3336
0589 /* VT3327 chipset*/
0590 #define P4M890_FUNCTION3     0x3327
0591 /* VT3293 chipset*/
0592 #define CN750_FUNCTION3     0x3208
0593 /* VT3364 chipset*/
0594 #define P4M900_FUNCTION3    0x3364
0595 /* VT3353 chipset*/
0596 #define VX800_FUNCTION3     0x3353
0597 /* VT3409 chipset*/
0598 #define VX855_FUNCTION3     0x3409
0599 /* VT3410 chipset*/
0600 #define VX900_FUNCTION3     0x3410
0601
0602 struct IODATA {
0603     u8 Index;
0604     u8 Mask;
0605     u8 Data;
0606 };
0607
0608 struct pci_device_id_info {
0609     u32 vendor;
0610     u32 device;
0611     u32 chip_index;
0612 };
0613
0614 struct via_device_mapping {
0615     u32 device;
0616     const char *name;
0617 };
0618
0619 extern int viafb_SAMM_ON;
0620 extern int viafb_dual_fb;
0621 extern int viafb_LCD2_ON;
0622 extern int viafb_LCD_ON;
0623 extern int viafb_DVI_ON;
0624 extern int viafb_hotplug;
0625
0626 struct via_display_timing var_to_timing(const struct fb_var_screeninfo *var,
0627     u16 cxres, u16 cyres);
0628 void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var,
0629     u16 cxres, u16 cyres, int iga);
0630 void viafb_set_vclock(u32 CLK, int set_iga);
0631 void viafb_load_reg(int timing_value, int viafb_load_reg_num,
0632     struct io_register *reg,
0633           int io_type);
0634 void via_set_source(u32 devices, u8 iga);
0635 void via_set_state(u32 devices, u8 state);
0636 void via_set_sync_polarity(u32 devices, u8 polarity);
0637 u32 via_parse_odev(char *input, char **end);
0638 void via_odev_to_seq(struct seq_file *m, u32 odev);
0639 void init_ad9389(void);
0640 /* Access I/O Function */
0641 void viafb_lock_crt(void);
0642 void viafb_unlock_crt(void);
0643 void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
0644 void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
0645 void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
0646 void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
0647                     *p_gfx_dpa_setting);
0648
0649 int viafb_setmode(void);
0650 void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
0651     const struct fb_videomode *mode);
0652 void viafb_init_chip_info(int chip_type);
0653 void viafb_init_dac(int set_iga);
0654 int viafb_get_refresh(int hres, int vres, u32 float_refresh);
0655 void viafb_update_device_setting(int hres, int vres, int bpp, int flag);
0656
0657 void viafb_set_iga_path(void);
0658 void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
0659 void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
0660 void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
0661
0662 #endif /* __HW_H__ */