fbdev/via/chip.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
0004  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
0005
0006  */
0007 #ifndef __CHIP_H__
0008 #define __CHIP_H__
0009
0010 #include "global.h"
0011
0012 /***************************************/
0013 /* Definition Graphic Chip Information */
0014 /***************************************/
0015
0016 #define     PCI_VIA_VENDOR_ID       0x1106
0017
0018 /* Define VIA Graphic Chip Name */
0019 #define     UNICHROME_CLE266        1
0020 #define     UNICHROME_CLE266_DID    0x3122
0021 #define     CLE266_REVISION_AX      0x0A
0022 #define     CLE266_REVISION_CX      0x0C
0023
0024 #define     UNICHROME_K400          2
0025 #define     UNICHROME_K400_DID      0x7205
0026
0027 #define     UNICHROME_K800          3
0028 #define     UNICHROME_K800_DID      0x3108
0029
0030 #define     UNICHROME_PM800         4
0031 #define     UNICHROME_PM800_DID     0x3118
0032
0033 #define     UNICHROME_CN700         5
0034 #define     UNICHROME_CN700_DID     0x3344
0035
0036 #define     UNICHROME_CX700         6
0037 #define     UNICHROME_CX700_DID     0x3157
0038 #define     CX700_REVISION_700      0x0
0039 #define     CX700_REVISION_700M     0x1
0040 #define     CX700_REVISION_700M2    0x2
0041
0042 #define     UNICHROME_CN750         7
0043 #define     UNICHROME_CN750_DID     0x3225
0044
0045 #define     UNICHROME_K8M890        8
0046 #define     UNICHROME_K8M890_DID    0x3230
0047
0048 #define     UNICHROME_P4M890        9
0049 #define     UNICHROME_P4M890_DID    0x3343
0050
0051 #define     UNICHROME_P4M900        10
0052 #define     UNICHROME_P4M900_DID    0x3371
0053
0054 #define     UNICHROME_VX800         11
0055 #define     UNICHROME_VX800_DID     0x1122
0056
0057 #define     UNICHROME_VX855         12
0058 #define     UNICHROME_VX855_DID     0x5122
0059
0060 #define     UNICHROME_VX900         13
0061 #define     UNICHROME_VX900_DID     0x7122
0062
0063 /**************************************************/
0064 /* Definition TMDS Trasmitter Information         */
0065 /**************************************************/
0066
0067 /* Definition TMDS Trasmitter Index */
0068 #define     NON_TMDS_TRANSMITTER    0x00
0069 #define     VT1632_TMDS             0x01
0070 #define     INTEGRATED_TMDS         0x42
0071
0072 /* Definition TMDS Trasmitter I2C Slave Address */
0073 #define     VT1632_TMDS_I2C_ADDR    0x10
0074
0075 /**************************************************/
0076 /* Definition LVDS Trasmitter Information         */
0077 /**************************************************/
0078
0079 /* Definition LVDS Trasmitter Index */
0080 #define     NON_LVDS_TRANSMITTER    0x00
0081 #define     VT1631_LVDS             0x01
0082 #define     VT1636_LVDS             0x0E
0083 #define     INTEGRATED_LVDS         0x41
0084
0085 /* Definition Digital Transmitter Mode */
0086 #define     TX_DATA_12_BITS         0x01
0087 #define     TX_DATA_24_BITS         0x02
0088 #define     TX_DATA_DDR_MODE        0x04
0089 #define     TX_DATA_SDR_MODE        0x08
0090
0091 /* Definition LVDS Trasmitter I2C Slave Address */
0092 #define     VT1631_LVDS_I2C_ADDR    0x70
0093 #define     VT3271_LVDS_I2C_ADDR    0x80
0094 #define     VT1636_LVDS_I2C_ADDR    0x80
0095
0096 struct tmds_chip_information {
0097     int tmds_chip_name;
0098     int tmds_chip_slave_addr;
0099     int output_interface;
0100     int i2c_port;
0101 };
0102
0103 struct lvds_chip_information {
0104     int lvds_chip_name;
0105     int lvds_chip_slave_addr;
0106     int output_interface;
0107     int i2c_port;
0108 };
0109
0110 /* The type of 2D engine */
0111 enum via_2d_engine {
0112     VIA_2D_ENG_H2,
0113     VIA_2D_ENG_H5,
0114     VIA_2D_ENG_M1,
0115 };
0116
0117 struct chip_information {
0118     int gfx_chip_name;
0119     int gfx_chip_revision;
0120     enum via_2d_engine twod_engine;
0121     struct tmds_chip_information tmds_chip_info;
0122     struct lvds_chip_information lvds_chip_info;
0123     struct lvds_chip_information lvds_chip_info2;
0124 };
0125
0126 struct tmds_setting_information {
0127     int iga_path;
0128     int h_active;
0129     int v_active;
0130     int max_pixel_clock;
0131 };
0132
0133 struct lvds_setting_information {
0134     int iga_path;
0135     int lcd_panel_hres;
0136     int lcd_panel_vres;
0137     int display_method;
0138     int device_lcd_dualedge;
0139     int LCDDithering;
0140     int lcd_mode;
0141     u32 vclk;       /*panel mode clock value */
0142 };
0143
0144 struct GFX_DPA_SETTING {
0145     int ClkRangeIndex;
0146     u8 DVP0;        /* CR96[3:0] */
0147     u8 DVP0DataDri_S1;  /* SR2A[5]   */
0148     u8 DVP0DataDri_S;   /* SR1B[1]   */
0149     u8 DVP0ClockDri_S1; /* SR2A[4]   */
0150     u8 DVP0ClockDri_S;  /* SR1E[2]   */
0151     u8 DVP1;        /* CR9B[3:0] */
0152     u8 DVP1Driving;     /* SR65[3:0], Data and Clock driving */
0153     u8 DFPHigh;     /* CR97[3:0] */
0154     u8 DFPLow;      /* CR99[3:0] */
0155
0156 };
0157
0158 struct VT1636_DPA_SETTING {
0159     u8 CLK_SEL_ST1;
0160     u8 CLK_SEL_ST2;
0161 };
0162 #endif /* __CHIP_H__ */