fbdev/via/accel.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
0004  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
0005
0006  */
0007
0008 #ifndef __ACCEL_H__
0009 #define __ACCEL_H__
0010
0011 #define FB_ACCEL_VIA_UNICHROME  50
0012
0013 /* MMIO Base Address Definition */
0014 #define MMIO_VGABASE                0x8000
0015 #define MMIO_CR_READ                (MMIO_VGABASE + 0x3D4)
0016 #define MMIO_CR_WRITE               (MMIO_VGABASE + 0x3D5)
0017 #define MMIO_SR_READ                (MMIO_VGABASE + 0x3C4)
0018 #define MMIO_SR_WRITE               (MMIO_VGABASE + 0x3C5)
0019
0020 /* HW Cursor Status Define */
0021 #define HW_Cursor_ON    0
0022 #define HW_Cursor_OFF   1
0023
0024 #define CURSOR_SIZE     (8 * 1024)
0025 #define VQ_SIZE         (256 * 1024)
0026
0027 #define VIA_MMIO_BLTBASE        0x200000
0028 #define VIA_MMIO_BLTSIZE        0x200000
0029
0030 /* Defines for 2D registers */
0031 #define VIA_REG_GECMD           0x000
0032 #define VIA_REG_GEMODE          0x004
0033 #define VIA_REG_SRCPOS          0x008
0034 #define VIA_REG_DSTPOS          0x00C
0035 /* width and height */
0036 #define VIA_REG_DIMENSION       0x010
0037 #define VIA_REG_PATADDR         0x014
0038 #define VIA_REG_FGCOLOR         0x018
0039 #define VIA_REG_BGCOLOR         0x01C
0040 /* top and left of clipping */
0041 #define VIA_REG_CLIPTL          0x020
0042 /* bottom and right of clipping */
0043 #define VIA_REG_CLIPBR          0x024
0044 #define VIA_REG_OFFSET          0x028
0045 /* color key control */
0046 #define VIA_REG_KEYCONTROL      0x02C
0047 #define VIA_REG_SRCBASE         0x030
0048 #define VIA_REG_DSTBASE         0x034
0049 /* pitch of src and dst */
0050 #define VIA_REG_PITCH           0x038
0051 #define VIA_REG_MONOPAT0        0x03C
0052 #define VIA_REG_MONOPAT1        0x040
0053 /* from 0x100 to 0x1ff */
0054 #define VIA_REG_COLORPAT        0x100
0055
0056 /* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/
0057 #define VIA_REG_GECMD_M1        0x000
0058 #define VIA_REG_GEMODE_M1       0x004
0059 #define VIA_REG_GESTATUS_M1     0x004       /* as same as VIA_REG_GEMODE */
0060 #define VIA_REG_PITCH_M1        0x008       /* pitch of src and dst */
0061 #define VIA_REG_DIMENSION_M1    0x00C       /* width and height */
0062 #define VIA_REG_DSTPOS_M1       0x010
0063 #define VIA_REG_LINE_XY_M1      0x010
0064 #define VIA_REG_DSTBASE_M1      0x014
0065 #define VIA_REG_SRCPOS_M1       0x018
0066 #define VIA_REG_LINE_K1K2_M1    0x018
0067 #define VIA_REG_SRCBASE_M1      0x01C
0068 #define VIA_REG_PATADDR_M1      0x020
0069 #define VIA_REG_MONOPAT0_M1     0x024
0070 #define VIA_REG_MONOPAT1_M1     0x028
0071 #define VIA_REG_OFFSET_M1       0x02C
0072 #define VIA_REG_LINE_ERROR_M1   0x02C
0073 #define VIA_REG_CLIPTL_M1       0x040       /* top and left of clipping */
0074 #define VIA_REG_CLIPBR_M1       0x044       /* bottom and right of clipping */
0075 #define VIA_REG_KEYCONTROL_M1   0x048       /* color key control */
0076 #define VIA_REG_FGCOLOR_M1      0x04C
0077 #define VIA_REG_DSTCOLORKEY_M1  0x04C       /* as same as VIA_REG_FG */
0078 #define VIA_REG_BGCOLOR_M1      0x050
0079 #define VIA_REG_SRCCOLORKEY_M1  0x050       /* as same as VIA_REG_BG */
0080 #define VIA_REG_MONOPATFGC_M1   0x058       /* Add BG color of Pattern. */
0081 #define VIA_REG_MONOPATBGC_M1   0x05C       /* Add FG color of Pattern. */
0082 #define VIA_REG_COLORPAT_M1     0x100       /* from 0x100 to 0x1ff */
0083
0084 /* VIA_REG_PITCH(0x38): Pitch Setting */
0085 #define VIA_PITCH_ENABLE        0x80000000
0086
0087 /* defines for VIA HW cursor registers */
0088 #define VIA_REG_CURSOR_MODE     0x2D0
0089 #define VIA_REG_CURSOR_POS      0x2D4
0090 #define VIA_REG_CURSOR_ORG      0x2D8
0091 #define VIA_REG_CURSOR_BG       0x2DC
0092 #define VIA_REG_CURSOR_FG       0x2E0
0093
0094 /* VIA_REG_GEMODE(0x04): GE mode */
0095 #define VIA_GEM_8bpp            0x00000000
0096 #define VIA_GEM_16bpp           0x00000100
0097 #define VIA_GEM_32bpp           0x00000300
0098
0099 /* VIA_REG_GECMD(0x00): 2D Engine Command  */
0100 #define VIA_GEC_NOOP            0x00000000
0101 #define VIA_GEC_BLT             0x00000001
0102 #define VIA_GEC_LINE            0x00000005
0103
0104 /* Rotate Command */
0105 #define VIA_GEC_ROT             0x00000008
0106
0107 #define VIA_GEC_SRC_XY          0x00000000
0108 #define VIA_GEC_SRC_LINEAR      0x00000010
0109 #define VIA_GEC_DST_XY          0x00000000
0110 #define VIA_GEC_DST_LINRAT      0x00000020
0111
0112 #define VIA_GEC_SRC_FB          0x00000000
0113 #define VIA_GEC_SRC_SYS         0x00000040
0114 #define VIA_GEC_DST_FB          0x00000000
0115 #define VIA_GEC_DST_SYS         0x00000080
0116
0117 /* source is mono */
0118 #define VIA_GEC_SRC_MONO        0x00000100
0119 /* pattern is mono */
0120 #define VIA_GEC_PAT_MONO        0x00000200
0121 /* mono src is opaque */
0122 #define VIA_GEC_MSRC_OPAQUE     0x00000000
0123 /* mono src is transparent */
0124 #define VIA_GEC_MSRC_TRANS      0x00000400
0125 /* pattern is in frame buffer */
0126 #define VIA_GEC_PAT_FB          0x00000000
0127 /* pattern is from reg setting */
0128 #define VIA_GEC_PAT_REG         0x00000800
0129
0130 #define VIA_GEC_CLIP_DISABLE    0x00000000
0131 #define VIA_GEC_CLIP_ENABLE     0x00001000
0132
0133 #define VIA_GEC_FIXCOLOR_PAT    0x00002000
0134
0135 #define VIA_GEC_INCX            0x00000000
0136 #define VIA_GEC_DECY            0x00004000
0137 #define VIA_GEC_INCY            0x00000000
0138 #define VIA_GEC_DECX            0x00008000
0139 /* mono pattern is opaque */
0140 #define VIA_GEC_MPAT_OPAQUE     0x00000000
0141 /* mono pattern is transparent */
0142 #define VIA_GEC_MPAT_TRANS      0x00010000
0143
0144 #define VIA_GEC_MONO_UNPACK     0x00000000
0145 #define VIA_GEC_MONO_PACK       0x00020000
0146 #define VIA_GEC_MONO_DWORD      0x00000000
0147 #define VIA_GEC_MONO_WORD       0x00040000
0148 #define VIA_GEC_MONO_BYTE       0x00080000
0149
0150 #define VIA_GEC_LASTPIXEL_ON    0x00000000
0151 #define VIA_GEC_LASTPIXEL_OFF   0x00100000
0152 #define VIA_GEC_X_MAJOR         0x00000000
0153 #define VIA_GEC_Y_MAJOR         0x00200000
0154 #define VIA_GEC_QUICK_START     0x00800000
0155
0156 /* defines for VIA 3D registers */
0157 #define VIA_REG_STATUS          0x400
0158 #define VIA_REG_CR_TRANSET      0x41C
0159 #define VIA_REG_CR_TRANSPACE    0x420
0160 #define VIA_REG_TRANSET         0x43C
0161 #define VIA_REG_TRANSPACE       0x440
0162
0163 /* VIA_REG_STATUS(0x400): Engine Status */
0164
0165 /* Command Regulator is busy */
0166 #define VIA_CMD_RGTR_BUSY       0x00000080
0167 /* 2D Engine is busy */
0168 #define VIA_2D_ENG_BUSY         0x00000002
0169 /* 3D Engine is busy */
0170 #define VIA_3D_ENG_BUSY         0x00000001
0171 /* Virtual Queue is busy */
0172 #define VIA_VR_QUEUE_BUSY       0x00020000
0173
0174 /* VIA_REG_STATUS(0x400): Engine Status for H5 */
0175 #define VIA_CMD_RGTR_BUSY_H5   0x00000010  /* Command Regulator is busy */
0176 #define VIA_2D_ENG_BUSY_H5     0x00000002  /* 2D Engine is busy */
0177 #define VIA_3D_ENG_BUSY_H5     0x00001FE1  /* 3D Engine is busy */
0178 #define VIA_VR_QUEUE_BUSY_H5   0x00000004  /* Virtual Queue is busy */
0179
0180 /* VIA_REG_STATUS(0x400): Engine Status for VT3353/3409 */
0181 #define VIA_CMD_RGTR_BUSY_M1   0x00000010  /* Command Regulator is busy */
0182 #define VIA_2D_ENG_BUSY_M1     0x00000002  /* 2D Engine is busy */
0183 #define VIA_3D_ENG_BUSY_M1     0x00001FE1  /* 3D Engine is busy */
0184 #define VIA_VR_QUEUE_BUSY_M1   0x00000004  /* Virtual Queue is busy */
0185
0186 #define MAXLOOP                 0xFFFFFF
0187
0188 #define VIA_BITBLT_COLOR    1
0189 #define VIA_BITBLT_MONO     2
0190 #define VIA_BITBLT_FILL     3
0191
0192 int viafb_setup_engine(struct fb_info *info);
0193 void viafb_reset_engine(struct viafb_par *viapar);
0194 void viafb_show_hw_cursor(struct fb_info *info, int Status);
0195 void viafb_wait_engine_idle(struct fb_info *info);
0196
0197 #endif /* __ACCEL_H__ */