fbdev/vermilion/vermilion.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (c) Intel Corp. 2007.
0004  * All Rights Reserved.
0005  *
0006  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
0007  * develop this driver.
0008  *
0009  * This file is part of the Vermilion Range fb driver.
0010  *
0011  * Authors:
0012  *   Thomas Hellström <thomas-at-tungstengraphics-dot-com>
0013  */
0014
0015 #ifndef _VERMILION_H_
0016 #define _VERMILION_H_
0017
0018 #include <linux/kernel.h>
0019 #include <linux/pci.h>
0020 #include <linux/atomic.h>
0021 #include <linux/mutex.h>
0022
0023 #define VML_DEVICE_GPU 0x5002
0024 #define VML_DEVICE_VDC 0x5009
0025
0026 #define VML_VRAM_AREAS 3
0027 #define VML_MAX_XRES 1024
0028 #define VML_MAX_YRES 768
0029 #define VML_MAX_XRES_VIRTUAL 1040
0030
0031 /*
0032  * Display controller registers:
0033  */
0034
0035 /* Display controller 10-bit color representation */
0036
0037 #define VML_R_MASK                   0x3FF00000
0038 #define VML_R_SHIFT                  20
0039 #define VML_G_MASK                   0x000FFC00
0040 #define VML_G_SHIFT                  10
0041 #define VML_B_MASK                   0x000003FF
0042 #define VML_B_SHIFT                  0
0043
0044 /* Graphics plane control */
0045 #define VML_DSPCCNTR                 0x00072180
0046 #define VML_GFX_ENABLE               0x80000000
0047 #define VML_GFX_GAMMABYPASS          0x40000000
0048 #define VML_GFX_ARGB1555             0x0C000000
0049 #define VML_GFX_RGB0888              0x18000000
0050 #define VML_GFX_ARGB8888             0x1C000000
0051 #define VML_GFX_ALPHACONST           0x02000000
0052 #define VML_GFX_ALPHAMULT            0x01000000
0053 #define VML_GFX_CONST_ALPHA          0x000000FF
0054
0055 /* Graphics plane start address. Pixel aligned. */
0056 #define VML_DSPCADDR                 0x00072184
0057
0058 /* Graphics plane stride register. */
0059 #define VML_DSPCSTRIDE               0x00072188
0060
0061 /* Graphics plane position register. */
0062 #define VML_DSPCPOS                  0x0007218C
0063 #define VML_POS_YMASK                0x0FFF0000
0064 #define VML_POS_YSHIFT               16
0065 #define VML_POS_XMASK                0x00000FFF
0066 #define VML_POS_XSHIFT               0
0067
0068 /* Graphics plane height and width */
0069 #define VML_DSPCSIZE                 0x00072190
0070 #define VML_SIZE_HMASK               0x0FFF0000
0071 #define VML_SIZE_HSHIFT              16
0072 #define VML_SISE_WMASK               0x00000FFF
0073 #define VML_SIZE_WSHIFT              0
0074
0075 /* Graphics plane gamma correction lookup table registers (129 * 32 bits) */
0076 #define VML_DSPCGAMLUT               0x00072200
0077
0078 /* Pixel video output configuration register */
0079 #define VML_PVOCONFIG                0x00061140
0080 #define VML_CONFIG_BASE              0x80000000
0081 #define VML_CONFIG_PIXEL_SWAP        0x04000000
0082 #define VML_CONFIG_DE_INV            0x01000000
0083 #define VML_CONFIG_HREF_INV          0x00400000
0084 #define VML_CONFIG_VREF_INV          0x00100000
0085 #define VML_CONFIG_CLK_INV           0x00040000
0086 #define VML_CONFIG_CLK_DIV2          0x00010000
0087 #define VML_CONFIG_ESTRB_INV         0x00008000
0088
0089 /* Pipe A Horizontal total register */
0090 #define VML_HTOTAL_A                 0x00060000
0091 #define VML_HTOTAL_MASK              0x1FFF0000
0092 #define VML_HTOTAL_SHIFT             16
0093 #define VML_HTOTAL_VAL               8192
0094 #define VML_HACTIVE_MASK             0x000007FF
0095 #define VML_HACTIVE_SHIFT            0
0096 #define VML_HACTIVE_VAL              4096
0097
0098 /* Pipe A Horizontal Blank register */
0099 #define VML_HBLANK_A                 0x00060004
0100 #define VML_HBLANK_END_MASK          0x1FFF0000
0101 #define VML_HBLANK_END_SHIFT         16
0102 #define VML_HBLANK_END_VAL           8192
0103 #define VML_HBLANK_START_MASK        0x00001FFF
0104 #define VML_HBLANK_START_SHIFT       0
0105 #define VML_HBLANK_START_VAL         8192
0106
0107 /* Pipe A Horizontal Sync register */
0108 #define VML_HSYNC_A                  0x00060008
0109 #define VML_HSYNC_END_MASK           0x1FFF0000
0110 #define VML_HSYNC_END_SHIFT          16
0111 #define VML_HSYNC_END_VAL            8192
0112 #define VML_HSYNC_START_MASK         0x00001FFF
0113 #define VML_HSYNC_START_SHIFT        0
0114 #define VML_HSYNC_START_VAL          8192
0115
0116 /* Pipe A Vertical total register */
0117 #define VML_VTOTAL_A                 0x0006000C
0118 #define VML_VTOTAL_MASK              0x1FFF0000
0119 #define VML_VTOTAL_SHIFT             16
0120 #define VML_VTOTAL_VAL               8192
0121 #define VML_VACTIVE_MASK             0x000007FF
0122 #define VML_VACTIVE_SHIFT            0
0123 #define VML_VACTIVE_VAL              4096
0124
0125 /* Pipe A Vertical Blank register */
0126 #define VML_VBLANK_A                 0x00060010
0127 #define VML_VBLANK_END_MASK          0x1FFF0000
0128 #define VML_VBLANK_END_SHIFT         16
0129 #define VML_VBLANK_END_VAL           8192
0130 #define VML_VBLANK_START_MASK        0x00001FFF
0131 #define VML_VBLANK_START_SHIFT       0
0132 #define VML_VBLANK_START_VAL         8192
0133
0134 /* Pipe A Vertical Sync register */
0135 #define VML_VSYNC_A                  0x00060014
0136 #define VML_VSYNC_END_MASK           0x1FFF0000
0137 #define VML_VSYNC_END_SHIFT          16
0138 #define VML_VSYNC_END_VAL            8192
0139 #define VML_VSYNC_START_MASK         0x00001FFF
0140 #define VML_VSYNC_START_SHIFT        0
0141 #define VML_VSYNC_START_VAL          8192
0142
0143 /* Pipe A Source Image size (minus one - equal to active size)
0144  * Programmable while pipe is enabled.
0145  */
0146 #define VML_PIPEASRC                 0x0006001C
0147 #define VML_PIPEASRC_HMASK           0x0FFF0000
0148 #define VML_PIPEASRC_HSHIFT          16
0149 #define VML_PIPEASRC_VMASK           0x00000FFF
0150 #define VML_PIPEASRC_VSHIFT          0
0151
0152 /* Pipe A Border Color Pattern register (10 bit color) */
0153 #define VML_BCLRPAT_A                0x00060020
0154
0155 /* Pipe A Canvas Color register  (10 bit color) */
0156 #define VML_CANVSCLR_A               0x00060024
0157
0158 /* Pipe A Configuration register */
0159 #define VML_PIPEACONF                0x00070008
0160 #define VML_PIPE_BASE                0x00000000
0161 #define VML_PIPE_ENABLE              0x80000000
0162 #define VML_PIPE_FORCE_BORDER        0x02000000
0163 #define VML_PIPE_PLANES_OFF          0x00080000
0164 #define VML_PIPE_ARGB_OUTPUT_MODE    0x00040000
0165
0166 /* Pipe A FIFO setting */
0167 #define VML_DSPARB                   0x00070030
0168 #define VML_FIFO_DEFAULT             0x00001D9C
0169
0170 /* MDVO rcomp status & pads control register */
0171 #define VML_RCOMPSTAT                0x00070048
0172 #define VML_MDVO_VDC_I_RCOMP         0x80000000
0173 #define VML_MDVO_POWERSAVE_OFF       0x00000008
0174 #define VML_MDVO_PAD_ENABLE          0x00000004
0175 #define VML_MDVO_PULLDOWN_ENABLE     0x00000001
0176
0177 struct vml_par {
0178     struct pci_dev *vdc;
0179     u64 vdc_mem_base;
0180     u64 vdc_mem_size;
0181     char __iomem *vdc_mem;
0182
0183     struct pci_dev *gpu;
0184     u64 gpu_mem_base;
0185     u64 gpu_mem_size;
0186     char __iomem *gpu_mem;
0187
0188     atomic_t refcount;
0189 };
0190
0191 struct vram_area {
0192     unsigned long logical;
0193     unsigned long phys;
0194     unsigned long size;
0195     unsigned order;
0196 };
0197
0198 struct vml_info {
0199     struct fb_info info;
0200     struct vml_par *par;
0201     struct list_head head;
0202     struct vram_area vram[VML_VRAM_AREAS];
0203     u64 vram_start;
0204     u64 vram_contig_size;
0205     u32 num_areas;
0206     void __iomem *vram_logical;
0207     u32 pseudo_palette[16];
0208     u32 stride;
0209     u32 bytes_per_pixel;
0210     atomic_t vmas;
0211     int cur_blank_mode;
0212     int pipe_disabled;
0213 };
0214
0215 /*
0216  * Subsystem
0217  */
0218
0219 struct vml_sys {
0220     char *name;
0221
0222     /*
0223      * Save / Restore;
0224      */
0225
0226     int (*save) (struct vml_sys * sys);
0227     int (*restore) (struct vml_sys * sys);
0228
0229     /*
0230      * PLL programming;
0231      */
0232
0233     int (*set_clock) (struct vml_sys * sys, int clock);
0234     int (*nearest_clock) (const struct vml_sys * sys, int clock);
0235 };
0236
0237 extern int vmlfb_register_subsys(struct vml_sys *sys);
0238 extern void vmlfb_unregister_subsys(struct vml_sys *sys);
0239
0240 #define VML_READ32(_par, _offset) \
0241     (ioread32((_par)->vdc_mem + (_offset)))
0242 #define VML_WRITE32(_par, _offset, _value)              \
0243     iowrite32(_value, (_par)->vdc_mem + (_offset))
0244
0245 #endif