Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Frame Buffer Device for Toshiba Mobile IO(TMIO) controller
0004  *
0005  * Copyright(C) 2005-2006 Chris Humbert
0006  * Copyright(C) 2005 Dirk Opfer
0007  * Copytight(C) 2007,2008 Dmitry Baryshkov
0008  *
0009  * Based on:
0010  *  drivers/video/w100fb.c
0011  *  code written by Sharp/Lineo for 2.4 kernels
0012  */
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/fb.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/delay.h>
0020 /* Why should fb driver call console functions? because console_lock() */
0021 #include <linux/console.h>
0022 #include <linux/mfd/core.h>
0023 #include <linux/mfd/tmio.h>
0024 #include <linux/uaccess.h>
0025 
0026 /*
0027  * accelerator commands
0028  */
0029 #define TMIOFB_ACC_CSADR(x) (0x00000000 | ((x) & 0x001ffffe))
0030 #define TMIOFB_ACC_CHPIX(x) (0x01000000 | ((x) & 0x000003ff))
0031 #define TMIOFB_ACC_CVPIX(x) (0x02000000 | ((x) & 0x000003ff))
0032 #define TMIOFB_ACC_PSADR(x) (0x03000000 | ((x) & 0x00fffffe))
0033 #define TMIOFB_ACC_PHPIX(x) (0x04000000 | ((x) & 0x000003ff))
0034 #define TMIOFB_ACC_PVPIX(x) (0x05000000 | ((x) & 0x000003ff))
0035 #define TMIOFB_ACC_PHOFS(x) (0x06000000 | ((x) & 0x000003ff))
0036 #define TMIOFB_ACC_PVOFS(x) (0x07000000 | ((x) & 0x000003ff))
0037 #define TMIOFB_ACC_POADR(x) (0x08000000 | ((x) & 0x00fffffe))
0038 #define TMIOFB_ACC_RSTR(x)  (0x09000000 | ((x) & 0x000000ff))
0039 #define TMIOFB_ACC_TCLOR(x) (0x0A000000 | ((x) & 0x0000ffff))
0040 #define TMIOFB_ACC_FILL(x)  (0x0B000000 | ((x) & 0x0000ffff))
0041 #define TMIOFB_ACC_DSADR(x) (0x0C000000 | ((x) & 0x00fffffe))
0042 #define TMIOFB_ACC_SSADR(x) (0x0D000000 | ((x) & 0x00fffffe))
0043 #define TMIOFB_ACC_DHPIX(x) (0x0E000000 | ((x) & 0x000003ff))
0044 #define TMIOFB_ACC_DVPIX(x) (0x0F000000 | ((x) & 0x000003ff))
0045 #define TMIOFB_ACC_SHPIX(x) (0x10000000 | ((x) & 0x000003ff))
0046 #define TMIOFB_ACC_SVPIX(x) (0x11000000 | ((x) & 0x000003ff))
0047 #define TMIOFB_ACC_LBINI(x) (0x12000000 | ((x) & 0x0000ffff))
0048 #define TMIOFB_ACC_LBK2(x)  (0x13000000 | ((x) & 0x0000ffff))
0049 #define TMIOFB_ACC_SHBINI(x)    (0x14000000 | ((x) & 0x0000ffff))
0050 #define TMIOFB_ACC_SHBK2(x) (0x15000000 | ((x) & 0x0000ffff))
0051 #define TMIOFB_ACC_SVBINI(x)    (0x16000000 | ((x) & 0x0000ffff))
0052 #define TMIOFB_ACC_SVBK2(x) (0x17000000 | ((x) & 0x0000ffff))
0053 
0054 #define TMIOFB_ACC_CMGO     0x20000000
0055 #define TMIOFB_ACC_CMGO_CEND    0x00000001
0056 #define TMIOFB_ACC_CMGO_INT 0x00000002
0057 #define TMIOFB_ACC_CMGO_CMOD    0x00000010
0058 #define TMIOFB_ACC_CMGO_CDVRV   0x00000020
0059 #define TMIOFB_ACC_CMGO_CDHRV   0x00000040
0060 #define TMIOFB_ACC_CMGO_RUND    0x00008000
0061 #define TMIOFB_ACC_SCGO     0x21000000
0062 #define TMIOFB_ACC_SCGO_CEND    0x00000001
0063 #define TMIOFB_ACC_SCGO_INT 0x00000002
0064 #define TMIOFB_ACC_SCGO_ROP3    0x00000004
0065 #define TMIOFB_ACC_SCGO_TRNS    0x00000008
0066 #define TMIOFB_ACC_SCGO_DVRV    0x00000010
0067 #define TMIOFB_ACC_SCGO_DHRV    0x00000020
0068 #define TMIOFB_ACC_SCGO_SVRV    0x00000040
0069 #define TMIOFB_ACC_SCGO_SHRV    0x00000080
0070 #define TMIOFB_ACC_SCGO_DSTXY   0x00008000
0071 #define TMIOFB_ACC_SBGO     0x22000000
0072 #define TMIOFB_ACC_SBGO_CEND    0x00000001
0073 #define TMIOFB_ACC_SBGO_INT 0x00000002
0074 #define TMIOFB_ACC_SBGO_DVRV    0x00000010
0075 #define TMIOFB_ACC_SBGO_DHRV    0x00000020
0076 #define TMIOFB_ACC_SBGO_SVRV    0x00000040
0077 #define TMIOFB_ACC_SBGO_SHRV    0x00000080
0078 #define TMIOFB_ACC_SBGO_SBMD    0x00000100
0079 #define TMIOFB_ACC_FLGO     0x23000000
0080 #define TMIOFB_ACC_FLGO_CEND    0x00000001
0081 #define TMIOFB_ACC_FLGO_INT 0x00000002
0082 #define TMIOFB_ACC_FLGO_ROP3    0x00000004
0083 #define TMIOFB_ACC_LDGO     0x24000000
0084 #define TMIOFB_ACC_LDGO_CEND    0x00000001
0085 #define TMIOFB_ACC_LDGO_INT 0x00000002
0086 #define TMIOFB_ACC_LDGO_ROP3    0x00000004
0087 #define TMIOFB_ACC_LDGO_ENDPX   0x00000008
0088 #define TMIOFB_ACC_LDGO_LVRV    0x00000010
0089 #define TMIOFB_ACC_LDGO_LHRV    0x00000020
0090 #define TMIOFB_ACC_LDGO_LDMOD   0x00000040
0091 
0092 /* a FIFO is always allocated, even if acceleration is not used */
0093 #define TMIOFB_FIFO_SIZE    512
0094 
0095 /*
0096  * LCD Host Controller Configuration Register
0097  *
0098  * This iomem area supports only 16-bit IO.
0099  */
0100 #define CCR_CMD         0x04 /* Command             */
0101 #define CCR_REVID       0x08 /* Revision ID         */
0102 #define CCR_BASEL       0x10 /* LCD Control Reg Base Addr Low   */
0103 #define CCR_BASEH       0x12 /* LCD Control Reg Base Addr High  */
0104 #define CCR_UGCC        0x40 /* Unified Gated Clock Control */
0105 #define CCR_GCC         0x42 /* Gated Clock Control     */
0106 #define CCR_USC         0x50 /* Unified Software Clear      */
0107 #define CCR_VRAMRTC     0x60 /* VRAM Timing Control     */
0108                 /* 0x61 VRAM Refresh Control        */
0109 #define CCR_VRAMSAC     0x62 /* VRAM Access Control     */
0110                 /* 0x63 VRAM Status         */
0111 #define CCR_VRAMBC      0x64 /* VRAM Block Control      */
0112 
0113 /*
0114  * LCD Control Register
0115  *
0116  * This iomem area supports only 16-bit IO.
0117  */
0118 #define LCR_UIS         0x000 /* Unified Interrupt Status   */
0119 #define LCR_VHPN        0x008 /* VRAM Horizontal Pixel Number   */
0120 #define LCR_CFSAL       0x00a /* Command FIFO Start Address Low */
0121 #define LCR_CFSAH       0x00c /* Command FIFO Start Address High */
0122 #define LCR_CFS         0x00e /* Command FIFO Size      */
0123 #define LCR_CFWS        0x010 /* Command FIFO Writeable Size    */
0124 #define LCR_BBIE        0x012 /* BitBLT Interrupt Enable    */
0125 #define LCR_BBISC       0x014 /* BitBLT Interrupt Status and Clear */
0126 #define LCR_CCS         0x016 /* Command Count Status       */
0127 #define LCR_BBES        0x018 /* BitBLT Execution Status    */
0128 #define LCR_CMDL        0x01c /* Command Low            */
0129 #define LCR_CMDH        0x01e /* Command High           */
0130 #define LCR_CFC         0x022 /* Command FIFO Clear     */
0131 #define LCR_CCIFC       0x024 /* CMOS Camera IF Control     */
0132 #define LCR_HWT         0x026 /* Hardware Test          */
0133 #define LCR_LCDCCRC     0x100 /* LCDC Clock and Reset Control   */
0134 #define LCR_LCDCC       0x102 /* LCDC Control           */
0135 #define LCR_LCDCOPC     0x104 /* LCDC Output Pin Control    */
0136 #define LCR_LCDIS       0x108 /* LCD Interrupt Status       */
0137 #define LCR_LCDIM       0x10a /* LCD Interrupt Mask     */
0138 #define LCR_LCDIE       0x10c /* LCD Interrupt Enable       */
0139 #define LCR_GDSAL       0x122 /* Graphics Display Start Address Low */
0140 #define LCR_GDSAH       0x124 /* Graphics Display Start Address High */
0141 #define LCR_VHPCL       0x12a /* VRAM Horizontal Pixel Count Low */
0142 #define LCR_VHPCH       0x12c /* VRAM Horizontal Pixel Count High */
0143 #define LCR_GM          0x12e /* Graphic Mode(VRAM access enable) */
0144 #define LCR_HT          0x140 /* Horizontal Total       */
0145 #define LCR_HDS         0x142 /* Horizontal Display Start   */
0146 #define LCR_HSS         0x144 /* H-Sync Start           */
0147 #define LCR_HSE         0x146 /* H-Sync End         */
0148 #define LCR_HNP         0x14c /* Horizontal Number of Pixels    */
0149 #define LCR_VT          0x150 /* Vertical Total         */
0150 #define LCR_VDS         0x152 /* Vertical Display Start     */
0151 #define LCR_VSS         0x154 /* V-Sync Start           */
0152 #define LCR_VSE         0x156 /* V-Sync End         */
0153 #define LCR_CDLN        0x160 /* Current Display Line Number    */
0154 #define LCR_ILN         0x162 /* Interrupt Line Number      */
0155 #define LCR_SP          0x164 /* Sync Polarity          */
0156 #define LCR_MISC        0x166 /* MISC(RGB565 mode)      */
0157 #define LCR_VIHSS       0x16a /* Video Interface H-Sync Start   */
0158 #define LCR_VIVS        0x16c /* Video Interface Vertical Start */
0159 #define LCR_VIVE        0x16e /* Video Interface Vertical End   */
0160 #define LCR_VIVSS       0x170 /* Video Interface V-Sync Start   */
0161 #define LCR_VCCIS       0x17e /* Video / CMOS Camera Interface Select */
0162 #define LCR_VIDWSAL     0x180 /* VI Data Write Start Address Low */
0163 #define LCR_VIDWSAH     0x182 /* VI Data Write Start Address High */
0164 #define LCR_VIDRSAL     0x184 /* VI Data Read Start Address Low */
0165 #define LCR_VIDRSAH     0x186 /* VI Data Read Start Address High */
0166 #define LCR_VIPDDST     0x188 /* VI Picture Data Display Start Timing */
0167 #define LCR_VIPDDET     0x186 /* VI Picture Data Display End Timing */
0168 #define LCR_VIE         0x18c /* Video Interface Enable     */
0169 #define LCR_VCS         0x18e /* Video/Camera Select        */
0170 #define LCR_VPHWC       0x194 /* Video Picture Horizontal Wait Count */
0171 #define LCR_VPHS        0x196 /* Video Picture Horizontal Size  */
0172 #define LCR_VPVWC       0x198 /* Video Picture Vertical Wait Count */
0173 #define LCR_VPVS        0x19a /* Video Picture Vertical Size    */
0174 #define LCR_PLHPIX      0x1a0 /* PLHPIX             */
0175 #define LCR_XS          0x1a2 /* XStart             */
0176 #define LCR_XCKHW       0x1a4 /* XCK High Width         */
0177 #define LCR_STHS        0x1a8 /* STH Start          */
0178 #define LCR_VT2         0x1aa /* Vertical Total         */
0179 #define LCR_YCKSW       0x1ac /* YCK Start Wait         */
0180 #define LCR_YSTS        0x1ae /* YST Start          */
0181 #define LCR_PPOLS       0x1b0 /* #PPOL Start            */
0182 #define LCR_PRECW       0x1b2 /* PREC Width         */
0183 #define LCR_VCLKHW      0x1b4 /* VCLK High Width        */
0184 #define LCR_OC          0x1b6 /* Output Control         */
0185 
0186 static char *mode_option;
0187 
0188 struct tmiofb_par {
0189     u32             pseudo_palette[16];
0190 
0191 #ifdef CONFIG_FB_TMIO_ACCELL
0192     wait_queue_head_t       wait_acc;
0193     bool                use_polling;
0194 #endif
0195 
0196     void __iomem            *ccr;
0197     void __iomem            *lcr;
0198 };
0199 
0200 /*--------------------------------------------------------------------------*/
0201 
0202 /*
0203  * reasons for an interrupt:
0204  *  uis bbisc   lcdis
0205  *  0100    0001    accelerator command completed
0206  *  2000    0001    vsync start
0207  *  2000    0002    display start
0208  *  2000    0004    line number match(0x1ff mask???)
0209  */
0210 static irqreturn_t tmiofb_irq(int irq, void *__info)
0211 {
0212     struct fb_info *info = __info;
0213     struct tmiofb_par *par = info->par;
0214     unsigned int bbisc = tmio_ioread16(par->lcr + LCR_BBISC);
0215 
0216 
0217     tmio_iowrite16(bbisc, par->lcr + LCR_BBISC);
0218 
0219 #ifdef CONFIG_FB_TMIO_ACCELL
0220     /*
0221      * We were in polling mode and now we got correct irq.
0222      * Switch back to IRQ-based sync of command FIFO
0223      */
0224     if (unlikely(par->use_polling && irq != -1)) {
0225         printk(KERN_INFO "tmiofb: switching to waitq\n");
0226         par->use_polling = false;
0227     }
0228 
0229     if (bbisc & 1)
0230         wake_up(&par->wait_acc);
0231 #endif
0232 
0233     return IRQ_HANDLED;
0234 }
0235 
0236 
0237 /*--------------------------------------------------------------------------*/
0238 
0239 
0240 /*
0241  * Turns off the LCD controller and LCD host controller.
0242  */
0243 static int tmiofb_hw_stop(struct platform_device *dev)
0244 {
0245     struct tmio_fb_data *data = dev_get_platdata(&dev->dev);
0246     struct fb_info *info = platform_get_drvdata(dev);
0247     struct tmiofb_par *par = info->par;
0248 
0249     tmio_iowrite16(0, par->ccr + CCR_UGCC);
0250     tmio_iowrite16(0, par->lcr + LCR_GM);
0251     data->lcd_set_power(dev, 0);
0252     tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);
0253 
0254     return 0;
0255 }
0256 
0257 /*
0258  * Initializes the LCD host controller.
0259  */
0260 static int tmiofb_hw_init(struct platform_device *dev)
0261 {
0262     const struct mfd_cell *cell = mfd_get_cell(dev);
0263     struct fb_info *info = platform_get_drvdata(dev);
0264     struct tmiofb_par *par = info->par;
0265     const struct resource *nlcr = &cell->resources[0];
0266     const struct resource *vram = &cell->resources[2];
0267     unsigned long base;
0268 
0269     if (nlcr == NULL || vram == NULL)
0270         return -EINVAL;
0271 
0272     base = nlcr->start;
0273 
0274     tmio_iowrite16(0x003a, par->ccr + CCR_UGCC);
0275     tmio_iowrite16(0x003a, par->ccr + CCR_GCC);
0276     tmio_iowrite16(0x3f00, par->ccr + CCR_USC);
0277 
0278     msleep(2); /* wait for device to settle */
0279 
0280     tmio_iowrite16(0x0000, par->ccr + CCR_USC);
0281     tmio_iowrite16(base >> 16, par->ccr + CCR_BASEH);
0282     tmio_iowrite16(base, par->ccr + CCR_BASEL);
0283     tmio_iowrite16(0x0002, par->ccr + CCR_CMD); /* base address enable */
0284     tmio_iowrite16(0x40a8, par->ccr + CCR_VRAMRTC); /* VRAMRC, VRAMTC */
0285     tmio_iowrite16(0x0018, par->ccr + CCR_VRAMSAC); /* VRAMSTS, VRAMAC */
0286     tmio_iowrite16(0x0002, par->ccr + CCR_VRAMBC);
0287     msleep(2); /* wait for device to settle */
0288     tmio_iowrite16(0x000b, par->ccr + CCR_VRAMBC);
0289 
0290     base = vram->start + info->screen_size;
0291     tmio_iowrite16(base >> 16, par->lcr + LCR_CFSAH);
0292     tmio_iowrite16(base, par->lcr + LCR_CFSAL);
0293     tmio_iowrite16(TMIOFB_FIFO_SIZE - 1, par->lcr + LCR_CFS);
0294     tmio_iowrite16(1, par->lcr + LCR_CFC);
0295     tmio_iowrite16(1, par->lcr + LCR_BBIE);
0296     tmio_iowrite16(0, par->lcr + LCR_CFWS);
0297 
0298     return 0;
0299 }
0300 
0301 /*
0302  * Sets the LCD controller's output resolution and pixel clock
0303  */
0304 static void tmiofb_hw_mode(struct platform_device *dev)
0305 {
0306     struct tmio_fb_data *data = dev_get_platdata(&dev->dev);
0307     struct fb_info *info = platform_get_drvdata(dev);
0308     struct fb_videomode *mode = info->mode;
0309     struct tmiofb_par *par = info->par;
0310     unsigned int i;
0311 
0312     tmio_iowrite16(0, par->lcr + LCR_GM);
0313     data->lcd_set_power(dev, 0);
0314     tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);
0315     data->lcd_mode(dev, mode);
0316     data->lcd_set_power(dev, 1);
0317 
0318     tmio_iowrite16(info->fix.line_length, par->lcr + LCR_VHPN);
0319     tmio_iowrite16(0, par->lcr + LCR_GDSAH);
0320     tmio_iowrite16(0, par->lcr + LCR_GDSAL);
0321     tmio_iowrite16(info->fix.line_length >> 16, par->lcr + LCR_VHPCH);
0322     tmio_iowrite16(info->fix.line_length, par->lcr + LCR_VHPCL);
0323     tmio_iowrite16(i = 0, par->lcr + LCR_HSS);
0324     tmio_iowrite16(i += mode->hsync_len, par->lcr + LCR_HSE);
0325     tmio_iowrite16(i += mode->left_margin, par->lcr + LCR_HDS);
0326     tmio_iowrite16(i += mode->xres + mode->right_margin, par->lcr + LCR_HT);
0327     tmio_iowrite16(mode->xres, par->lcr + LCR_HNP);
0328     tmio_iowrite16(i = 0, par->lcr + LCR_VSS);
0329     tmio_iowrite16(i += mode->vsync_len, par->lcr + LCR_VSE);
0330     tmio_iowrite16(i += mode->upper_margin, par->lcr + LCR_VDS);
0331     tmio_iowrite16(i += mode->yres, par->lcr + LCR_ILN);
0332     tmio_iowrite16(i += mode->lower_margin, par->lcr + LCR_VT);
0333     tmio_iowrite16(3, par->lcr + LCR_MISC); /* RGB565 mode */
0334     tmio_iowrite16(1, par->lcr + LCR_GM); /* VRAM enable */
0335     tmio_iowrite16(0x4007, par->lcr + LCR_LCDCC);
0336     tmio_iowrite16(3, par->lcr + LCR_SP);  /* sync polarity */
0337 
0338     tmio_iowrite16(0x0010, par->lcr + LCR_LCDCCRC);
0339     msleep(5); /* wait for device to settle */
0340     tmio_iowrite16(0x0014, par->lcr + LCR_LCDCCRC); /* STOP_CKP */
0341     msleep(5); /* wait for device to settle */
0342     tmio_iowrite16(0x0015, par->lcr + LCR_LCDCCRC); /* STOP_CKP|SOFT_RESET*/
0343     tmio_iowrite16(0xfffa, par->lcr + LCR_VCS);
0344 }
0345 
0346 /*--------------------------------------------------------------------------*/
0347 
0348 #ifdef CONFIG_FB_TMIO_ACCELL
0349 static int __must_check
0350 tmiofb_acc_wait(struct fb_info *info, unsigned int ccs)
0351 {
0352     struct tmiofb_par *par = info->par;
0353     /*
0354      * This code can be called with interrupts disabled.
0355      * So instead of relaying on irq to trigger the event,
0356      * poll the state till the necessary command is executed.
0357      */
0358     if (irqs_disabled() || par->use_polling) {
0359         int i = 0;
0360         while (tmio_ioread16(par->lcr + LCR_CCS) > ccs) {
0361             udelay(1);
0362             i++;
0363             if (i > 10000) {
0364                 pr_err("tmiofb: timeout waiting for %d\n",
0365                         ccs);
0366                 return -ETIMEDOUT;
0367             }
0368             tmiofb_irq(-1, info);
0369         }
0370     } else {
0371         if (!wait_event_interruptible_timeout(par->wait_acc,
0372                 tmio_ioread16(par->lcr + LCR_CCS) <= ccs,
0373                 1000)) {
0374             pr_err("tmiofb: timeout waiting for %d\n", ccs);
0375             return -ETIMEDOUT;
0376         }
0377     }
0378 
0379     return 0;
0380 }
0381 
0382 /*
0383  * Writes an accelerator command to the accelerator's FIFO.
0384  */
0385 static int
0386 tmiofb_acc_write(struct fb_info *info, const u32 *cmd, unsigned int count)
0387 {
0388     struct tmiofb_par *par = info->par;
0389     int ret;
0390 
0391     ret = tmiofb_acc_wait(info, TMIOFB_FIFO_SIZE - count);
0392     if (ret)
0393         return ret;
0394 
0395     for (; count; count--, cmd++) {
0396         tmio_iowrite16(*cmd >> 16, par->lcr + LCR_CMDH);
0397         tmio_iowrite16(*cmd, par->lcr + LCR_CMDL);
0398     }
0399 
0400     return ret;
0401 }
0402 
0403 /*
0404  * Wait for the accelerator to finish its operations before writing
0405  * to the framebuffer for consistent display output.
0406  */
0407 static int tmiofb_sync(struct fb_info *fbi)
0408 {
0409     struct tmiofb_par *par = fbi->par;
0410 
0411     int ret;
0412     int i = 0;
0413 
0414     ret = tmiofb_acc_wait(fbi, 0);
0415 
0416     while (tmio_ioread16(par->lcr + LCR_BBES) & 2) { /* blit active */
0417         udelay(1);
0418         i++ ;
0419         if (i > 10000) {
0420             printk(KERN_ERR "timeout waiting for blit to end!\n");
0421             return -ETIMEDOUT;
0422         }
0423     }
0424 
0425     return ret;
0426 }
0427 
0428 static void
0429 tmiofb_fillrect(struct fb_info *fbi, const struct fb_fillrect *rect)
0430 {
0431     const u32 cmd[] = {
0432         TMIOFB_ACC_DSADR((rect->dy * fbi->mode->xres + rect->dx) * 2),
0433         TMIOFB_ACC_DHPIX(rect->width - 1),
0434         TMIOFB_ACC_DVPIX(rect->height - 1),
0435         TMIOFB_ACC_FILL(rect->color),
0436         TMIOFB_ACC_FLGO,
0437     };
0438 
0439     if (fbi->state != FBINFO_STATE_RUNNING ||
0440         fbi->flags & FBINFO_HWACCEL_DISABLED) {
0441         cfb_fillrect(fbi, rect);
0442         return;
0443     }
0444 
0445     tmiofb_acc_write(fbi, cmd, ARRAY_SIZE(cmd));
0446 }
0447 
0448 static void
0449 tmiofb_copyarea(struct fb_info *fbi, const struct fb_copyarea *area)
0450 {
0451     const u32 cmd[] = {
0452         TMIOFB_ACC_DSADR((area->dy * fbi->mode->xres + area->dx) * 2),
0453         TMIOFB_ACC_DHPIX(area->width - 1),
0454         TMIOFB_ACC_DVPIX(area->height - 1),
0455         TMIOFB_ACC_SSADR((area->sy * fbi->mode->xres + area->sx) * 2),
0456         TMIOFB_ACC_SCGO,
0457     };
0458 
0459     if (fbi->state != FBINFO_STATE_RUNNING ||
0460         fbi->flags & FBINFO_HWACCEL_DISABLED) {
0461         cfb_copyarea(fbi, area);
0462         return;
0463     }
0464 
0465     tmiofb_acc_write(fbi, cmd, ARRAY_SIZE(cmd));
0466 }
0467 #endif
0468 
0469 static void tmiofb_clearscreen(struct fb_info *info)
0470 {
0471     const struct fb_fillrect rect = {
0472         .dx = 0,
0473         .dy = 0,
0474         .width  = info->mode->xres,
0475         .height = info->mode->yres,
0476         .color  = 0,
0477         .rop    = ROP_COPY,
0478     };
0479 
0480     info->fbops->fb_fillrect(info, &rect);
0481 }
0482 
0483 static int tmiofb_vblank(struct fb_info *fbi, struct fb_vblank *vblank)
0484 {
0485     struct tmiofb_par *par = fbi->par;
0486     struct fb_videomode *mode = fbi->mode;
0487     unsigned int vcount = tmio_ioread16(par->lcr + LCR_CDLN);
0488     unsigned int vds = mode->vsync_len + mode->upper_margin;
0489 
0490     vblank->vcount = vcount;
0491     vblank->flags = FB_VBLANK_HAVE_VBLANK | FB_VBLANK_HAVE_VCOUNT
0492                         | FB_VBLANK_HAVE_VSYNC;
0493 
0494     if (vcount < mode->vsync_len)
0495         vblank->flags |= FB_VBLANK_VSYNCING;
0496 
0497     if (vcount < vds || vcount > vds + mode->yres)
0498         vblank->flags |= FB_VBLANK_VBLANKING;
0499 
0500     return 0;
0501 }
0502 
0503 
0504 static int tmiofb_ioctl(struct fb_info *fbi,
0505         unsigned int cmd, unsigned long arg)
0506 {
0507     switch (cmd) {
0508     case FBIOGET_VBLANK: {
0509         struct fb_vblank vblank = {0};
0510         void __user *argp = (void __user *) arg;
0511 
0512         tmiofb_vblank(fbi, &vblank);
0513         if (copy_to_user(argp, &vblank, sizeof vblank))
0514             return -EFAULT;
0515         return 0;
0516     }
0517 
0518 #ifdef CONFIG_FB_TMIO_ACCELL
0519     case FBIO_TMIO_ACC_SYNC:
0520         tmiofb_sync(fbi);
0521         return 0;
0522 
0523     case FBIO_TMIO_ACC_WRITE: {
0524         u32 __user *argp = (void __user *) arg;
0525         u32 len;
0526         u32 acc[16];
0527 
0528         if (get_user(len, argp))
0529             return -EFAULT;
0530         if (len > ARRAY_SIZE(acc))
0531             return -EINVAL;
0532         if (copy_from_user(acc, argp + 1, sizeof(u32) * len))
0533             return -EFAULT;
0534 
0535         return tmiofb_acc_write(fbi, acc, len);
0536     }
0537 #endif
0538     }
0539 
0540     return -ENOTTY;
0541 }
0542 
0543 /*--------------------------------------------------------------------------*/
0544 
0545 /* Select the smallest mode that allows the desired resolution to be
0546  * displayed.  If desired, the x and y parameters can be rounded up to
0547  * match the selected mode.
0548  */
0549 static struct fb_videomode *
0550 tmiofb_find_mode(struct fb_info *info, struct fb_var_screeninfo *var)
0551 {
0552     struct tmio_fb_data *data = dev_get_platdata(info->device);
0553     struct fb_videomode *best = NULL;
0554     int i;
0555 
0556     for (i = 0; i < data->num_modes; i++) {
0557         struct fb_videomode *mode = data->modes + i;
0558 
0559         if (mode->xres >= var->xres && mode->yres >= var->yres
0560                 && (!best || (mode->xres < best->xres
0561                        && mode->yres < best->yres)))
0562             best = mode;
0563     }
0564 
0565     return best;
0566 }
0567 
0568 static int tmiofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
0569 {
0570 
0571     struct fb_videomode *mode;
0572     struct tmio_fb_data *data = dev_get_platdata(info->device);
0573 
0574     mode = tmiofb_find_mode(info, var);
0575     if (!mode || var->bits_per_pixel > 16)
0576         return -EINVAL;
0577 
0578     fb_videomode_to_var(var, mode);
0579 
0580     var->xres_virtual = mode->xres;
0581     var->yres_virtual = info->screen_size / (mode->xres * 2);
0582 
0583     if (var->yres_virtual < var->yres)
0584         return -EINVAL;
0585 
0586     var->xoffset = 0;
0587     var->yoffset = 0;
0588     var->bits_per_pixel = 16;
0589     var->grayscale = 0;
0590     var->red.offset = 11;
0591     var->red.length = 5;
0592     var->green.offset = 5;
0593     var->green.length = 6;
0594     var->blue.offset = 0;
0595     var->blue.length = 5;
0596     var->transp.offset = 0;
0597     var->transp.length = 0;
0598     var->nonstd = 0;
0599     var->height = data->height; /* mm */
0600     var->width = data->width; /* mm */
0601     var->rotate = 0;
0602     return 0;
0603 }
0604 
0605 static int tmiofb_set_par(struct fb_info *info)
0606 {
0607     struct fb_var_screeninfo *var = &info->var;
0608     struct fb_videomode *mode;
0609 
0610     mode = tmiofb_find_mode(info, var);
0611     if (!mode)
0612         return -EINVAL;
0613 
0614     info->mode = mode;
0615     info->fix.line_length = info->mode->xres *
0616             var->bits_per_pixel / 8;
0617 
0618     tmiofb_hw_mode(to_platform_device(info->device));
0619     tmiofb_clearscreen(info);
0620     return 0;
0621 }
0622 
0623 static int tmiofb_setcolreg(unsigned regno, unsigned red, unsigned green,
0624                unsigned blue, unsigned transp,
0625                struct fb_info *info)
0626 {
0627     struct tmiofb_par *par = info->par;
0628 
0629     if (regno < ARRAY_SIZE(par->pseudo_palette)) {
0630         par->pseudo_palette[regno] =
0631             ((red & 0xf800)) |
0632             ((green & 0xfc00) >>  5) |
0633             ((blue & 0xf800) >> 11);
0634         return 0;
0635     }
0636 
0637     return -EINVAL;
0638 }
0639 
0640 static int tmiofb_blank(int blank, struct fb_info *info)
0641 {
0642     /*
0643      * everything is done in lcd/bl drivers.
0644      * this is purely to make sysfs happy and work.
0645      */
0646     return 0;
0647 }
0648 
0649 static const struct fb_ops tmiofb_ops = {
0650     .owner      = THIS_MODULE,
0651 
0652     .fb_ioctl   = tmiofb_ioctl,
0653     .fb_check_var   = tmiofb_check_var,
0654     .fb_set_par = tmiofb_set_par,
0655     .fb_setcolreg   = tmiofb_setcolreg,
0656     .fb_blank   = tmiofb_blank,
0657     .fb_imageblit   = cfb_imageblit,
0658 #ifdef CONFIG_FB_TMIO_ACCELL
0659     .fb_sync    = tmiofb_sync,
0660     .fb_fillrect    = tmiofb_fillrect,
0661     .fb_copyarea    = tmiofb_copyarea,
0662 #else
0663     .fb_fillrect    = cfb_fillrect,
0664     .fb_copyarea    = cfb_copyarea,
0665 #endif
0666 };
0667 
0668 /*--------------------------------------------------------------------------*/
0669 
0670 static int tmiofb_probe(struct platform_device *dev)
0671 {
0672     const struct mfd_cell *cell = mfd_get_cell(dev);
0673     struct tmio_fb_data *data = dev_get_platdata(&dev->dev);
0674     struct resource *ccr = platform_get_resource(dev, IORESOURCE_MEM, 1);
0675     struct resource *lcr = platform_get_resource(dev, IORESOURCE_MEM, 0);
0676     struct resource *vram = platform_get_resource(dev, IORESOURCE_MEM, 2);
0677     int irq = platform_get_irq(dev, 0);
0678     struct fb_info *info;
0679     struct tmiofb_par *par;
0680     int retval;
0681 
0682     /*
0683      * This is the only way ATM to disable the fb
0684      */
0685     if (data == NULL) {
0686         dev_err(&dev->dev, "NULL platform data!\n");
0687         return -EINVAL;
0688     }
0689     if (ccr == NULL || lcr == NULL || vram == NULL || irq < 0) {
0690         dev_err(&dev->dev, "missing resources\n");
0691         return -EINVAL;
0692     }
0693 
0694     info = framebuffer_alloc(sizeof(struct tmiofb_par), &dev->dev);
0695 
0696     if (!info)
0697         return -ENOMEM;
0698 
0699     par = info->par;
0700 
0701 #ifdef CONFIG_FB_TMIO_ACCELL
0702     init_waitqueue_head(&par->wait_acc);
0703 
0704     par->use_polling = true;
0705 
0706     info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA
0707             | FBINFO_HWACCEL_FILLRECT;
0708 #else
0709     info->flags = FBINFO_DEFAULT;
0710 #endif
0711 
0712     info->fbops = &tmiofb_ops;
0713 
0714     strcpy(info->fix.id, "tmio-fb");
0715     info->fix.smem_start = vram->start;
0716     info->fix.smem_len = resource_size(vram);
0717     info->fix.type = FB_TYPE_PACKED_PIXELS;
0718     info->fix.visual = FB_VISUAL_TRUECOLOR;
0719     info->fix.mmio_start = lcr->start;
0720     info->fix.mmio_len = resource_size(lcr);
0721     info->fix.accel = FB_ACCEL_NONE;
0722     info->screen_size = info->fix.smem_len - (4 * TMIOFB_FIFO_SIZE);
0723     info->pseudo_palette = par->pseudo_palette;
0724 
0725     par->ccr = ioremap(ccr->start, resource_size(ccr));
0726     if (!par->ccr) {
0727         retval = -ENOMEM;
0728         goto err_ioremap_ccr;
0729     }
0730 
0731     par->lcr = ioremap(info->fix.mmio_start, info->fix.mmio_len);
0732     if (!par->lcr) {
0733         retval = -ENOMEM;
0734         goto err_ioremap_lcr;
0735     }
0736 
0737     info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
0738     if (!info->screen_base) {
0739         retval = -ENOMEM;
0740         goto err_ioremap_vram;
0741     }
0742 
0743     retval = request_irq(irq, &tmiofb_irq, 0,
0744                     dev_name(&dev->dev), info);
0745 
0746     if (retval)
0747         goto err_request_irq;
0748 
0749     platform_set_drvdata(dev, info);
0750 
0751     retval = fb_find_mode(&info->var, info, mode_option,
0752             data->modes, data->num_modes,
0753             data->modes, 16);
0754     if (!retval) {
0755         retval = -EINVAL;
0756         goto err_find_mode;
0757     }
0758 
0759     if (cell->enable) {
0760         retval = cell->enable(dev);
0761         if (retval)
0762             goto err_enable;
0763     }
0764 
0765     retval = tmiofb_hw_init(dev);
0766     if (retval)
0767         goto err_hw_init;
0768 
0769     fb_videomode_to_modelist(data->modes, data->num_modes,
0770                  &info->modelist);
0771 
0772     retval = register_framebuffer(info);
0773     if (retval < 0)
0774         goto err_register_framebuffer;
0775 
0776     fb_info(info, "%s frame buffer device\n", info->fix.id);
0777 
0778     return 0;
0779 
0780 err_register_framebuffer:
0781 /*err_set_par:*/
0782     tmiofb_hw_stop(dev);
0783 err_hw_init:
0784     if (cell->disable)
0785         cell->disable(dev);
0786 err_enable:
0787 err_find_mode:
0788     free_irq(irq, info);
0789 err_request_irq:
0790     iounmap(info->screen_base);
0791 err_ioremap_vram:
0792     iounmap(par->lcr);
0793 err_ioremap_lcr:
0794     iounmap(par->ccr);
0795 err_ioremap_ccr:
0796     framebuffer_release(info);
0797     return retval;
0798 }
0799 
0800 static int tmiofb_remove(struct platform_device *dev)
0801 {
0802     const struct mfd_cell *cell = mfd_get_cell(dev);
0803     struct fb_info *info = platform_get_drvdata(dev);
0804     int irq = platform_get_irq(dev, 0);
0805     struct tmiofb_par *par;
0806 
0807     if (info) {
0808         par = info->par;
0809         unregister_framebuffer(info);
0810 
0811         tmiofb_hw_stop(dev);
0812 
0813         if (cell->disable)
0814             cell->disable(dev);
0815 
0816         free_irq(irq, info);
0817 
0818         iounmap(info->screen_base);
0819         iounmap(par->lcr);
0820         iounmap(par->ccr);
0821 
0822         framebuffer_release(info);
0823     }
0824 
0825     return 0;
0826 }
0827 
0828 #ifdef DEBUG
0829 static void tmiofb_dump_regs(struct platform_device *dev)
0830 {
0831     struct fb_info *info = platform_get_drvdata(dev);
0832     struct tmiofb_par *par = info->par;
0833 
0834     printk(KERN_DEBUG "lhccr:\n");
0835 #define CCR_PR(n)   printk(KERN_DEBUG "\t" #n " = \t%04x\n",\
0836         tmio_ioread16(par->ccr + CCR_ ## n));
0837     CCR_PR(CMD);
0838     CCR_PR(REVID);
0839     CCR_PR(BASEL);
0840     CCR_PR(BASEH);
0841     CCR_PR(UGCC);
0842     CCR_PR(GCC);
0843     CCR_PR(USC);
0844     CCR_PR(VRAMRTC);
0845     CCR_PR(VRAMSAC);
0846     CCR_PR(VRAMBC);
0847 #undef CCR_PR
0848 
0849     printk(KERN_DEBUG "lcr: \n");
0850 #define LCR_PR(n)   printk(KERN_DEBUG "\t" #n " = \t%04x\n",\
0851         tmio_ioread16(par->lcr + LCR_ ## n));
0852     LCR_PR(UIS);
0853     LCR_PR(VHPN);
0854     LCR_PR(CFSAL);
0855     LCR_PR(CFSAH);
0856     LCR_PR(CFS);
0857     LCR_PR(CFWS);
0858     LCR_PR(BBIE);
0859     LCR_PR(BBISC);
0860     LCR_PR(CCS);
0861     LCR_PR(BBES);
0862     LCR_PR(CMDL);
0863     LCR_PR(CMDH);
0864     LCR_PR(CFC);
0865     LCR_PR(CCIFC);
0866     LCR_PR(HWT);
0867     LCR_PR(LCDCCRC);
0868     LCR_PR(LCDCC);
0869     LCR_PR(LCDCOPC);
0870     LCR_PR(LCDIS);
0871     LCR_PR(LCDIM);
0872     LCR_PR(LCDIE);
0873     LCR_PR(GDSAL);
0874     LCR_PR(GDSAH);
0875     LCR_PR(VHPCL);
0876     LCR_PR(VHPCH);
0877     LCR_PR(GM);
0878     LCR_PR(HT);
0879     LCR_PR(HDS);
0880     LCR_PR(HSS);
0881     LCR_PR(HSE);
0882     LCR_PR(HNP);
0883     LCR_PR(VT);
0884     LCR_PR(VDS);
0885     LCR_PR(VSS);
0886     LCR_PR(VSE);
0887     LCR_PR(CDLN);
0888     LCR_PR(ILN);
0889     LCR_PR(SP);
0890     LCR_PR(MISC);
0891     LCR_PR(VIHSS);
0892     LCR_PR(VIVS);
0893     LCR_PR(VIVE);
0894     LCR_PR(VIVSS);
0895     LCR_PR(VCCIS);
0896     LCR_PR(VIDWSAL);
0897     LCR_PR(VIDWSAH);
0898     LCR_PR(VIDRSAL);
0899     LCR_PR(VIDRSAH);
0900     LCR_PR(VIPDDST);
0901     LCR_PR(VIPDDET);
0902     LCR_PR(VIE);
0903     LCR_PR(VCS);
0904     LCR_PR(VPHWC);
0905     LCR_PR(VPHS);
0906     LCR_PR(VPVWC);
0907     LCR_PR(VPVS);
0908     LCR_PR(PLHPIX);
0909     LCR_PR(XS);
0910     LCR_PR(XCKHW);
0911     LCR_PR(STHS);
0912     LCR_PR(VT2);
0913     LCR_PR(YCKSW);
0914     LCR_PR(YSTS);
0915     LCR_PR(PPOLS);
0916     LCR_PR(PRECW);
0917     LCR_PR(VCLKHW);
0918     LCR_PR(OC);
0919 #undef LCR_PR
0920 }
0921 #endif
0922 
0923 #ifdef CONFIG_PM
0924 static int tmiofb_suspend(struct platform_device *dev, pm_message_t state)
0925 {
0926     struct fb_info *info = platform_get_drvdata(dev);
0927 #ifdef CONFIG_FB_TMIO_ACCELL
0928     struct tmiofb_par *par = info->par;
0929 #endif
0930     const struct mfd_cell *cell = mfd_get_cell(dev);
0931     int retval = 0;
0932 
0933     console_lock();
0934 
0935     fb_set_suspend(info, 1);
0936 
0937     if (info->fbops->fb_sync)
0938         info->fbops->fb_sync(info);
0939 
0940 
0941 #ifdef CONFIG_FB_TMIO_ACCELL
0942     /*
0943      * The fb should be usable even if interrupts are disabled (and they are
0944      * during suspend/resume). Switch temporary to forced polling.
0945      */
0946     printk(KERN_INFO "tmiofb: switching to polling\n");
0947     par->use_polling = true;
0948 #endif
0949     tmiofb_hw_stop(dev);
0950 
0951     if (cell->suspend)
0952         retval = cell->suspend(dev);
0953 
0954     console_unlock();
0955 
0956     return retval;
0957 }
0958 
0959 static int tmiofb_resume(struct platform_device *dev)
0960 {
0961     struct fb_info *info = platform_get_drvdata(dev);
0962     const struct mfd_cell *cell = mfd_get_cell(dev);
0963     int retval = 0;
0964 
0965     console_lock();
0966 
0967     if (cell->resume) {
0968         retval = cell->resume(dev);
0969         if (retval)
0970             goto out;
0971     }
0972 
0973     tmiofb_irq(-1, info);
0974 
0975     tmiofb_hw_init(dev);
0976 
0977     tmiofb_hw_mode(dev);
0978 
0979     fb_set_suspend(info, 0);
0980 out:
0981     console_unlock();
0982     return retval;
0983 }
0984 #else
0985 #define tmiofb_suspend  NULL
0986 #define tmiofb_resume   NULL
0987 #endif
0988 
0989 static struct platform_driver tmiofb_driver = {
0990     .driver.name    = "tmio-fb",
0991     .driver.owner   = THIS_MODULE,
0992     .probe      = tmiofb_probe,
0993     .remove     = tmiofb_remove,
0994     .suspend    = tmiofb_suspend,
0995     .resume     = tmiofb_resume,
0996 };
0997 
0998 /*--------------------------------------------------------------------------*/
0999 
1000 #ifndef MODULE
1001 static void __init tmiofb_setup(char *options)
1002 {
1003     char *this_opt;
1004 
1005     if (!options || !*options)
1006         return;
1007 
1008     while ((this_opt = strsep(&options, ",")) != NULL) {
1009         if (!*this_opt)
1010             continue;
1011         /*
1012          * FIXME
1013          */
1014     }
1015 }
1016 #endif
1017 
1018 static int __init tmiofb_init(void)
1019 {
1020 #ifndef MODULE
1021     char *option = NULL;
1022 
1023     if (fb_get_options("tmiofb", &option))
1024         return -ENODEV;
1025     tmiofb_setup(option);
1026 #endif
1027     return platform_driver_register(&tmiofb_driver);
1028 }
1029 
1030 static void __exit tmiofb_cleanup(void)
1031 {
1032     platform_driver_unregister(&tmiofb_driver);
1033 }
1034 
1035 module_init(tmiofb_init);
1036 module_exit(tmiofb_cleanup);
1037 
1038 MODULE_DESCRIPTION("TMIO framebuffer driver");
1039 MODULE_AUTHOR("Chris Humbert, Dirk Opfer, Dmitry Baryshkov");
1040 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!