video/fbdev/sa1100fb.h

0001 /*
0002  * linux/drivers/video/sa1100fb.h
0003  *    -- StrongARM 1100 LCD Controller Frame Buffer Device
0004  *
0005  *  Copyright (C) 1999 Eric A. Thomas
0006  *   Based on acornfb.c Copyright (C) Russell King.
0007  *
0008  * This file is subject to the terms and conditions of the GNU General Public
0009  * License.  See the file COPYING in the main directory of this archive
0010  * for more details.
0011  */
0012
0013 struct gpio_desc;
0014
0015 #define LCCR0           0x0000          /* LCD Control Reg. 0 */
0016 #define LCSR            0x0004          /* LCD Status Reg. */
0017 #define DBAR1           0x0010          /* LCD DMA Base Address Reg. channel 1 */
0018 #define DCAR1           0x0014          /* LCD DMA Current Address Reg. channel 1 */
0019 #define DBAR2           0x0018          /* LCD DMA Base Address Reg.  channel 2 */
0020 #define DCAR2           0x001C          /* LCD DMA Current Address Reg. channel 2 */
0021 #define LCCR1           0x0020          /* LCD Control Reg. 1 */
0022 #define LCCR2           0x0024          /* LCD Control Reg. 2 */
0023 #define LCCR3           0x0028          /* LCD Control Reg. 3 */
0024
0025 /* Shadows for LCD controller registers */
0026 struct sa1100fb_lcd_reg {
0027     unsigned long lccr0;
0028     unsigned long lccr1;
0029     unsigned long lccr2;
0030     unsigned long lccr3;
0031 };
0032
0033 struct sa1100fb_info {
0034     struct fb_info      fb;
0035     struct device       *dev;
0036     const struct sa1100fb_rgb *rgb[NR_RGB];
0037     void __iomem        *base;
0038     struct gpio_desc    *shannon_lcden;
0039
0040     /*
0041      * These are the addresses we mapped
0042      * the framebuffer memory region to.
0043      */
0044     dma_addr_t      map_dma;
0045     u_char *        map_cpu;
0046     u_int           map_size;
0047
0048     u_char *        screen_cpu;
0049     dma_addr_t      screen_dma;
0050     u16 *           palette_cpu;
0051     dma_addr_t      palette_dma;
0052     u_int           palette_size;
0053
0054     dma_addr_t      dbar1;
0055     dma_addr_t      dbar2;
0056
0057     u_int           reg_lccr0;
0058     u_int           reg_lccr1;
0059     u_int           reg_lccr2;
0060     u_int           reg_lccr3;
0061
0062     volatile u_char     state;
0063     volatile u_char     task_state;
0064     struct mutex        ctrlr_lock;
0065     wait_queue_head_t   ctrlr_wait;
0066     struct work_struct  task;
0067
0068 #ifdef CONFIG_CPU_FREQ
0069     struct notifier_block   freq_transition;
0070 #endif
0071
0072     const struct sa1100fb_mach_info *inf;
0073     struct clk *clk;
0074
0075     u32 pseudo_palette[16];
0076 };
0077
0078 #define TO_INF(ptr,member)  container_of(ptr,struct sa1100fb_info,member)
0079
0080 #define SA1100_PALETTE_MODE_VAL(bpp)    (((bpp) & 0x018) << 9)
0081
0082 /*
0083  * These are the actions for set_ctrlr_state
0084  */
0085 #define C_DISABLE       (0)
0086 #define C_ENABLE        (1)
0087 #define C_DISABLE_CLKCHANGE (2)
0088 #define C_ENABLE_CLKCHANGE  (3)
0089 #define C_REENABLE      (4)
0090 #define C_DISABLE_PM        (5)
0091 #define C_ENABLE_PM     (6)
0092 #define C_STARTUP       (7)
0093
0094 #define SA1100_NAME "SA1100"
0095
0096 /*
0097  * Minimum X and Y resolutions
0098  */
0099 #define MIN_XRES    64
0100 #define MIN_YRES    64
0101