video/fbdev/s3c2410fb-regs-lcd.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
0004  *            http://www.simtec.co.uk/products/SWLINUX/
0005  */
0006
0007 #ifndef ___ASM_ARCH_REGS_LCD_H
0008 #define ___ASM_ARCH_REGS_LCD_H
0009
0010 /*
0011  * a couple of values are used as platform data in
0012  * include/linux/platform_data/fb-s3c2410.h and not
0013  * duplicated here.
0014  */
0015 #include <linux/platform_data/fb-s3c2410.h>
0016
0017 #define S3C2410_LCDREG(x)   (x)
0018
0019 /* LCD control registers */
0020 #define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
0021 #define S3C2410_LCDCON2     S3C2410_LCDREG(0x04)
0022 #define S3C2410_LCDCON3     S3C2410_LCDREG(0x08)
0023 #define S3C2410_LCDCON4     S3C2410_LCDREG(0x0C)
0024 #define S3C2410_LCDCON5     S3C2410_LCDREG(0x10)
0025
0026 #define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
0027 #define S3C2410_LCDCON1_MMODE      (1<<7)
0028 #define S3C2410_LCDCON1_DSCAN4     (0<<5)
0029 #define S3C2410_LCDCON1_STN4       (1<<5)
0030 #define S3C2410_LCDCON1_STN8       (2<<5)
0031 #define S3C2410_LCDCON1_TFT    (3<<5)
0032
0033 #define S3C2410_LCDCON1_STN1BPP    (0<<1)
0034 #define S3C2410_LCDCON1_STN2GREY   (1<<1)
0035 #define S3C2410_LCDCON1_STN4GREY   (2<<1)
0036 #define S3C2410_LCDCON1_STN8BPP    (3<<1)
0037 #define S3C2410_LCDCON1_STN12BPP   (4<<1)
0038
0039 #define S3C2410_LCDCON1_ENVID      (1)
0040
0041 #define S3C2410_LCDCON1_MODEMASK    0x1E
0042
0043 #define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
0044 #define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
0045 #define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
0046 #define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
0047
0048 #define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
0049 #define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >>  6) & 0xFF)
0050 #define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >>  0) & 0x3F)
0051
0052 #define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
0053 #define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
0054 #define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
0055 #define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
0056 #define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
0057
0058 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
0059 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
0060
0061 /* LDCCON4 changes for STN mode on the S3C2412 */
0062
0063 #define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
0064 #define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
0065 #define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
0066
0067 #define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >>  0) & 0xFF)
0068
0069 /* framebuffer start addressed */
0070 #define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
0071 #define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
0072 #define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
0073
0074 #define S3C2410_LCDBANK(x)  ((x) << 21)
0075 #define S3C2410_LCDBASEU(x) (x)
0076
0077 #define S3C2410_OFFSIZE(x)  ((x) << 11)
0078 #define S3C2410_PAGEWIDTH(x)    (x)
0079
0080 /* colour lookup and miscellaneous controls */
0081
0082 #define S3C2410_REDLUT     S3C2410_LCDREG(0x20)
0083 #define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
0084 #define S3C2410_BLUELUT    S3C2410_LCDREG(0x28)
0085
0086 #define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
0087 #define S3C2410_TPAL       S3C2410_LCDREG(0x50)
0088
0089 #define S3C2410_TPAL_EN     (1<<24)
0090
0091 /* interrupt info */
0092 #define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
0093 #define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
0094 #define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
0095 #define S3C2410_LCDINT_FIWSEL   (1<<2)
0096 #define S3C2410_LCDINT_FRSYNC   (1<<1)
0097 #define S3C2410_LCDINT_FICNT    (1<<0)
0098
0099 /* s3c2442 extra stn registers */
0100
0101 #define S3C2442_REDLUT      S3C2410_LCDREG(0x20)
0102 #define S3C2442_GREENLUT    S3C2410_LCDREG(0x24)
0103 #define S3C2442_BLUELUT     S3C2410_LCDREG(0x28)
0104 #define S3C2442_DITHMODE    S3C2410_LCDREG(0x20)
0105
0106 #define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
0107
0108 #define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
0109
0110 /* S3C2412 registers */
0111
0112 #define S3C2412_TPAL        S3C2410_LCDREG(0x20)
0113
0114 #define S3C2412_LCDINTPND   S3C2410_LCDREG(0x24)
0115 #define S3C2412_LCDSRCPND   S3C2410_LCDREG(0x28)
0116 #define S3C2412_LCDINTMSK   S3C2410_LCDREG(0x2C)
0117
0118 #define S3C2412_TCONSEL     S3C2410_LCDREG(0x30)
0119
0120 #define S3C2412_LCDCON6     S3C2410_LCDREG(0x34)
0121 #define S3C2412_LCDCON7     S3C2410_LCDREG(0x38)
0122 #define S3C2412_LCDCON8     S3C2410_LCDREG(0x3C)
0123 #define S3C2412_LCDCON9     S3C2410_LCDREG(0x40)
0124
0125 #define S3C2412_REDLUT(x)   S3C2410_LCDREG(0x44 + ((x)*4))
0126 #define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
0127 #define S3C2412_BLUELUT(x)  S3C2410_LCDREG(0x98 + ((x)*4))
0128
0129 #define S3C2412_FRCPAT(x)   S3C2410_LCDREG(0xB4 + ((x)*4))
0130
0131 /* general registers */
0132
0133 /* base of the LCD registers, where INTPND, INTSRC and then INTMSK
0134  * are available. */
0135
0136 #define S3C2410_LCDINTBASE  S3C2410_LCDREG(0x54)
0137 #define S3C2412_LCDINTBASE  S3C2410_LCDREG(0x24)
0138
0139 #define S3C24XX_LCDINTPND   (0x00)
0140 #define S3C24XX_LCDSRCPND   (0x04)
0141 #define S3C24XX_LCDINTMSK   (0x08)
0142
0143 #endif /* ___ASM_ARCH_REGS_LCD_H */