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0001 /* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
0002 /*
0003  * Copyright 1996-1997  David J. McKay
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice shall be included in
0013  * all copies or substantial portions of the Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0019  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
0020  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0021  * SOFTWARE.
0022  */
0023 
0024 /*
0025  * GPL licensing note -- nVidia is allowing a liberal interpretation of
0026  * the documentation restriction above, to merely say that this nVidia's
0027  * copyright and disclaimer should be included with all code derived
0028  * from this source.  -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 
0029  */
0030 
0031 /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
0032    <jpaana@s2.org> */
0033 
0034 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
0035 5 20:47:06 mvojkovi Exp $ */
0036 
0037 #include <linux/delay.h>
0038 #include <linux/pci.h>
0039 #include <linux/pci_ids.h>
0040 #include "nv_type.h"
0041 #include "rivafb.h"
0042 #include "nvreg.h"
0043 
0044 #define PFX "rivafb: "
0045 
0046 static inline unsigned char MISCin(struct riva_par *par)
0047 {
0048     return (VGA_RD08(par->riva.PVIO, 0x3cc));
0049 }
0050 
0051 static Bool 
0052 riva_is_connected(struct riva_par *par, Bool second)
0053 {
0054     volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0;
0055     U032 reg52C, reg608;
0056     Bool present;
0057 
0058     if(second) PRAMDAC += 0x800;
0059 
0060     reg52C = NV_RD32(PRAMDAC, 0x052C);
0061     reg608 = NV_RD32(PRAMDAC, 0x0608);
0062 
0063     NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
0064 
0065     NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
0066     mdelay(1); 
0067     NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
0068 
0069     NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140);
0070     NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000);
0071 
0072     mdelay(1);
0073 
0074     present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
0075 
0076     NV_WR32(par->riva.PRAMDAC0, 0x0608,
0077         NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
0078 
0079     NV_WR32(PRAMDAC, 0x052C, reg52C);
0080     NV_WR32(PRAMDAC, 0x0608, reg608);
0081 
0082     return present;
0083 }
0084 
0085 static void
0086 riva_override_CRTC(struct riva_par *par)
0087 {
0088     printk(KERN_INFO PFX
0089         "Detected CRTC controller %i being used\n",
0090         par->SecondCRTC ? 1 : 0);
0091 
0092     if(par->forceCRTC != -1) {
0093         printk(KERN_INFO PFX
0094             "Forcing usage of CRTC %i\n", par->forceCRTC);
0095         par->SecondCRTC = par->forceCRTC;
0096     }
0097 }
0098 
0099 static void
0100 riva_is_second(struct riva_par *par)
0101 {
0102     if (par->FlatPanel == 1) {
0103         switch(par->Chipset & 0xffff) {
0104         case 0x0174:
0105         case 0x0175:
0106         case 0x0176:
0107         case 0x0177:
0108         case 0x0179:
0109         case 0x017C:
0110         case 0x017D:
0111         case 0x0186:
0112         case 0x0187:
0113         /* this might not be a good default for the chips below */
0114         case 0x0286:
0115         case 0x028C:
0116         case 0x0316:
0117         case 0x0317:
0118         case 0x031A:
0119         case 0x031B:
0120         case 0x031C:
0121         case 0x031D:
0122         case 0x031E:
0123         case 0x031F:
0124         case 0x0324:
0125         case 0x0325:
0126         case 0x0328:
0127         case 0x0329:
0128         case 0x032C:
0129         case 0x032D:
0130             par->SecondCRTC = TRUE;
0131             break;
0132         default:
0133             par->SecondCRTC = FALSE;
0134             break;
0135         }
0136     } else {
0137         if(riva_is_connected(par, 0)) {
0138 
0139             if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
0140                 par->SecondCRTC = TRUE;
0141             else
0142                 par->SecondCRTC = FALSE;
0143         } else 
0144         if (riva_is_connected(par, 1)) {
0145             if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
0146                 par->SecondCRTC = TRUE;
0147             else
0148                 par->SecondCRTC = FALSE;
0149         } else /* default */
0150             par->SecondCRTC = FALSE;
0151     }
0152     riva_override_CRTC(par);
0153 }
0154 
0155 unsigned long riva_get_memlen(struct riva_par *par)
0156 {
0157     RIVA_HW_INST *chip = &par->riva;
0158     unsigned long memlen = 0;
0159     unsigned int chipset = par->Chipset;
0160     struct pci_dev* dev;
0161     u32 amt;
0162     int domain = pci_domain_nr(par->pdev->bus);
0163 
0164     switch (chip->Architecture) {
0165     case NV_ARCH_03:
0166         if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
0167             if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
0168                 && ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
0169                 /*
0170                  * SDRAM 128 ZX.
0171                  */
0172                 switch (NV_RD32(chip->PFB,0x00000000) & 0x03) {
0173                 case 2:
0174                     memlen = 1024 * 4;
0175                     break;
0176                 case 1:
0177                     memlen = 1024 * 2;
0178                     break;
0179                 default:
0180                     memlen = 1024 * 8;
0181                     break;
0182                 }
0183             } else {
0184                 memlen = 1024 * 8;
0185             }            
0186         } else  {
0187             /*
0188              * SGRAM 128.
0189              */
0190             switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
0191             case 0:
0192                 memlen = 1024 * 8;
0193                 break;
0194             case 2:
0195                 memlen = 1024 * 4;
0196                 break;
0197             default:
0198                 memlen = 1024 * 2;
0199                 break;
0200             }
0201         }        
0202         break;
0203     case NV_ARCH_04:
0204         if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) {
0205             memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) *
0206                 1024 * 2 + 1024 * 2;
0207         } else {
0208             switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
0209             case 0:
0210                 memlen = 1024 * 32;
0211                 break;
0212             case 1:
0213                 memlen = 1024 * 4;
0214                 break;
0215             case 2:
0216                 memlen = 1024 * 8;
0217                 break;
0218             case 3:
0219             default:
0220                 memlen = 1024 * 16;
0221                 break;
0222             }
0223         }
0224         break;
0225     case NV_ARCH_10:
0226     case NV_ARCH_20:
0227     case NV_ARCH_30:
0228         if(chipset == NV_CHIP_IGEFORCE2) {
0229 
0230             dev = pci_get_domain_bus_and_slot(domain, 0, 1);
0231             pci_read_config_dword(dev, 0x7C, &amt);
0232             pci_dev_put(dev);
0233             memlen = (((amt >> 6) & 31) + 1) * 1024;
0234         } else if (chipset == NV_CHIP_0x01F0) {
0235             dev = pci_get_domain_bus_and_slot(domain, 0, 1);
0236             pci_read_config_dword(dev, 0x84, &amt);
0237             pci_dev_put(dev);
0238             memlen = (((amt >> 4) & 127) + 1) * 1024;
0239         } else {
0240             switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
0241                 0x000000FF){
0242             case 0x02:
0243                 memlen = 1024 * 2;
0244                 break;
0245             case 0x04:
0246                 memlen = 1024 * 4;
0247                 break;
0248             case 0x08:
0249                 memlen = 1024 * 8;
0250                 break;
0251             case 0x10:
0252                 memlen = 1024 * 16;
0253                 break;
0254             case 0x20:
0255                 memlen = 1024 * 32;
0256                 break;
0257             case 0x40:
0258                 memlen = 1024 * 64;
0259                 break;
0260             case 0x80:
0261                 memlen = 1024 * 128;
0262                 break;
0263             default:
0264                 memlen = 1024 * 16;
0265                 break;
0266             }
0267         }
0268         break;
0269     }
0270     return memlen;
0271 }
0272 
0273 unsigned long riva_get_maxdclk(struct riva_par *par)
0274 {
0275     RIVA_HW_INST *chip = &par->riva;
0276     unsigned long dclk = 0;
0277 
0278     switch (chip->Architecture) {
0279     case NV_ARCH_03:
0280         if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
0281             if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
0282                 && ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) {
0283                 /*
0284                  * SDRAM 128 ZX.
0285                  */
0286                 dclk = 800000;
0287             } else {
0288                 dclk = 1000000;
0289             }            
0290         } else {
0291             /*
0292              * SGRAM 128.
0293              */
0294             dclk = 1000000;
0295         } 
0296         break;
0297     case NV_ARCH_04:
0298     case NV_ARCH_10:
0299     case NV_ARCH_20:
0300     case NV_ARCH_30:
0301         switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) {
0302         case 3:
0303             dclk = 800000;
0304             break;
0305         default:
0306             dclk = 1000000;
0307             break;
0308         }
0309         break;
0310     }
0311     return dclk;
0312 }
0313 
0314 void
0315 riva_common_setup(struct riva_par *par)
0316 {
0317     par->riva.EnableIRQ = 0;
0318     par->riva.PRAMDAC0 =
0319         (volatile U032 __iomem *)(par->ctrl_base + 0x00680000);
0320     par->riva.PFB =
0321         (volatile U032 __iomem *)(par->ctrl_base + 0x00100000);
0322     par->riva.PFIFO =
0323         (volatile U032 __iomem *)(par->ctrl_base + 0x00002000);
0324     par->riva.PGRAPH =
0325         (volatile U032 __iomem *)(par->ctrl_base + 0x00400000);
0326     par->riva.PEXTDEV =
0327         (volatile U032 __iomem *)(par->ctrl_base + 0x00101000);
0328     par->riva.PTIMER =
0329         (volatile U032 __iomem *)(par->ctrl_base + 0x00009000);
0330     par->riva.PMC =
0331         (volatile U032 __iomem *)(par->ctrl_base + 0x00000000);
0332     par->riva.FIFO =
0333         (volatile U032 __iomem *)(par->ctrl_base + 0x00800000);
0334     par->riva.PCIO0 = par->ctrl_base + 0x00601000;
0335     par->riva.PDIO0 = par->ctrl_base + 0x00681000;
0336     par->riva.PVIO = par->ctrl_base + 0x000C0000;
0337 
0338     par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
0339     
0340     if (par->FlatPanel == -1) {
0341         switch (par->Chipset & 0xffff) {
0342         case 0x0112:   /* known laptop chips */
0343         case 0x0174:
0344         case 0x0175:
0345         case 0x0176:
0346         case 0x0177:
0347         case 0x0179:
0348         case 0x017C:
0349         case 0x017D:
0350         case 0x0186:
0351         case 0x0187:
0352         case 0x0286:
0353         case 0x028C:
0354         case 0x0316:
0355         case 0x0317:
0356         case 0x031A:
0357         case 0x031B:
0358         case 0x031C:
0359         case 0x031D:
0360         case 0x031E:
0361         case 0x031F:
0362         case 0x0324:
0363         case 0x0325:
0364         case 0x0328:
0365         case 0x0329:
0366         case 0x032C:
0367         case 0x032D:
0368             printk(KERN_INFO PFX 
0369                 "On a laptop.  Assuming Digital Flat Panel\n");
0370             par->FlatPanel = 1;
0371             break;
0372         default:
0373             break;
0374         }
0375     }
0376     
0377     switch (par->Chipset & 0x0ff0) {
0378     case 0x0110:
0379         if (par->Chipset == NV_CHIP_GEFORCE2_GO)
0380             par->SecondCRTC = TRUE; 
0381 #if defined(__powerpc__)
0382         if (par->FlatPanel == 1)
0383             par->SecondCRTC = TRUE;
0384 #endif
0385         riva_override_CRTC(par);
0386         break;
0387     case 0x0170:
0388     case 0x0180:
0389     case 0x01F0:
0390     case 0x0250:
0391     case 0x0280:
0392     case 0x0300:
0393     case 0x0310:
0394     case 0x0320:
0395     case 0x0330:
0396     case 0x0340:
0397         riva_is_second(par);
0398         break;
0399     default:
0400         break;
0401     }
0402 
0403     if (par->SecondCRTC) {
0404         par->riva.PCIO = par->riva.PCIO0 + 0x2000;
0405         par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
0406         par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
0407         par->riva.PDIO = par->riva.PDIO0 + 0x2000;
0408     } else {
0409         par->riva.PCIO = par->riva.PCIO0;
0410         par->riva.PCRTC = par->riva.PCRTC0;
0411         par->riva.PRAMDAC = par->riva.PRAMDAC0;
0412         par->riva.PDIO = par->riva.PDIO0;
0413     }
0414 
0415     if (par->FlatPanel == -1) {
0416         /* Fix me, need x86 DDC code */
0417         par->FlatPanel = 0;
0418     }
0419     par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
0420 
0421     RivaGetConfig(&par->riva, par->pdev, par->Chipset);
0422 }
0423
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