video/fbdev/pxafb.h

0001 #ifndef __PXAFB_H__
0002 #define __PXAFB_H__
0003
0004 /*
0005  * linux/drivers/video/pxafb.h
0006  *    -- Intel PXA250/210 LCD Controller Frame Buffer Device
0007  *
0008  *  Copyright (C) 1999 Eric A. Thomas.
0009  *  Copyright (C) 2004 Jean-Frederic Clere.
0010  *  Copyright (C) 2004 Ian Campbell.
0011  *  Copyright (C) 2004 Jeff Lackey.
0012  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
0013  *  which in turn is
0014  *   Based on acornfb.c Copyright (C) Russell King.
0015  *
0016  *  2001-08-03: Cliff Brake <cbrake@acclent.com>
0017  *   - ported SA1100 code to PXA
0018  *
0019  * This file is subject to the terms and conditions of the GNU General Public
0020  * License.  See the file COPYING in the main directory of this archive
0021  * for more details.
0022  */
0023
0024 /* PXA LCD DMA descriptor */
0025 struct pxafb_dma_descriptor {
0026     unsigned int fdadr;
0027     unsigned int fsadr;
0028     unsigned int fidr;
0029     unsigned int ldcmd;
0030 };
0031
0032 enum {
0033     PAL_NONE    = -1,
0034     PAL_BASE    = 0,
0035     PAL_OV1     = 1,
0036     PAL_OV2     = 2,
0037     PAL_MAX,
0038 };
0039
0040 enum {
0041     DMA_BASE    = 0,
0042     DMA_UPPER   = 0,
0043     DMA_LOWER   = 1,
0044     DMA_OV1     = 1,
0045     DMA_OV2_Y   = 2,
0046     DMA_OV2_Cb  = 3,
0047     DMA_OV2_Cr  = 4,
0048     DMA_CURSOR  = 5,
0049     DMA_CMD     = 6,
0050     DMA_MAX,
0051 };
0052
0053 /* maximum palette size - 256 entries, each 4 bytes long */
0054 #define PALETTE_SIZE    (256 * 4)
0055 #define CMD_BUFF_SIZE   (1024 * 50)
0056
0057 /* NOTE: the palette and frame dma descriptors are doubled to allow
0058  * the 2nd set for branch settings (FBRx)
0059  */
0060 struct pxafb_dma_buff {
0061     unsigned char palette[PAL_MAX * PALETTE_SIZE];
0062     uint16_t cmd_buff[CMD_BUFF_SIZE];
0063     struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
0064     struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
0065 };
0066
0067 enum {
0068     OVERLAY1,
0069     OVERLAY2,
0070 };
0071
0072 enum {
0073     OVERLAY_FORMAT_RGB = 0,
0074     OVERLAY_FORMAT_YUV444_PACKED,
0075     OVERLAY_FORMAT_YUV444_PLANAR,
0076     OVERLAY_FORMAT_YUV422_PLANAR,
0077     OVERLAY_FORMAT_YUV420_PLANAR,
0078 };
0079
0080 #define NONSTD_TO_XPOS(x)   (((x) >> 0)  & 0x3ff)
0081 #define NONSTD_TO_YPOS(x)   (((x) >> 10) & 0x3ff)
0082 #define NONSTD_TO_PFOR(x)   (((x) >> 20) & 0x7)
0083
0084 struct pxafb_layer;
0085
0086 struct pxafb_layer_ops {
0087     void (*enable)(struct pxafb_layer *);
0088     void (*disable)(struct pxafb_layer *);
0089     void (*setup)(struct pxafb_layer *);
0090 };
0091
0092 struct pxafb_layer {
0093     struct fb_info      fb;
0094     int         id;
0095     int         registered;
0096     uint32_t        usage;
0097     uint32_t        control[2];
0098
0099     struct pxafb_layer_ops  *ops;
0100
0101     void __iomem        *video_mem;
0102     unsigned long       video_mem_phys;
0103     size_t          video_mem_size;
0104     struct completion   branch_done;
0105
0106     struct pxafb_info   *fbi;
0107 };
0108
0109 struct pxafb_info {
0110     struct fb_info      fb;
0111     struct device       *dev;
0112     struct clk      *clk;
0113
0114     void __iomem        *mmio_base;
0115
0116     struct pxafb_dma_buff   *dma_buff;
0117     size_t          dma_buff_size;
0118     dma_addr_t      dma_buff_phys;
0119     dma_addr_t      fdadr[DMA_MAX * 2];
0120
0121     void __iomem        *video_mem; /* virtual address of frame buffer */
0122     unsigned long       video_mem_phys; /* physical address of frame buffer */
0123     size_t          video_mem_size; /* size of the frame buffer */
0124     u16 *           palette_cpu;    /* virtual address of palette memory */
0125     u_int           palette_size;
0126
0127     u_int           lccr0;
0128     u_int           lccr3;
0129     u_int           lccr4;
0130     u_int           cmap_inverse:1,
0131                 cmap_static:1,
0132                 unused:30;
0133
0134     u_int           reg_lccr0;
0135     u_int           reg_lccr1;
0136     u_int           reg_lccr2;
0137     u_int           reg_lccr3;
0138     u_int           reg_lccr4;
0139     u_int           reg_cmdcr;
0140
0141     unsigned long   hsync_time;
0142
0143     volatile u_char     state;
0144     volatile u_char     task_state;
0145     struct mutex        ctrlr_lock;
0146     wait_queue_head_t   ctrlr_wait;
0147     struct work_struct  task;
0148
0149     struct completion   disable_done;
0150
0151 #ifdef CONFIG_FB_PXA_SMARTPANEL
0152     uint16_t        *smart_cmds;
0153     size_t          n_smart_cmds;
0154     struct completion   command_done;
0155     struct completion   refresh_done;
0156     struct task_struct  *smart_thread;
0157 #endif
0158
0159 #ifdef CONFIG_FB_PXA_OVERLAY
0160     struct pxafb_layer  overlay[2];
0161 #endif
0162
0163 #ifdef CONFIG_CPU_FREQ
0164     struct notifier_block   freq_transition;
0165 #endif
0166
0167     struct regulator *lcd_supply;
0168     bool lcd_supply_enabled;
0169
0170     void (*lcd_power)(int, struct fb_var_screeninfo *);
0171     void (*backlight_power)(int);
0172
0173     struct pxafb_mach_info  *inf;
0174 };
0175
0176 #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
0177
0178 /*
0179  * These are the actions for set_ctrlr_state
0180  */
0181 #define C_DISABLE       (0)
0182 #define C_ENABLE        (1)
0183 #define C_DISABLE_CLKCHANGE (2)
0184 #define C_ENABLE_CLKCHANGE  (3)
0185 #define C_REENABLE      (4)
0186 #define C_DISABLE_PM        (5)
0187 #define C_ENABLE_PM     (6)
0188 #define C_STARTUP       (7)
0189
0190 #define PXA_NAME    "PXA"
0191
0192 /*
0193  * Minimum X and Y resolutions
0194  */
0195 #define MIN_XRES    64
0196 #define MIN_YRES    64
0197
0198 /* maximum X and Y resolutions - note these are limits from the register
0199  * bits length instead of the real ones
0200  */
0201 #define MAX_XRES    1024
0202 #define MAX_YRES    1024
0203
0204 #endif /* __PXAFB_H__ */