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0001 /*
0002  *  linux/drivers/video/pxafb.c
0003  *
0004  *  Copyright (C) 1999 Eric A. Thomas.
0005  *  Copyright (C) 2004 Jean-Frederic Clere.
0006  *  Copyright (C) 2004 Ian Campbell.
0007  *  Copyright (C) 2004 Jeff Lackey.
0008  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
0009  *  which in turn is
0010  *   Based on acornfb.c Copyright (C) Russell King.
0011  *
0012  * This file is subject to the terms and conditions of the GNU General Public
0013  * License.  See the file COPYING in the main directory of this archive for
0014  * more details.
0015  *
0016  *          Intel PXA250/210 LCD Controller Frame Buffer Driver
0017  *
0018  * Please direct your questions and comments on this driver to the following
0019  * email address:
0020  *
0021  *  linux-arm-kernel@lists.arm.linux.org.uk
0022  *
0023  * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
0024  *
0025  *   Copyright (C) 2004, Intel Corporation
0026  *
0027  *     2003/08/27: <yu.tang@intel.com>
0028  *     2004/03/10: <stanley.cai@intel.com>
0029  *     2004/10/28: <yan.yin@intel.com>
0030  *
0031  *   Copyright (C) 2006-2008 Marvell International Ltd.
0032  *   All Rights Reserved
0033  */
0034 
0035 #include <linux/module.h>
0036 #include <linux/moduleparam.h>
0037 #include <linux/kernel.h>
0038 #include <linux/sched.h>
0039 #include <linux/errno.h>
0040 #include <linux/string.h>
0041 #include <linux/interrupt.h>
0042 #include <linux/slab.h>
0043 #include <linux/mm.h>
0044 #include <linux/fb.h>
0045 #include <linux/delay.h>
0046 #include <linux/init.h>
0047 #include <linux/ioport.h>
0048 #include <linux/cpufreq.h>
0049 #include <linux/platform_device.h>
0050 #include <linux/dma-mapping.h>
0051 #include <linux/clk.h>
0052 #include <linux/err.h>
0053 #include <linux/completion.h>
0054 #include <linux/mutex.h>
0055 #include <linux/kthread.h>
0056 #include <linux/freezer.h>
0057 #include <linux/console.h>
0058 #include <linux/of_graph.h>
0059 #include <linux/regulator/consumer.h>
0060 #include <linux/soc/pxa/cpu.h>
0061 #include <video/of_display_timing.h>
0062 #include <video/videomode.h>
0063 
0064 #include <asm/io.h>
0065 #include <asm/irq.h>
0066 #include <asm/div64.h>
0067 #include <linux/platform_data/video-pxafb.h>
0068 
0069 /*
0070  * Complain if VAR is out of range.
0071  */
0072 #define DEBUG_VAR 1
0073 
0074 #include "pxafb.h"
0075 #include "pxa3xx-regs.h"
0076 
0077 /* Bits which should not be set in machine configuration structures */
0078 #define LCCR0_INVALID_CONFIG_MASK   (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
0079                      LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
0080                      LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
0081 
0082 #define LCCR3_INVALID_CONFIG_MASK   (LCCR3_HSP | LCCR3_VSP |\
0083                      LCCR3_PCD | LCCR3_BPP(0xf))
0084 
0085 static int pxafb_activate_var(struct fb_var_screeninfo *var,
0086                 struct pxafb_info *);
0087 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
0088 static void setup_base_frame(struct pxafb_info *fbi,
0089                              struct fb_var_screeninfo *var, int branch);
0090 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
0091                unsigned long offset, size_t size);
0092 
0093 static unsigned long video_mem_size = 0;
0094 
0095 static inline unsigned long
0096 lcd_readl(struct pxafb_info *fbi, unsigned int off)
0097 {
0098     return __raw_readl(fbi->mmio_base + off);
0099 }
0100 
0101 static inline void
0102 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
0103 {
0104     __raw_writel(val, fbi->mmio_base + off);
0105 }
0106 
0107 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
0108 {
0109     unsigned long flags;
0110 
0111     local_irq_save(flags);
0112     /*
0113      * We need to handle two requests being made at the same time.
0114      * There are two important cases:
0115      *  1. When we are changing VT (C_REENABLE) while unblanking
0116      *     (C_ENABLE) We must perform the unblanking, which will
0117      *     do our REENABLE for us.
0118      *  2. When we are blanking, but immediately unblank before
0119      *     we have blanked.  We do the "REENABLE" thing here as
0120      *     well, just to be sure.
0121      */
0122     if (fbi->task_state == C_ENABLE && state == C_REENABLE)
0123         state = (u_int) -1;
0124     if (fbi->task_state == C_DISABLE && state == C_ENABLE)
0125         state = C_REENABLE;
0126 
0127     if (state != (u_int)-1) {
0128         fbi->task_state = state;
0129         schedule_work(&fbi->task);
0130     }
0131     local_irq_restore(flags);
0132 }
0133 
0134 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
0135 {
0136     chan &= 0xffff;
0137     chan >>= 16 - bf->length;
0138     return chan << bf->offset;
0139 }
0140 
0141 static int
0142 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
0143                u_int trans, struct fb_info *info)
0144 {
0145     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
0146     u_int val;
0147 
0148     if (regno >= fbi->palette_size)
0149         return 1;
0150 
0151     if (fbi->fb.var.grayscale) {
0152         fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
0153         return 0;
0154     }
0155 
0156     switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
0157     case LCCR4_PAL_FOR_0:
0158         val  = ((red   >>  0) & 0xf800);
0159         val |= ((green >>  5) & 0x07e0);
0160         val |= ((blue  >> 11) & 0x001f);
0161         fbi->palette_cpu[regno] = val;
0162         break;
0163     case LCCR4_PAL_FOR_1:
0164         val  = ((red   << 8) & 0x00f80000);
0165         val |= ((green >> 0) & 0x0000fc00);
0166         val |= ((blue  >> 8) & 0x000000f8);
0167         ((u32 *)(fbi->palette_cpu))[regno] = val;
0168         break;
0169     case LCCR4_PAL_FOR_2:
0170         val  = ((red   << 8) & 0x00fc0000);
0171         val |= ((green >> 0) & 0x0000fc00);
0172         val |= ((blue  >> 8) & 0x000000fc);
0173         ((u32 *)(fbi->palette_cpu))[regno] = val;
0174         break;
0175     case LCCR4_PAL_FOR_3:
0176         val  = ((red   << 8) & 0x00ff0000);
0177         val |= ((green >> 0) & 0x0000ff00);
0178         val |= ((blue  >> 8) & 0x000000ff);
0179         ((u32 *)(fbi->palette_cpu))[regno] = val;
0180         break;
0181     }
0182 
0183     return 0;
0184 }
0185 
0186 static int
0187 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
0188            u_int trans, struct fb_info *info)
0189 {
0190     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
0191     unsigned int val;
0192     int ret = 1;
0193 
0194     /*
0195      * If inverse mode was selected, invert all the colours
0196      * rather than the register number.  The register number
0197      * is what you poke into the framebuffer to produce the
0198      * colour you requested.
0199      */
0200     if (fbi->cmap_inverse) {
0201         red   = 0xffff - red;
0202         green = 0xffff - green;
0203         blue  = 0xffff - blue;
0204     }
0205 
0206     /*
0207      * If greyscale is true, then we convert the RGB value
0208      * to greyscale no matter what visual we are using.
0209      */
0210     if (fbi->fb.var.grayscale)
0211         red = green = blue = (19595 * red + 38470 * green +
0212                     7471 * blue) >> 16;
0213 
0214     switch (fbi->fb.fix.visual) {
0215     case FB_VISUAL_TRUECOLOR:
0216         /*
0217          * 16-bit True Colour.  We encode the RGB value
0218          * according to the RGB bitfield information.
0219          */
0220         if (regno < 16) {
0221             u32 *pal = fbi->fb.pseudo_palette;
0222 
0223             val  = chan_to_field(red, &fbi->fb.var.red);
0224             val |= chan_to_field(green, &fbi->fb.var.green);
0225             val |= chan_to_field(blue, &fbi->fb.var.blue);
0226 
0227             pal[regno] = val;
0228             ret = 0;
0229         }
0230         break;
0231 
0232     case FB_VISUAL_STATIC_PSEUDOCOLOR:
0233     case FB_VISUAL_PSEUDOCOLOR:
0234         ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
0235         break;
0236     }
0237 
0238     return ret;
0239 }
0240 
0241 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
0242 static inline int var_to_depth(struct fb_var_screeninfo *var)
0243 {
0244     return var->red.length + var->green.length +
0245         var->blue.length + var->transp.length;
0246 }
0247 
0248 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
0249 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
0250 {
0251     int bpp = -EINVAL;
0252 
0253     switch (var->bits_per_pixel) {
0254     case 1:  bpp = 0; break;
0255     case 2:  bpp = 1; break;
0256     case 4:  bpp = 2; break;
0257     case 8:  bpp = 3; break;
0258     case 16: bpp = 4; break;
0259     case 24:
0260         switch (var_to_depth(var)) {
0261         case 18: bpp = 6; break; /* 18-bits/pixel packed */
0262         case 19: bpp = 8; break; /* 19-bits/pixel packed */
0263         case 24: bpp = 9; break;
0264         }
0265         break;
0266     case 32:
0267         switch (var_to_depth(var)) {
0268         case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
0269         case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
0270         case 25: bpp = 10; break;
0271         }
0272         break;
0273     }
0274     return bpp;
0275 }
0276 
0277 /*
0278  *  pxafb_var_to_lccr3():
0279  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
0280  *
0281  *  NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
0282  *  implication of the acutal use of transparency bit,  which we handle it
0283  *  here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
0284  *  Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
0285  *
0286  *  Transparency for palette pixel formats is not supported at the moment.
0287  */
0288 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
0289 {
0290     int bpp = pxafb_var_to_bpp(var);
0291     uint32_t lccr3;
0292 
0293     if (bpp < 0)
0294         return 0;
0295 
0296     lccr3 = LCCR3_BPP(bpp);
0297 
0298     switch (var_to_depth(var)) {
0299     case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
0300     case 18: lccr3 |= LCCR3_PDFOR_3; break;
0301     case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
0302          break;
0303     case 19:
0304     case 25: lccr3 |= LCCR3_PDFOR_0; break;
0305     }
0306     return lccr3;
0307 }
0308 
0309 #define SET_PIXFMT(v, r, g, b, t)               \
0310 ({                              \
0311     (v)->transp.offset = (t) ? (r) + (g) + (b) : 0;     \
0312     (v)->transp.length = (t) ? (t) : 0;         \
0313     (v)->blue.length   = (b); (v)->blue.offset = 0;     \
0314     (v)->green.length  = (g); (v)->green.offset = (b);  \
0315     (v)->red.length    = (r); (v)->red.offset = (b) + (g);  \
0316 })
0317 
0318 /* set the RGBT bitfields of fb_var_screeninf according to
0319  * var->bits_per_pixel and given depth
0320  */
0321 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
0322 {
0323     if (depth == 0)
0324         depth = var->bits_per_pixel;
0325 
0326     if (var->bits_per_pixel < 16) {
0327         /* indexed pixel formats */
0328         var->red.offset    = 0; var->red.length    = 8;
0329         var->green.offset  = 0; var->green.length  = 8;
0330         var->blue.offset   = 0; var->blue.length   = 8;
0331         var->transp.offset = 0; var->transp.length = 8;
0332     }
0333 
0334     switch (depth) {
0335     case 16: var->transp.length ?
0336          SET_PIXFMT(var, 5, 5, 5, 1) :      /* RGBT555 */
0337          SET_PIXFMT(var, 5, 6, 5, 0); break;    /* RGB565 */
0338     case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;    /* RGB666 */
0339     case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;    /* RGBT666 */
0340     case 24: var->transp.length ?
0341          SET_PIXFMT(var, 8, 8, 7, 1) :      /* RGBT887 */
0342          SET_PIXFMT(var, 8, 8, 8, 0); break;    /* RGB888 */
0343     case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;    /* RGBT888 */
0344     }
0345 }
0346 
0347 #ifdef CONFIG_CPU_FREQ
0348 /*
0349  *  pxafb_display_dma_period()
0350  *    Calculate the minimum period (in picoseconds) between two DMA
0351  *    requests for the LCD controller.  If we hit this, it means we're
0352  *    doing nothing but LCD DMA.
0353  */
0354 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
0355 {
0356     /*
0357      * Period = pixclock * bits_per_byte * bytes_per_transfer
0358      *              / memory_bits_per_pixel;
0359      */
0360     return var->pixclock * 8 * 16 / var->bits_per_pixel;
0361 }
0362 #endif
0363 
0364 /*
0365  * Select the smallest mode that allows the desired resolution to be
0366  * displayed. If desired parameters can be rounded up.
0367  */
0368 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
0369                          struct fb_var_screeninfo *var)
0370 {
0371     struct pxafb_mode_info *mode = NULL;
0372     struct pxafb_mode_info *modelist = mach->modes;
0373     unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
0374     unsigned int i;
0375 
0376     for (i = 0; i < mach->num_modes; i++) {
0377         if (modelist[i].xres >= var->xres &&
0378             modelist[i].yres >= var->yres &&
0379             modelist[i].xres < best_x &&
0380             modelist[i].yres < best_y &&
0381             modelist[i].bpp >= var->bits_per_pixel) {
0382             best_x = modelist[i].xres;
0383             best_y = modelist[i].yres;
0384             mode = &modelist[i];
0385         }
0386     }
0387 
0388     return mode;
0389 }
0390 
0391 static void pxafb_setmode(struct fb_var_screeninfo *var,
0392               struct pxafb_mode_info *mode)
0393 {
0394     var->xres       = mode->xres;
0395     var->yres       = mode->yres;
0396     var->bits_per_pixel = mode->bpp;
0397     var->pixclock       = mode->pixclock;
0398     var->hsync_len      = mode->hsync_len;
0399     var->left_margin    = mode->left_margin;
0400     var->right_margin   = mode->right_margin;
0401     var->vsync_len      = mode->vsync_len;
0402     var->upper_margin   = mode->upper_margin;
0403     var->lower_margin   = mode->lower_margin;
0404     var->sync       = mode->sync;
0405     var->grayscale      = mode->cmap_greyscale;
0406     var->transp.length  = mode->transparency;
0407 
0408     /* set the initial RGBA bitfields */
0409     pxafb_set_pixfmt(var, mode->depth);
0410 }
0411 
0412 static int pxafb_adjust_timing(struct pxafb_info *fbi,
0413                    struct fb_var_screeninfo *var)
0414 {
0415     int line_length;
0416 
0417     var->xres = max_t(int, var->xres, MIN_XRES);
0418     var->yres = max_t(int, var->yres, MIN_YRES);
0419 
0420     if (!(fbi->lccr0 & LCCR0_LCDT)) {
0421         clamp_val(var->hsync_len, 1, 64);
0422         clamp_val(var->vsync_len, 1, 64);
0423         clamp_val(var->left_margin,  1, 255);
0424         clamp_val(var->right_margin, 1, 255);
0425         clamp_val(var->upper_margin, 1, 255);
0426         clamp_val(var->lower_margin, 1, 255);
0427     }
0428 
0429     /* make sure each line is aligned on word boundary */
0430     line_length = var->xres * var->bits_per_pixel / 8;
0431     line_length = ALIGN(line_length, 4);
0432     var->xres = line_length * 8 / var->bits_per_pixel;
0433 
0434     /* we don't support xpan, force xres_virtual to be equal to xres */
0435     var->xres_virtual = var->xres;
0436 
0437     if (var->accel_flags & FB_ACCELF_TEXT)
0438         var->yres_virtual = fbi->fb.fix.smem_len / line_length;
0439     else
0440         var->yres_virtual = max(var->yres_virtual, var->yres);
0441 
0442     /* check for limits */
0443     if (var->xres > MAX_XRES || var->yres > MAX_YRES)
0444         return -EINVAL;
0445 
0446     if (var->yres > var->yres_virtual)
0447         return -EINVAL;
0448 
0449     return 0;
0450 }
0451 
0452 /*
0453  *  pxafb_check_var():
0454  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
0455  *    if it's too big, return -EINVAL.
0456  *
0457  *    Round up in the following order: bits_per_pixel, xres,
0458  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
0459  *    bitfields, horizontal timing, vertical timing.
0460  */
0461 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
0462 {
0463     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
0464     struct pxafb_mach_info *inf = fbi->inf;
0465     int err;
0466 
0467     if (inf->fixed_modes) {
0468         struct pxafb_mode_info *mode;
0469 
0470         mode = pxafb_getmode(inf, var);
0471         if (!mode)
0472             return -EINVAL;
0473         pxafb_setmode(var, mode);
0474     }
0475 
0476     /* do a test conversion to BPP fields to check the color formats */
0477     err = pxafb_var_to_bpp(var);
0478     if (err < 0)
0479         return err;
0480 
0481     pxafb_set_pixfmt(var, var_to_depth(var));
0482 
0483     err = pxafb_adjust_timing(fbi, var);
0484     if (err)
0485         return err;
0486 
0487 #ifdef CONFIG_CPU_FREQ
0488     pr_debug("pxafb: dma period = %d ps\n",
0489          pxafb_display_dma_period(var));
0490 #endif
0491 
0492     return 0;
0493 }
0494 
0495 /*
0496  * pxafb_set_par():
0497  *  Set the user defined part of the display for the specified console
0498  */
0499 static int pxafb_set_par(struct fb_info *info)
0500 {
0501     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
0502     struct fb_var_screeninfo *var = &info->var;
0503 
0504     if (var->bits_per_pixel >= 16)
0505         fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
0506     else if (!fbi->cmap_static)
0507         fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
0508     else {
0509         /*
0510          * Some people have weird ideas about wanting static
0511          * pseudocolor maps.  I suspect their user space
0512          * applications are broken.
0513          */
0514         fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
0515     }
0516 
0517     fbi->fb.fix.line_length = var->xres_virtual *
0518                   var->bits_per_pixel / 8;
0519     if (var->bits_per_pixel >= 16)
0520         fbi->palette_size = 0;
0521     else
0522         fbi->palette_size = var->bits_per_pixel == 1 ?
0523                     4 : 1 << var->bits_per_pixel;
0524 
0525     fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
0526 
0527     if (fbi->fb.var.bits_per_pixel >= 16)
0528         fb_dealloc_cmap(&fbi->fb.cmap);
0529     else
0530         fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
0531 
0532     pxafb_activate_var(var, fbi);
0533 
0534     return 0;
0535 }
0536 
0537 static int pxafb_pan_display(struct fb_var_screeninfo *var,
0538                  struct fb_info *info)
0539 {
0540     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
0541     struct fb_var_screeninfo newvar;
0542     int dma = DMA_MAX + DMA_BASE;
0543 
0544     if (fbi->state != C_ENABLE)
0545         return 0;
0546 
0547     /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
0548      * was passed in and copy the rest from the old screeninfo.
0549      */
0550     memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
0551     newvar.xoffset = var->xoffset;
0552     newvar.yoffset = var->yoffset;
0553     newvar.vmode &= ~FB_VMODE_YWRAP;
0554     newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
0555 
0556     setup_base_frame(fbi, &newvar, 1);
0557 
0558     if (fbi->lccr0 & LCCR0_SDS)
0559         lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
0560 
0561     lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
0562     return 0;
0563 }
0564 
0565 /*
0566  * pxafb_blank():
0567  *  Blank the display by setting all palette values to zero.  Note, the
0568  *  16 bpp mode does not really use the palette, so this will not
0569  *      blank the display in all modes.
0570  */
0571 static int pxafb_blank(int blank, struct fb_info *info)
0572 {
0573     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
0574     int i;
0575 
0576     switch (blank) {
0577     case FB_BLANK_POWERDOWN:
0578     case FB_BLANK_VSYNC_SUSPEND:
0579     case FB_BLANK_HSYNC_SUSPEND:
0580     case FB_BLANK_NORMAL:
0581         if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
0582             fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
0583             for (i = 0; i < fbi->palette_size; i++)
0584                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
0585 
0586         pxafb_schedule_work(fbi, C_DISABLE);
0587         /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
0588         break;
0589 
0590     case FB_BLANK_UNBLANK:
0591         /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
0592         if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
0593             fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
0594             fb_set_cmap(&fbi->fb.cmap, info);
0595         pxafb_schedule_work(fbi, C_ENABLE);
0596     }
0597     return 0;
0598 }
0599 
0600 static const struct fb_ops pxafb_ops = {
0601     .owner      = THIS_MODULE,
0602     .fb_check_var   = pxafb_check_var,
0603     .fb_set_par = pxafb_set_par,
0604     .fb_pan_display = pxafb_pan_display,
0605     .fb_setcolreg   = pxafb_setcolreg,
0606     .fb_fillrect    = cfb_fillrect,
0607     .fb_copyarea    = cfb_copyarea,
0608     .fb_imageblit   = cfb_imageblit,
0609     .fb_blank   = pxafb_blank,
0610 };
0611 
0612 #ifdef CONFIG_FB_PXA_OVERLAY
0613 static void overlay1fb_setup(struct pxafb_layer *ofb)
0614 {
0615     int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
0616     unsigned long start = ofb->video_mem_phys;
0617     setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
0618 }
0619 
0620 /* Depending on the enable status of overlay1/2, the DMA should be
0621  * updated from FDADRx (when disabled) or FBRx (when enabled).
0622  */
0623 static void overlay1fb_enable(struct pxafb_layer *ofb)
0624 {
0625     int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
0626     uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
0627 
0628     lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
0629     lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
0630     lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
0631 }
0632 
0633 static void overlay1fb_disable(struct pxafb_layer *ofb)
0634 {
0635     uint32_t lccr5;
0636 
0637     if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
0638         return;
0639 
0640     lccr5 = lcd_readl(ofb->fbi, LCCR5);
0641 
0642     lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
0643 
0644     lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
0645     lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
0646     lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
0647 
0648     if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
0649         pr_warn("%s: timeout disabling overlay1\n", __func__);
0650 
0651     lcd_writel(ofb->fbi, LCCR5, lccr5);
0652 }
0653 
0654 static void overlay2fb_setup(struct pxafb_layer *ofb)
0655 {
0656     int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
0657     unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
0658 
0659     if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
0660         size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
0661         setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
0662     } else {
0663         size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
0664         switch (pfor) {
0665         case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
0666         case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
0667         case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
0668         }
0669         start[1] = start[0] + size;
0670         start[2] = start[1] + size / div;
0671         setup_frame_dma(ofb->fbi, DMA_OV2_Y,  -1, start[0], size);
0672         setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
0673         setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
0674     }
0675 }
0676 
0677 static void overlay2fb_enable(struct pxafb_layer *ofb)
0678 {
0679     int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
0680     int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
0681     uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y]  | (enabled ? 0x1 : 0);
0682     uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
0683     uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
0684 
0685     if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
0686         lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
0687     else {
0688         lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
0689         lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
0690         lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
0691     }
0692     lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
0693     lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
0694 }
0695 
0696 static void overlay2fb_disable(struct pxafb_layer *ofb)
0697 {
0698     uint32_t lccr5;
0699 
0700     if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
0701         return;
0702 
0703     lccr5 = lcd_readl(ofb->fbi, LCCR5);
0704 
0705     lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
0706 
0707     lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
0708     lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
0709     lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y]  | 0x3);
0710     lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
0711     lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
0712 
0713     if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
0714         pr_warn("%s: timeout disabling overlay2\n", __func__);
0715 }
0716 
0717 static struct pxafb_layer_ops ofb_ops[] = {
0718     [0] = {
0719         .enable     = overlay1fb_enable,
0720         .disable    = overlay1fb_disable,
0721         .setup      = overlay1fb_setup,
0722     },
0723     [1] = {
0724         .enable     = overlay2fb_enable,
0725         .disable    = overlay2fb_disable,
0726         .setup      = overlay2fb_setup,
0727     },
0728 };
0729 
0730 static int overlayfb_open(struct fb_info *info, int user)
0731 {
0732     struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
0733 
0734     /* no support for framebuffer console on overlay */
0735     if (user == 0)
0736         return -ENODEV;
0737 
0738     if (ofb->usage++ == 0) {
0739         /* unblank the base framebuffer */
0740         console_lock();
0741         fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
0742         console_unlock();
0743     }
0744 
0745     return 0;
0746 }
0747 
0748 static int overlayfb_release(struct fb_info *info, int user)
0749 {
0750     struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
0751 
0752     if (ofb->usage == 1) {
0753         ofb->ops->disable(ofb);
0754         ofb->fb.var.height  = -1;
0755         ofb->fb.var.width   = -1;
0756         ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
0757         ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
0758 
0759         ofb->usage--;
0760     }
0761     return 0;
0762 }
0763 
0764 static int overlayfb_check_var(struct fb_var_screeninfo *var,
0765                    struct fb_info *info)
0766 {
0767     struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
0768     struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
0769     int xpos, ypos, pfor, bpp;
0770 
0771     xpos = NONSTD_TO_XPOS(var->nonstd);
0772     ypos = NONSTD_TO_YPOS(var->nonstd);
0773     pfor = NONSTD_TO_PFOR(var->nonstd);
0774 
0775     bpp = pxafb_var_to_bpp(var);
0776     if (bpp < 0)
0777         return -EINVAL;
0778 
0779     /* no support for YUV format on overlay1 */
0780     if (ofb->id == OVERLAY1 && pfor != 0)
0781         return -EINVAL;
0782 
0783     /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
0784     switch (pfor) {
0785     case OVERLAY_FORMAT_RGB:
0786         bpp = pxafb_var_to_bpp(var);
0787         if (bpp < 0)
0788             return -EINVAL;
0789 
0790         pxafb_set_pixfmt(var, var_to_depth(var));
0791         break;
0792     case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
0793     case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
0794     case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
0795     case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
0796     default:
0797         return -EINVAL;
0798     }
0799 
0800     /* each line must start at a 32-bit word boundary */
0801     if ((xpos * bpp) % 32)
0802         return -EINVAL;
0803 
0804     /* xres must align on 32-bit word boundary */
0805     var->xres = roundup(var->xres * bpp, 32) / bpp;
0806 
0807     if ((xpos + var->xres > base_var->xres) ||
0808         (ypos + var->yres > base_var->yres))
0809         return -EINVAL;
0810 
0811     var->xres_virtual = var->xres;
0812     var->yres_virtual = max(var->yres, var->yres_virtual);
0813     return 0;
0814 }
0815 
0816 static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
0817 {
0818     struct fb_var_screeninfo *var = &ofb->fb.var;
0819     int pfor = NONSTD_TO_PFOR(var->nonstd);
0820     int size, bpp = 0;
0821 
0822     switch (pfor) {
0823     case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
0824     case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
0825     case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
0826     case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
0827     case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
0828     }
0829 
0830     ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
0831 
0832     size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
0833 
0834     if (ofb->video_mem) {
0835         if (ofb->video_mem_size >= size)
0836             return 0;
0837     }
0838     return -EINVAL;
0839 }
0840 
0841 static int overlayfb_set_par(struct fb_info *info)
0842 {
0843     struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
0844     struct fb_var_screeninfo *var = &info->var;
0845     int xpos, ypos, pfor, bpp, ret;
0846 
0847     ret = overlayfb_check_video_memory(ofb);
0848     if (ret)
0849         return ret;
0850 
0851     bpp  = pxafb_var_to_bpp(var);
0852     xpos = NONSTD_TO_XPOS(var->nonstd);
0853     ypos = NONSTD_TO_YPOS(var->nonstd);
0854     pfor = NONSTD_TO_PFOR(var->nonstd);
0855 
0856     ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
0857               OVLxC1_BPP(bpp);
0858     ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
0859 
0860     if (ofb->id == OVERLAY2)
0861         ofb->control[1] |= OVL2C2_PFOR(pfor);
0862 
0863     ofb->ops->setup(ofb);
0864     ofb->ops->enable(ofb);
0865     return 0;
0866 }
0867 
0868 static const struct fb_ops overlay_fb_ops = {
0869     .owner          = THIS_MODULE,
0870     .fb_open        = overlayfb_open,
0871     .fb_release     = overlayfb_release,
0872     .fb_check_var       = overlayfb_check_var,
0873     .fb_set_par     = overlayfb_set_par,
0874 };
0875 
0876 static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
0877                    int id)
0878 {
0879     sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
0880 
0881     ofb->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
0882     ofb->fb.fix.xpanstep        = 0;
0883     ofb->fb.fix.ypanstep        = 1;
0884 
0885     ofb->fb.var.activate        = FB_ACTIVATE_NOW;
0886     ofb->fb.var.height      = -1;
0887     ofb->fb.var.width       = -1;
0888     ofb->fb.var.vmode       = FB_VMODE_NONINTERLACED;
0889 
0890     ofb->fb.fbops           = &overlay_fb_ops;
0891     ofb->fb.flags           = FBINFO_FLAG_DEFAULT;
0892     ofb->fb.node            = -1;
0893     ofb->fb.pseudo_palette      = NULL;
0894 
0895     ofb->id = id;
0896     ofb->ops = &ofb_ops[id];
0897     ofb->usage = 0;
0898     ofb->fbi = fbi;
0899     init_completion(&ofb->branch_done);
0900 }
0901 
0902 static inline int pxafb_overlay_supported(void)
0903 {
0904     if (cpu_is_pxa27x() || cpu_is_pxa3xx())
0905         return 1;
0906 
0907     return 0;
0908 }
0909 
0910 static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
0911                       struct pxafb_layer *ofb)
0912 {
0913     /* We assume that user will use at most video_mem_size for overlay fb,
0914      * anyway, it's useless to use 16bpp main plane and 24bpp overlay
0915      */
0916     ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
0917         GFP_KERNEL | __GFP_ZERO);
0918     if (ofb->video_mem == NULL)
0919         return -ENOMEM;
0920 
0921     ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
0922     ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
0923 
0924     mutex_lock(&ofb->fb.mm_lock);
0925     ofb->fb.fix.smem_start  = ofb->video_mem_phys;
0926     ofb->fb.fix.smem_len    = pxafb->video_mem_size;
0927     mutex_unlock(&ofb->fb.mm_lock);
0928 
0929     ofb->fb.screen_base = ofb->video_mem;
0930 
0931     return 0;
0932 }
0933 
0934 static void pxafb_overlay_init(struct pxafb_info *fbi)
0935 {
0936     int i, ret;
0937 
0938     if (!pxafb_overlay_supported())
0939         return;
0940 
0941     for (i = 0; i < 2; i++) {
0942         struct pxafb_layer *ofb = &fbi->overlay[i];
0943         init_pxafb_overlay(fbi, ofb, i);
0944         ret = register_framebuffer(&ofb->fb);
0945         if (ret) {
0946             dev_err(fbi->dev, "failed to register overlay %d\n", i);
0947             continue;
0948         }
0949         ret = pxafb_overlay_map_video_memory(fbi, ofb);
0950         if (ret) {
0951             dev_err(fbi->dev,
0952                 "failed to map video memory for overlay %d\n",
0953                 i);
0954             unregister_framebuffer(&ofb->fb);
0955             continue;
0956         }
0957         ofb->registered = 1;
0958     }
0959 
0960     /* mask all IU/BS/EOF/SOF interrupts */
0961     lcd_writel(fbi, LCCR5, ~0);
0962 
0963     pr_info("PXA Overlay driver loaded successfully!\n");
0964 }
0965 
0966 static void pxafb_overlay_exit(struct pxafb_info *fbi)
0967 {
0968     int i;
0969 
0970     if (!pxafb_overlay_supported())
0971         return;
0972 
0973     for (i = 0; i < 2; i++) {
0974         struct pxafb_layer *ofb = &fbi->overlay[i];
0975         if (ofb->registered) {
0976             if (ofb->video_mem)
0977                 free_pages_exact(ofb->video_mem,
0978                     ofb->video_mem_size);
0979             unregister_framebuffer(&ofb->fb);
0980         }
0981     }
0982 }
0983 #else
0984 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
0985 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
0986 #endif /* CONFIG_FB_PXA_OVERLAY */
0987 
0988 /*
0989  * Calculate the PCD value from the clock rate (in picoseconds).
0990  * We take account of the PPCR clock setting.
0991  * From PXA Developer's Manual:
0992  *
0993  *   PixelClock =      LCLK
0994  *                -------------
0995  *                2 ( PCD + 1 )
0996  *
0997  *   PCD =      LCLK
0998  *         ------------- - 1
0999  *         2(PixelClock)
1000  *
1001  * Where:
1002  *   LCLK = LCD/Memory Clock
1003  *   PCD = LCCR3[7:0]
1004  *
1005  * PixelClock here is in Hz while the pixclock argument given is the
1006  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
1007  *
1008  * The function get_lclk_frequency_10khz returns LCLK in units of
1009  * 10khz. Calling the result of this function lclk gives us the
1010  * following
1011  *
1012  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1013  *          -------------------------------------- - 1
1014  *                          2
1015  *
1016  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
1017  */
1018 static inline unsigned int get_pcd(struct pxafb_info *fbi,
1019                    unsigned int pixclock)
1020 {
1021     unsigned long long pcd;
1022 
1023     /* FIXME: Need to take into account Double Pixel Clock mode
1024      * (DPC) bit? or perhaps set it based on the various clock
1025      * speeds */
1026     pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
1027     pcd *= pixclock;
1028     do_div(pcd, 100000000 * 2);
1029     /* no need for this, since we should subtract 1 anyway. they cancel */
1030     /* pcd += 1; */ /* make up for integer math truncations */
1031     return (unsigned int)pcd;
1032 }
1033 
1034 /*
1035  * Some touchscreens need hsync information from the video driver to
1036  * function correctly. We export it here.  Note that 'hsync_time' and
1037  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
1038  * of the hsync period in seconds.
1039  */
1040 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1041 {
1042     unsigned long htime;
1043 
1044     if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1045         fbi->hsync_time = 0;
1046         return;
1047     }
1048 
1049     htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1050 
1051     fbi->hsync_time = htime;
1052 }
1053 
1054 unsigned long pxafb_get_hsync_time(struct device *dev)
1055 {
1056     struct pxafb_info *fbi = dev_get_drvdata(dev);
1057 
1058     /* If display is blanked/suspended, hsync isn't active */
1059     if (!fbi || (fbi->state != C_ENABLE))
1060         return 0;
1061 
1062     return fbi->hsync_time;
1063 }
1064 EXPORT_SYMBOL(pxafb_get_hsync_time);
1065 
1066 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1067                unsigned long start, size_t size)
1068 {
1069     struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1070     unsigned int dma_desc_off, pal_desc_off;
1071 
1072     if (dma < 0 || dma >= DMA_MAX * 2)
1073         return -EINVAL;
1074 
1075     dma_desc = &fbi->dma_buff->dma_desc[dma];
1076     dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1077 
1078     dma_desc->fsadr = start;
1079     dma_desc->fidr  = 0;
1080     dma_desc->ldcmd = size;
1081 
1082     if (pal < 0 || pal >= PAL_MAX * 2) {
1083         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1084         fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1085     } else {
1086         pal_desc = &fbi->dma_buff->pal_desc[pal];
1087         pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1088 
1089         pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1090         pal_desc->fidr  = 0;
1091 
1092         if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1093             pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1094         else
1095             pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1096 
1097         pal_desc->ldcmd |= LDCMD_PAL;
1098 
1099         /* flip back and forth between palette and frame buffer */
1100         pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1101         dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1102         fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1103     }
1104 
1105     return 0;
1106 }
1107 
1108 static void setup_base_frame(struct pxafb_info *fbi,
1109                              struct fb_var_screeninfo *var,
1110                              int branch)
1111 {
1112     struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1113     int nbytes, dma, pal, bpp = var->bits_per_pixel;
1114     unsigned long offset;
1115 
1116     dma = DMA_BASE + (branch ? DMA_MAX : 0);
1117     pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1118 
1119     nbytes = fix->line_length * var->yres;
1120     offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1121 
1122     if (fbi->lccr0 & LCCR0_SDS) {
1123         nbytes = nbytes / 2;
1124         setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1125     }
1126 
1127     setup_frame_dma(fbi, dma, pal, offset, nbytes);
1128 }
1129 
1130 #ifdef CONFIG_FB_PXA_SMARTPANEL
1131 static int setup_smart_dma(struct pxafb_info *fbi)
1132 {
1133     struct pxafb_dma_descriptor *dma_desc;
1134     unsigned long dma_desc_off, cmd_buff_off;
1135 
1136     dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1137     dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1138     cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1139 
1140     dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1141     dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1142     dma_desc->fidr  = 0;
1143     dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1144 
1145     fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1146     return 0;
1147 }
1148 
1149 int pxafb_smart_flush(struct fb_info *info)
1150 {
1151     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1152     uint32_t prsr;
1153     int ret = 0;
1154 
1155     /* disable controller until all registers are set up */
1156     lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1157 
1158     /* 1. make it an even number of commands to align on 32-bit boundary
1159      * 2. add the interrupt command to the end of the chain so we can
1160      *    keep track of the end of the transfer
1161      */
1162 
1163     while (fbi->n_smart_cmds & 1)
1164         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1165 
1166     fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1167     fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1168     setup_smart_dma(fbi);
1169 
1170     /* continue to execute next command */
1171     prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1172     lcd_writel(fbi, PRSR, prsr);
1173 
1174     /* stop the processor in case it executed "wait for sync" cmd */
1175     lcd_writel(fbi, CMDCR, 0x0001);
1176 
1177     /* don't send interrupts for fifo underruns on channel 6 */
1178     lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1179 
1180     lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1181     lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1182     lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1183     lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1184     lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1185     lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1186 
1187     /* begin sending */
1188     lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1189 
1190     if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1191         pr_warn("%s: timeout waiting for command done\n", __func__);
1192         ret = -ETIMEDOUT;
1193     }
1194 
1195     /* quick disable */
1196     prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1197     lcd_writel(fbi, PRSR, prsr);
1198     lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1199     lcd_writel(fbi, FDADR6, 0);
1200     fbi->n_smart_cmds = 0;
1201     return ret;
1202 }
1203 
1204 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1205 {
1206     int i;
1207     struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1208 
1209     for (i = 0; i < n_cmds; i++, cmds++) {
1210         /* if it is a software delay, flush and delay */
1211         if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1212             pxafb_smart_flush(info);
1213             mdelay(*cmds & 0xff);
1214             continue;
1215         }
1216 
1217         /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1218         if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1219             pxafb_smart_flush(info);
1220 
1221         fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1222     }
1223 
1224     return 0;
1225 }
1226 
1227 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1228 {
1229     unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1230     return (t == 0) ? 1 : t;
1231 }
1232 
1233 static void setup_smart_timing(struct pxafb_info *fbi,
1234                 struct fb_var_screeninfo *var)
1235 {
1236     struct pxafb_mach_info *inf = fbi->inf;
1237     struct pxafb_mode_info *mode = &inf->modes[0];
1238     unsigned long lclk = clk_get_rate(fbi->clk);
1239     unsigned t1, t2, t3, t4;
1240 
1241     t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1242     t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1243     t3 = mode->op_hold_time;
1244     t4 = mode->cmd_inh_time;
1245 
1246     fbi->reg_lccr1 =
1247         LCCR1_DisWdth(var->xres) |
1248         LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1249         LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1250         LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1251 
1252     fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1253     fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1254     fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1255     fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1256 
1257     /* FIXME: make this configurable */
1258     fbi->reg_cmdcr = 1;
1259 }
1260 
1261 static int pxafb_smart_thread(void *arg)
1262 {
1263     struct pxafb_info *fbi = arg;
1264     struct pxafb_mach_info *inf = fbi->inf;
1265 
1266     if (!inf->smart_update) {
1267         pr_err("%s: not properly initialized, thread terminated\n",
1268                 __func__);
1269         return -EINVAL;
1270     }
1271 
1272     pr_debug("%s(): task starting\n", __func__);
1273 
1274     set_freezable();
1275     while (!kthread_should_stop()) {
1276 
1277         if (try_to_freeze())
1278             continue;
1279 
1280         mutex_lock(&fbi->ctrlr_lock);
1281 
1282         if (fbi->state == C_ENABLE) {
1283             inf->smart_update(&fbi->fb);
1284             complete(&fbi->refresh_done);
1285         }
1286 
1287         mutex_unlock(&fbi->ctrlr_lock);
1288 
1289         set_current_state(TASK_INTERRUPTIBLE);
1290         schedule_timeout(msecs_to_jiffies(30));
1291     }
1292 
1293     pr_debug("%s(): task ending\n", __func__);
1294     return 0;
1295 }
1296 
1297 static int pxafb_smart_init(struct pxafb_info *fbi)
1298 {
1299     if (!(fbi->lccr0 & LCCR0_LCDT))
1300         return 0;
1301 
1302     fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1303     fbi->n_smart_cmds = 0;
1304 
1305     init_completion(&fbi->command_done);
1306     init_completion(&fbi->refresh_done);
1307 
1308     fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1309                     "lcd_refresh");
1310     if (IS_ERR(fbi->smart_thread)) {
1311         pr_err("%s: unable to create kernel thread\n", __func__);
1312         return PTR_ERR(fbi->smart_thread);
1313     }
1314 
1315     return 0;
1316 }
1317 #else
1318 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1319 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1320 
1321 static void setup_parallel_timing(struct pxafb_info *fbi,
1322                   struct fb_var_screeninfo *var)
1323 {
1324     unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1325 
1326     fbi->reg_lccr1 =
1327         LCCR1_DisWdth(var->xres) +
1328         LCCR1_HorSnchWdth(var->hsync_len) +
1329         LCCR1_BegLnDel(var->left_margin) +
1330         LCCR1_EndLnDel(var->right_margin);
1331 
1332     /*
1333      * If we have a dual scan LCD, we need to halve
1334      * the YRES parameter.
1335      */
1336     lines_per_panel = var->yres;
1337     if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1338         lines_per_panel /= 2;
1339 
1340     fbi->reg_lccr2 =
1341         LCCR2_DisHght(lines_per_panel) +
1342         LCCR2_VrtSnchWdth(var->vsync_len) +
1343         LCCR2_BegFrmDel(var->upper_margin) +
1344         LCCR2_EndFrmDel(var->lower_margin);
1345 
1346     fbi->reg_lccr3 = fbi->lccr3 |
1347         (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1348          LCCR3_HorSnchH : LCCR3_HorSnchL) |
1349         (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1350          LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1351 
1352     if (pcd) {
1353         fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1354         set_hsync_time(fbi, pcd);
1355     }
1356 }
1357 
1358 /*
1359  * pxafb_activate_var():
1360  *  Configures LCD Controller based on entries in var parameter.
1361  *  Settings are only written to the controller if changes were made.
1362  */
1363 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1364                   struct pxafb_info *fbi)
1365 {
1366     u_long flags;
1367 
1368     /* Update shadow copy atomically */
1369     local_irq_save(flags);
1370 
1371 #ifdef CONFIG_FB_PXA_SMARTPANEL
1372     if (fbi->lccr0 & LCCR0_LCDT)
1373         setup_smart_timing(fbi, var);
1374     else
1375 #endif
1376         setup_parallel_timing(fbi, var);
1377 
1378     setup_base_frame(fbi, var, 0);
1379 
1380     fbi->reg_lccr0 = fbi->lccr0 |
1381         (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1382          LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
1383 
1384     fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1385 
1386     fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1387     fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1388     local_irq_restore(flags);
1389 
1390     /*
1391      * Only update the registers if the controller is enabled
1392      * and something has changed.
1393      */
1394     if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1395         (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1396         (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1397         (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1398         (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1399         (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1400         ((fbi->lccr0 & LCCR0_SDS) &&
1401         (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1402         pxafb_schedule_work(fbi, C_REENABLE);
1403 
1404     return 0;
1405 }
1406 
1407 /*
1408  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
1409  * Do not call them directly; set_ctrlr_state does the correct serialisation
1410  * to ensure that things happen in the right way 100% of time time.
1411  *  -- rmk
1412  */
1413 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1414 {
1415     pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1416 
1417     if (fbi->backlight_power)
1418         fbi->backlight_power(on);
1419 }
1420 
1421 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1422 {
1423     pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1424 
1425     if (fbi->lcd_power)
1426         fbi->lcd_power(on, &fbi->fb.var);
1427 
1428     if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) {
1429         int ret;
1430 
1431         if (on)
1432             ret = regulator_enable(fbi->lcd_supply);
1433         else
1434             ret = regulator_disable(fbi->lcd_supply);
1435 
1436         if (ret < 0)
1437             pr_warn("Unable to %s LCD supply regulator: %d\n",
1438                 on ? "enable" : "disable", ret);
1439         else
1440             fbi->lcd_supply_enabled = on;
1441     }
1442 }
1443 
1444 static void pxafb_enable_controller(struct pxafb_info *fbi)
1445 {
1446     pr_debug("pxafb: Enabling LCD controller\n");
1447     pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1448     pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1449     pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1450     pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1451     pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1452     pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1453 
1454     /* enable LCD controller clock */
1455     if (clk_prepare_enable(fbi->clk)) {
1456         pr_err("%s: Failed to prepare clock\n", __func__);
1457         return;
1458     }
1459 
1460     if (fbi->lccr0 & LCCR0_LCDT)
1461         return;
1462 
1463     /* Sequence from 11.7.10 */
1464     lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1465     lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1466     lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1467     lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1468     lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1469 
1470     lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1471     if (fbi->lccr0 & LCCR0_SDS)
1472         lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1473     lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1474 }
1475 
1476 static void pxafb_disable_controller(struct pxafb_info *fbi)
1477 {
1478     uint32_t lccr0;
1479 
1480 #ifdef CONFIG_FB_PXA_SMARTPANEL
1481     if (fbi->lccr0 & LCCR0_LCDT) {
1482         wait_for_completion_timeout(&fbi->refresh_done,
1483                 msecs_to_jiffies(200));
1484         return;
1485     }
1486 #endif
1487 
1488     /* Clear LCD Status Register */
1489     lcd_writel(fbi, LCSR, 0xffffffff);
1490 
1491     lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1492     lcd_writel(fbi, LCCR0, lccr0);
1493     lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1494 
1495     wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200));
1496 
1497     /* disable LCD controller clock */
1498     clk_disable_unprepare(fbi->clk);
1499 }
1500 
1501 /*
1502  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1503  */
1504 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1505 {
1506     struct pxafb_info *fbi = dev_id;
1507     unsigned int lccr0, lcsr;
1508 
1509     lcsr = lcd_readl(fbi, LCSR);
1510     if (lcsr & LCSR_LDD) {
1511         lccr0 = lcd_readl(fbi, LCCR0);
1512         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1513         complete(&fbi->disable_done);
1514     }
1515 
1516 #ifdef CONFIG_FB_PXA_SMARTPANEL
1517     if (lcsr & LCSR_CMD_INT)
1518         complete(&fbi->command_done);
1519 #endif
1520     lcd_writel(fbi, LCSR, lcsr);
1521 
1522 #ifdef CONFIG_FB_PXA_OVERLAY
1523     {
1524         unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1525         if (lcsr1 & LCSR1_BS(1))
1526             complete(&fbi->overlay[0].branch_done);
1527 
1528         if (lcsr1 & LCSR1_BS(2))
1529             complete(&fbi->overlay[1].branch_done);
1530 
1531         lcd_writel(fbi, LCSR1, lcsr1);
1532     }
1533 #endif
1534     return IRQ_HANDLED;
1535 }
1536 
1537 /*
1538  * This function must be called from task context only, since it will
1539  * sleep when disabling the LCD controller, or if we get two contending
1540  * processes trying to alter state.
1541  */
1542 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1543 {
1544     u_int old_state;
1545 
1546     mutex_lock(&fbi->ctrlr_lock);
1547 
1548     old_state = fbi->state;
1549 
1550     /*
1551      * Hack around fbcon initialisation.
1552      */
1553     if (old_state == C_STARTUP && state == C_REENABLE)
1554         state = C_ENABLE;
1555 
1556     switch (state) {
1557     case C_DISABLE_CLKCHANGE:
1558         /*
1559          * Disable controller for clock change.  If the
1560          * controller is already disabled, then do nothing.
1561          */
1562         if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1563             fbi->state = state;
1564             /* TODO __pxafb_lcd_power(fbi, 0); */
1565             pxafb_disable_controller(fbi);
1566         }
1567         break;
1568 
1569     case C_DISABLE_PM:
1570     case C_DISABLE:
1571         /*
1572          * Disable controller
1573          */
1574         if (old_state != C_DISABLE) {
1575             fbi->state = state;
1576             __pxafb_backlight_power(fbi, 0);
1577             __pxafb_lcd_power(fbi, 0);
1578             if (old_state != C_DISABLE_CLKCHANGE)
1579                 pxafb_disable_controller(fbi);
1580         }
1581         break;
1582 
1583     case C_ENABLE_CLKCHANGE:
1584         /*
1585          * Enable the controller after clock change.  Only
1586          * do this if we were disabled for the clock change.
1587          */
1588         if (old_state == C_DISABLE_CLKCHANGE) {
1589             fbi->state = C_ENABLE;
1590             pxafb_enable_controller(fbi);
1591             /* TODO __pxafb_lcd_power(fbi, 1); */
1592         }
1593         break;
1594 
1595     case C_REENABLE:
1596         /*
1597          * Re-enable the controller only if it was already
1598          * enabled.  This is so we reprogram the control
1599          * registers.
1600          */
1601         if (old_state == C_ENABLE) {
1602             __pxafb_lcd_power(fbi, 0);
1603             pxafb_disable_controller(fbi);
1604             pxafb_enable_controller(fbi);
1605             __pxafb_lcd_power(fbi, 1);
1606         }
1607         break;
1608 
1609     case C_ENABLE_PM:
1610         /*
1611          * Re-enable the controller after PM.  This is not
1612          * perfect - think about the case where we were doing
1613          * a clock change, and we suspended half-way through.
1614          */
1615         if (old_state != C_DISABLE_PM)
1616             break;
1617         fallthrough;
1618 
1619     case C_ENABLE:
1620         /*
1621          * Power up the LCD screen, enable controller, and
1622          * turn on the backlight.
1623          */
1624         if (old_state != C_ENABLE) {
1625             fbi->state = C_ENABLE;
1626             pxafb_enable_controller(fbi);
1627             __pxafb_lcd_power(fbi, 1);
1628             __pxafb_backlight_power(fbi, 1);
1629         }
1630         break;
1631     }
1632     mutex_unlock(&fbi->ctrlr_lock);
1633 }
1634 
1635 /*
1636  * Our LCD controller task (which is called when we blank or unblank)
1637  * via keventd.
1638  */
1639 static void pxafb_task(struct work_struct *work)
1640 {
1641     struct pxafb_info *fbi =
1642         container_of(work, struct pxafb_info, task);
1643     u_int state = xchg(&fbi->task_state, -1);
1644 
1645     set_ctrlr_state(fbi, state);
1646 }
1647 
1648 #ifdef CONFIG_CPU_FREQ
1649 /*
1650  * CPU clock speed change handler.  We need to adjust the LCD timing
1651  * parameters when the CPU clock is adjusted by the power management
1652  * subsystem.
1653  *
1654  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1655  */
1656 static int
1657 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1658 {
1659     struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1660     /* TODO struct cpufreq_freqs *f = data; */
1661     u_int pcd;
1662 
1663     switch (val) {
1664     case CPUFREQ_PRECHANGE:
1665 #ifdef CONFIG_FB_PXA_OVERLAY
1666         if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1667 #endif
1668             set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1669         break;
1670 
1671     case CPUFREQ_POSTCHANGE:
1672         pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1673         set_hsync_time(fbi, pcd);
1674         fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1675                   LCCR3_PixClkDiv(pcd);
1676         set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1677         break;
1678     }
1679     return 0;
1680 }
1681 #endif
1682 
1683 #ifdef CONFIG_PM
1684 /*
1685  * Power management hooks.  Note that we won't be called from IRQ context,
1686  * unlike the blank functions above, so we may sleep.
1687  */
1688 static int pxafb_suspend(struct device *dev)
1689 {
1690     struct pxafb_info *fbi = dev_get_drvdata(dev);
1691 
1692     set_ctrlr_state(fbi, C_DISABLE_PM);
1693     return 0;
1694 }
1695 
1696 static int pxafb_resume(struct device *dev)
1697 {
1698     struct pxafb_info *fbi = dev_get_drvdata(dev);
1699 
1700     set_ctrlr_state(fbi, C_ENABLE_PM);
1701     return 0;
1702 }
1703 
1704 static const struct dev_pm_ops pxafb_pm_ops = {
1705     .suspend    = pxafb_suspend,
1706     .resume     = pxafb_resume,
1707 };
1708 #endif
1709 
1710 static int pxafb_init_video_memory(struct pxafb_info *fbi)
1711 {
1712     int size = PAGE_ALIGN(fbi->video_mem_size);
1713 
1714     fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1715     if (fbi->video_mem == NULL)
1716         return -ENOMEM;
1717 
1718     fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1719     fbi->video_mem_size = size;
1720 
1721     fbi->fb.fix.smem_start  = fbi->video_mem_phys;
1722     fbi->fb.fix.smem_len    = fbi->video_mem_size;
1723     fbi->fb.screen_base = fbi->video_mem;
1724 
1725     return fbi->video_mem ? 0 : -ENOMEM;
1726 }
1727 
1728 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1729                    struct pxafb_mach_info *inf)
1730 {
1731     unsigned int lcd_conn = inf->lcd_conn;
1732     struct pxafb_mode_info *m;
1733     int i;
1734 
1735     fbi->cmap_inverse   = inf->cmap_inverse;
1736     fbi->cmap_static    = inf->cmap_static;
1737     fbi->lccr4      = inf->lccr4;
1738 
1739     switch (lcd_conn & LCD_TYPE_MASK) {
1740     case LCD_TYPE_MONO_STN:
1741         fbi->lccr0 = LCCR0_CMS;
1742         break;
1743     case LCD_TYPE_MONO_DSTN:
1744         fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1745         break;
1746     case LCD_TYPE_COLOR_STN:
1747         fbi->lccr0 = 0;
1748         break;
1749     case LCD_TYPE_COLOR_DSTN:
1750         fbi->lccr0 = LCCR0_SDS;
1751         break;
1752     case LCD_TYPE_COLOR_TFT:
1753         fbi->lccr0 = LCCR0_PAS;
1754         break;
1755     case LCD_TYPE_SMART_PANEL:
1756         fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1757         break;
1758     default:
1759         /* fall back to backward compatibility way */
1760         fbi->lccr0 = inf->lccr0;
1761         fbi->lccr3 = inf->lccr3;
1762         goto decode_mode;
1763     }
1764 
1765     if (lcd_conn == LCD_MONO_STN_8BPP)
1766         fbi->lccr0 |= LCCR0_DPD;
1767 
1768     fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1769 
1770     fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1771     fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1772     fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1773 
1774 decode_mode:
1775     pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1776 
1777     /* decide video memory size as follows:
1778      * 1. default to mode of maximum resolution
1779      * 2. allow platform to override
1780      * 3. allow module parameter to override
1781      */
1782     for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1783         fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1784                 m->xres * m->yres * m->bpp / 8);
1785 
1786     if (inf->video_mem_size > fbi->video_mem_size)
1787         fbi->video_mem_size = inf->video_mem_size;
1788 
1789     if (video_mem_size > fbi->video_mem_size)
1790         fbi->video_mem_size = video_mem_size;
1791 }
1792 
1793 static struct pxafb_info *pxafb_init_fbinfo(struct device *dev,
1794                         struct pxafb_mach_info *inf)
1795 {
1796     struct pxafb_info *fbi;
1797     void *addr;
1798 
1799     /* Alloc the pxafb_info and pseudo_palette in one step */
1800     fbi = devm_kzalloc(dev, sizeof(struct pxafb_info) + sizeof(u32) * 16,
1801                GFP_KERNEL);
1802     if (!fbi)
1803         return ERR_PTR(-ENOMEM);
1804 
1805     fbi->dev = dev;
1806     fbi->inf = inf;
1807 
1808     fbi->clk = devm_clk_get(dev, NULL);
1809     if (IS_ERR(fbi->clk))
1810         return ERR_CAST(fbi->clk);
1811 
1812     strcpy(fbi->fb.fix.id, PXA_NAME);
1813 
1814     fbi->fb.fix.type    = FB_TYPE_PACKED_PIXELS;
1815     fbi->fb.fix.type_aux    = 0;
1816     fbi->fb.fix.xpanstep    = 0;
1817     fbi->fb.fix.ypanstep    = 1;
1818     fbi->fb.fix.ywrapstep   = 0;
1819     fbi->fb.fix.accel   = FB_ACCEL_NONE;
1820 
1821     fbi->fb.var.nonstd  = 0;
1822     fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1823     fbi->fb.var.height  = -1;
1824     fbi->fb.var.width   = -1;
1825     fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1826     fbi->fb.var.vmode   = FB_VMODE_NONINTERLACED;
1827 
1828     fbi->fb.fbops       = &pxafb_ops;
1829     fbi->fb.flags       = FBINFO_DEFAULT;
1830     fbi->fb.node        = -1;
1831 
1832     addr = fbi;
1833     addr = addr + sizeof(struct pxafb_info);
1834     fbi->fb.pseudo_palette  = addr;
1835 
1836     fbi->state      = C_STARTUP;
1837     fbi->task_state     = (u_char)-1;
1838 
1839     pxafb_decode_mach_info(fbi, inf);
1840 
1841 #ifdef CONFIG_FB_PXA_OVERLAY
1842     /* place overlay(s) on top of base */
1843     if (pxafb_overlay_supported())
1844         fbi->lccr0 |= LCCR0_OUC;
1845 #endif
1846 
1847     init_waitqueue_head(&fbi->ctrlr_wait);
1848     INIT_WORK(&fbi->task, pxafb_task);
1849     mutex_init(&fbi->ctrlr_lock);
1850     init_completion(&fbi->disable_done);
1851 
1852     return fbi;
1853 }
1854 
1855 #ifdef CONFIG_FB_PXA_PARAMETERS
1856 static int parse_opt_mode(struct device *dev, const char *this_opt,
1857               struct pxafb_mach_info *inf)
1858 {
1859     const char *name = this_opt+5;
1860     unsigned int namelen = strlen(name);
1861     int res_specified = 0, bpp_specified = 0;
1862     unsigned int xres = 0, yres = 0, bpp = 0;
1863     int yres_specified = 0;
1864     int i;
1865     for (i = namelen-1; i >= 0; i--) {
1866         switch (name[i]) {
1867         case '-':
1868             namelen = i;
1869             if (!bpp_specified && !yres_specified) {
1870                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1871                 bpp_specified = 1;
1872             } else
1873                 goto done;
1874             break;
1875         case 'x':
1876             if (!yres_specified) {
1877                 yres = simple_strtoul(&name[i+1], NULL, 0);
1878                 yres_specified = 1;
1879             } else
1880                 goto done;
1881             break;
1882         case '0' ... '9':
1883             break;
1884         default:
1885             goto done;
1886         }
1887     }
1888     if (i < 0 && yres_specified) {
1889         xres = simple_strtoul(name, NULL, 0);
1890         res_specified = 1;
1891     }
1892 done:
1893     if (res_specified) {
1894         dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1895         inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1896     }
1897     if (bpp_specified)
1898         switch (bpp) {
1899         case 1:
1900         case 2:
1901         case 4:
1902         case 8:
1903         case 16:
1904             inf->modes[0].bpp = bpp;
1905             dev_info(dev, "overriding bit depth: %d\n", bpp);
1906             break;
1907         default:
1908             dev_err(dev, "Depth %d is not valid\n", bpp);
1909             return -EINVAL;
1910         }
1911     return 0;
1912 }
1913 
1914 static int parse_opt(struct device *dev, char *this_opt,
1915              struct pxafb_mach_info *inf)
1916 {
1917     struct pxafb_mode_info *mode = &inf->modes[0];
1918     char s[64];
1919 
1920     s[0] = '\0';
1921 
1922     if (!strncmp(this_opt, "vmem:", 5)) {
1923         video_mem_size = memparse(this_opt + 5, NULL);
1924     } else if (!strncmp(this_opt, "mode:", 5)) {
1925         return parse_opt_mode(dev, this_opt, inf);
1926     } else if (!strncmp(this_opt, "pixclock:", 9)) {
1927         mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1928         sprintf(s, "pixclock: %ld\n", mode->pixclock);
1929     } else if (!strncmp(this_opt, "left:", 5)) {
1930         mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1931         sprintf(s, "left: %u\n", mode->left_margin);
1932     } else if (!strncmp(this_opt, "right:", 6)) {
1933         mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1934         sprintf(s, "right: %u\n", mode->right_margin);
1935     } else if (!strncmp(this_opt, "upper:", 6)) {
1936         mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1937         sprintf(s, "upper: %u\n", mode->upper_margin);
1938     } else if (!strncmp(this_opt, "lower:", 6)) {
1939         mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1940         sprintf(s, "lower: %u\n", mode->lower_margin);
1941     } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1942         mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1943         sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1944     } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1945         mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1946         sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1947     } else if (!strncmp(this_opt, "hsync:", 6)) {
1948         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1949             sprintf(s, "hsync: Active Low\n");
1950             mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1951         } else {
1952             sprintf(s, "hsync: Active High\n");
1953             mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1954         }
1955     } else if (!strncmp(this_opt, "vsync:", 6)) {
1956         if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1957             sprintf(s, "vsync: Active Low\n");
1958             mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1959         } else {
1960             sprintf(s, "vsync: Active High\n");
1961             mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1962         }
1963     } else if (!strncmp(this_opt, "dpc:", 4)) {
1964         if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1965             sprintf(s, "double pixel clock: false\n");
1966             inf->lccr3 &= ~LCCR3_DPC;
1967         } else {
1968             sprintf(s, "double pixel clock: true\n");
1969             inf->lccr3 |= LCCR3_DPC;
1970         }
1971     } else if (!strncmp(this_opt, "outputen:", 9)) {
1972         if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1973             sprintf(s, "output enable: active low\n");
1974             inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1975         } else {
1976             sprintf(s, "output enable: active high\n");
1977             inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1978         }
1979     } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1980         if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1981             sprintf(s, "pixel clock polarity: falling edge\n");
1982             inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1983         } else {
1984             sprintf(s, "pixel clock polarity: rising edge\n");
1985             inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1986         }
1987     } else if (!strncmp(this_opt, "color", 5)) {
1988         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1989     } else if (!strncmp(this_opt, "mono", 4)) {
1990         inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1991     } else if (!strncmp(this_opt, "active", 6)) {
1992         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1993     } else if (!strncmp(this_opt, "passive", 7)) {
1994         inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1995     } else if (!strncmp(this_opt, "single", 6)) {
1996         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1997     } else if (!strncmp(this_opt, "dual", 4)) {
1998         inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1999     } else if (!strncmp(this_opt, "4pix", 4)) {
2000         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
2001     } else if (!strncmp(this_opt, "8pix", 4)) {
2002         inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
2003     } else {
2004         dev_err(dev, "unknown option: %s\n", this_opt);
2005         return -EINVAL;
2006     }
2007 
2008     if (s[0] != '\0')
2009         dev_info(dev, "override %s", s);
2010 
2011     return 0;
2012 }
2013 
2014 static int pxafb_parse_options(struct device *dev, char *options,
2015                    struct pxafb_mach_info *inf)
2016 {
2017     char *this_opt;
2018     int ret;
2019 
2020     if (!options || !*options)
2021         return 0;
2022 
2023     dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2024 
2025     /* could be made table driven or similar?... */
2026     while ((this_opt = strsep(&options, ",")) != NULL) {
2027         ret = parse_opt(dev, this_opt, inf);
2028         if (ret)
2029             return ret;
2030     }
2031     return 0;
2032 }
2033 
2034 static char g_options[256] = "";
2035 
2036 #ifndef MODULE
2037 static int __init pxafb_setup_options(void)
2038 {
2039     char *options = NULL;
2040 
2041     if (fb_get_options("pxafb", &options))
2042         return -ENODEV;
2043 
2044     if (options)
2045         strscpy(g_options, options, sizeof(g_options));
2046 
2047     return 0;
2048 }
2049 #else
2050 #define pxafb_setup_options()       (0)
2051 
2052 module_param_string(options, g_options, sizeof(g_options), 0);
2053 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.rst)");
2054 #endif
2055 
2056 #else
2057 #define pxafb_parse_options(...)    (0)
2058 #define pxafb_setup_options()       (0)
2059 #endif
2060 
2061 #ifdef DEBUG_VAR
2062 /* Check for various illegal bit-combinations. Currently only
2063  * a warning is given. */
2064 static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
2065 {
2066     if (inf->lcd_conn)
2067         return;
2068 
2069     if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2070         dev_warn(dev, "machine LCCR0 setting contains "
2071                 "illegal bits: %08x\n",
2072             inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2073     if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2074         dev_warn(dev, "machine LCCR3 setting contains "
2075                 "illegal bits: %08x\n",
2076             inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2077     if (inf->lccr0 & LCCR0_DPD &&
2078         ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2079          (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2080          (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2081         dev_warn(dev, "Double Pixel Data (DPD) mode is "
2082                 "only valid in passive mono"
2083                 " single panel mode\n");
2084     if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2085         (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2086         dev_warn(dev, "Dual panel only valid in passive mode\n");
2087     if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2088          (inf->modes->upper_margin || inf->modes->lower_margin))
2089         dev_warn(dev, "Upper and lower margins must be 0 in "
2090                 "passive mode\n");
2091 }
2092 #else
2093 #define pxafb_check_options(...)    do {} while (0)
2094 #endif
2095 
2096 #if defined(CONFIG_OF)
2097 static const char * const lcd_types[] = {
2098     "unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn",
2099     "color-tft", "smart-panel", NULL
2100 };
2101 
2102 static int of_get_pxafb_display(struct device *dev, struct device_node *disp,
2103                 struct pxafb_mach_info *info, u32 bus_width)
2104 {
2105     struct display_timings *timings;
2106     struct videomode vm;
2107     int i, ret = -EINVAL;
2108     const char *s;
2109 
2110     ret = of_property_read_string(disp, "lcd-type", &s);
2111     if (ret)
2112         s = "color-tft";
2113 
2114     i = match_string(lcd_types, -1, s);
2115     if (i < 0) {
2116         dev_err(dev, "lcd-type %s is unknown\n", s);
2117         return i;
2118     }
2119     info->lcd_conn |= LCD_CONN_TYPE(i);
2120     info->lcd_conn |= LCD_CONN_WIDTH(bus_width);
2121 
2122     timings = of_get_display_timings(disp);
2123     if (!timings)
2124         return -EINVAL;
2125 
2126     ret = -ENOMEM;
2127     info->modes = devm_kcalloc(dev, timings->num_timings,
2128                    sizeof(info->modes[0]),
2129                    GFP_KERNEL);
2130     if (!info->modes)
2131         goto out;
2132     info->num_modes = timings->num_timings;
2133 
2134     for (i = 0; i < timings->num_timings; i++) {
2135         ret = videomode_from_timings(timings, &vm, i);
2136         if (ret) {
2137             dev_err(dev, "videomode_from_timings %d failed: %d\n",
2138                 i, ret);
2139             goto out;
2140         }
2141         if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
2142             info->lcd_conn |= LCD_PCLK_EDGE_RISE;
2143         if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
2144             info->lcd_conn |= LCD_PCLK_EDGE_FALL;
2145         if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
2146             info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH;
2147         if (vm.flags & DISPLAY_FLAGS_DE_LOW)
2148             info->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
2149         if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
2150             info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT;
2151         if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
2152             info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT;
2153 
2154         info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000);
2155         info->modes[i].xres = vm.hactive;
2156         info->modes[i].yres = vm.vactive;
2157         info->modes[i].hsync_len = vm.hsync_len;
2158         info->modes[i].left_margin = vm.hback_porch;
2159         info->modes[i].right_margin = vm.hfront_porch;
2160         info->modes[i].vsync_len = vm.vsync_len;
2161         info->modes[i].upper_margin = vm.vback_porch;
2162         info->modes[i].lower_margin = vm.vfront_porch;
2163     }
2164     ret = 0;
2165 
2166 out:
2167     display_timings_release(timings);
2168     return ret;
2169 }
2170 
2171 static int of_get_pxafb_mode_info(struct device *dev,
2172                   struct pxafb_mach_info *info)
2173 {
2174     struct device_node *display, *np;
2175     u32 bus_width;
2176     int ret, i;
2177 
2178     np = of_graph_get_next_endpoint(dev->of_node, NULL);
2179     if (!np) {
2180         dev_err(dev, "could not find endpoint\n");
2181         return -EINVAL;
2182     }
2183     ret = of_property_read_u32(np, "bus-width", &bus_width);
2184     if (ret) {
2185         dev_err(dev, "no bus-width specified: %d\n", ret);
2186         of_node_put(np);
2187         return ret;
2188     }
2189 
2190     display = of_graph_get_remote_port_parent(np);
2191     of_node_put(np);
2192     if (!display) {
2193         dev_err(dev, "no display defined\n");
2194         return -EINVAL;
2195     }
2196 
2197     ret = of_get_pxafb_display(dev, display, info, bus_width);
2198     of_node_put(display);
2199     if (ret)
2200         return ret;
2201 
2202     for (i = 0; i < info->num_modes; i++)
2203         info->modes[i].bpp = bus_width;
2204 
2205     return 0;
2206 }
2207 
2208 static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2209 {
2210     int ret;
2211     struct pxafb_mach_info *info;
2212 
2213     if (!dev->of_node)
2214         return NULL;
2215     info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2216     if (!info)
2217         return ERR_PTR(-ENOMEM);
2218     ret = of_get_pxafb_mode_info(dev, info);
2219     if (ret)
2220         return ERR_PTR(ret);
2221 
2222     /*
2223      * On purpose, neither lccrX registers nor video memory size can be
2224      * specified through device-tree, they are considered more a debug hack
2225      * available through command line.
2226      */
2227     return info;
2228 }
2229 #else
2230 static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
2231 {
2232     return NULL;
2233 }
2234 #endif
2235 
2236 static int pxafb_probe(struct platform_device *dev)
2237 {
2238     struct pxafb_info *fbi;
2239     struct pxafb_mach_info *inf, *pdata;
2240     int i, irq, ret;
2241 
2242     dev_dbg(&dev->dev, "pxafb_probe\n");
2243 
2244     ret = -ENOMEM;
2245     pdata = dev_get_platdata(&dev->dev);
2246     inf = devm_kmalloc(&dev->dev, sizeof(*inf), GFP_KERNEL);
2247     if (!inf)
2248         goto failed;
2249 
2250     if (pdata) {
2251         *inf = *pdata;
2252         inf->modes =
2253             devm_kmalloc_array(&dev->dev, pdata->num_modes,
2254                        sizeof(inf->modes[0]), GFP_KERNEL);
2255         if (!inf->modes)
2256             goto failed;
2257         for (i = 0; i < inf->num_modes; i++)
2258             inf->modes[i] = pdata->modes[i];
2259     } else {
2260         inf = of_pxafb_of_mach_info(&dev->dev);
2261     }
2262 
2263     if (IS_ERR_OR_NULL(inf))
2264         goto failed;
2265 
2266     ret = pxafb_parse_options(&dev->dev, g_options, inf);
2267     if (ret < 0)
2268         goto failed;
2269 
2270     pxafb_check_options(&dev->dev, inf);
2271 
2272     dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2273             inf->modes->xres,
2274             inf->modes->yres,
2275             inf->modes->bpp);
2276     if (inf->modes->xres == 0 ||
2277         inf->modes->yres == 0 ||
2278         inf->modes->bpp == 0) {
2279         dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2280         ret = -EINVAL;
2281         goto failed;
2282     }
2283 
2284     fbi = pxafb_init_fbinfo(&dev->dev, inf);
2285     if (IS_ERR(fbi)) {
2286         dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2287         ret = PTR_ERR(fbi);
2288         goto failed;
2289     }
2290 
2291     if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2292         fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2293 
2294     fbi->backlight_power = inf->pxafb_backlight_power;
2295     fbi->lcd_power = inf->pxafb_lcd_power;
2296 
2297     fbi->lcd_supply = devm_regulator_get_optional(&dev->dev, "lcd");
2298     if (IS_ERR(fbi->lcd_supply)) {
2299         if (PTR_ERR(fbi->lcd_supply) == -EPROBE_DEFER)
2300             return -EPROBE_DEFER;
2301 
2302         fbi->lcd_supply = NULL;
2303     }
2304 
2305     fbi->mmio_base = devm_platform_ioremap_resource(dev, 0);
2306     if (IS_ERR(fbi->mmio_base)) {
2307         dev_err(&dev->dev, "failed to get I/O memory\n");
2308         ret = PTR_ERR(fbi->mmio_base);
2309         goto failed;
2310     }
2311 
2312     fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2313     fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2314                 &fbi->dma_buff_phys, GFP_KERNEL);
2315     if (fbi->dma_buff == NULL) {
2316         dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2317         ret = -ENOMEM;
2318         goto failed;
2319     }
2320 
2321     ret = pxafb_init_video_memory(fbi);
2322     if (ret) {
2323         dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2324         ret = -ENOMEM;
2325         goto failed_free_dma;
2326     }
2327 
2328     irq = platform_get_irq(dev, 0);
2329     if (irq < 0) {
2330         dev_err(&dev->dev, "no IRQ defined\n");
2331         ret = -ENODEV;
2332         goto failed_free_mem;
2333     }
2334 
2335     ret = devm_request_irq(&dev->dev, irq, pxafb_handle_irq, 0, "LCD", fbi);
2336     if (ret) {
2337         dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2338         ret = -EBUSY;
2339         goto failed_free_mem;
2340     }
2341 
2342     ret = pxafb_smart_init(fbi);
2343     if (ret) {
2344         dev_err(&dev->dev, "failed to initialize smartpanel\n");
2345         goto failed_free_mem;
2346     }
2347 
2348     /*
2349      * This makes sure that our colour bitfield
2350      * descriptors are correctly initialised.
2351      */
2352     ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2353     if (ret) {
2354         dev_err(&dev->dev, "failed to get suitable mode\n");
2355         goto failed_free_mem;
2356     }
2357 
2358     ret = pxafb_set_par(&fbi->fb);
2359     if (ret) {
2360         dev_err(&dev->dev, "Failed to set parameters\n");
2361         goto failed_free_mem;
2362     }
2363 
2364     platform_set_drvdata(dev, fbi);
2365 
2366     ret = register_framebuffer(&fbi->fb);
2367     if (ret < 0) {
2368         dev_err(&dev->dev,
2369             "Failed to register framebuffer device: %d\n", ret);
2370         goto failed_free_cmap;
2371     }
2372 
2373     pxafb_overlay_init(fbi);
2374 
2375 #ifdef CONFIG_CPU_FREQ
2376     fbi->freq_transition.notifier_call = pxafb_freq_transition;
2377     cpufreq_register_notifier(&fbi->freq_transition,
2378                 CPUFREQ_TRANSITION_NOTIFIER);
2379 #endif
2380 
2381     /*
2382      * Ok, now enable the LCD controller
2383      */
2384     set_ctrlr_state(fbi, C_ENABLE);
2385 
2386     return 0;
2387 
2388 failed_free_cmap:
2389     if (fbi->fb.cmap.len)
2390         fb_dealloc_cmap(&fbi->fb.cmap);
2391 failed_free_mem:
2392     free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2393 failed_free_dma:
2394     dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2395             fbi->dma_buff, fbi->dma_buff_phys);
2396 failed:
2397     return ret;
2398 }
2399 
2400 static int pxafb_remove(struct platform_device *dev)
2401 {
2402     struct pxafb_info *fbi = platform_get_drvdata(dev);
2403     struct fb_info *info;
2404 
2405     if (!fbi)
2406         return 0;
2407 
2408     info = &fbi->fb;
2409 
2410     pxafb_overlay_exit(fbi);
2411     unregister_framebuffer(info);
2412 
2413     pxafb_disable_controller(fbi);
2414 
2415     if (fbi->fb.cmap.len)
2416         fb_dealloc_cmap(&fbi->fb.cmap);
2417 
2418     free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2419 
2420     dma_free_coherent(&dev->dev, fbi->dma_buff_size, fbi->dma_buff,
2421               fbi->dma_buff_phys);
2422 
2423     return 0;
2424 }
2425 
2426 static const struct of_device_id pxafb_of_dev_id[] = {
2427     { .compatible = "marvell,pxa270-lcdc", },
2428     { .compatible = "marvell,pxa300-lcdc", },
2429     { .compatible = "marvell,pxa2xx-lcdc", },
2430     { /* sentinel */ }
2431 };
2432 MODULE_DEVICE_TABLE(of, pxafb_of_dev_id);
2433 
2434 static struct platform_driver pxafb_driver = {
2435     .probe      = pxafb_probe,
2436     .remove     = pxafb_remove,
2437     .driver     = {
2438         .name   = "pxa2xx-fb",
2439         .of_match_table = pxafb_of_dev_id,
2440 #ifdef CONFIG_PM
2441         .pm = &pxafb_pm_ops,
2442 #endif
2443     },
2444 };
2445 
2446 static int __init pxafb_init(void)
2447 {
2448     if (pxafb_setup_options())
2449         return -EINVAL;
2450 
2451     return platform_driver_register(&pxafb_driver);
2452 }
2453 
2454 static void __exit pxafb_exit(void)
2455 {
2456     platform_driver_unregister(&pxafb_driver);
2457 }
2458 
2459 module_init(pxafb_init);
2460 module_exit(pxafb_exit);
2461 
2462 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2463 MODULE_LICENSE("GPL");
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