video/fbdev/pxa3xx-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_ARCH_REGS_LCD_H
0003 #define __ASM_ARCH_REGS_LCD_H
0004
0005 /*
0006  * LCD Controller Registers and Bits Definitions
0007  */
0008 #define LCCR0       (0x000) /* LCD Controller Control Register 0 */
0009 #define LCCR1       (0x004) /* LCD Controller Control Register 1 */
0010 #define LCCR2       (0x008) /* LCD Controller Control Register 2 */
0011 #define LCCR3       (0x00C) /* LCD Controller Control Register 3 */
0012 #define LCCR4       (0x010) /* LCD Controller Control Register 4 */
0013 #define LCCR5       (0x014) /* LCD Controller Control Register 5 */
0014 #define LCSR        (0x038) /* LCD Controller Status Register 0 */
0015 #define LCSR1       (0x034) /* LCD Controller Status Register 1 */
0016 #define LIIDR       (0x03C) /* LCD Controller Interrupt ID Register */
0017 #define TMEDRGBR    (0x040) /* TMED RGB Seed Register */
0018 #define TMEDCR      (0x044) /* TMED Control Register */
0019
0020 #define FBR0        (0x020) /* DMA Channel 0 Frame Branch Register */
0021 #define FBR1        (0x024) /* DMA Channel 1 Frame Branch Register */
0022 #define FBR2        (0x028) /* DMA Channel 2 Frame Branch Register */
0023 #define FBR3        (0x02C) /* DMA Channel 2 Frame Branch Register */
0024 #define FBR4        (0x030) /* DMA Channel 2 Frame Branch Register */
0025 #define FBR5        (0x110) /* DMA Channel 2 Frame Branch Register */
0026 #define FBR6        (0x114) /* DMA Channel 2 Frame Branch Register */
0027
0028 #define OVL1C1      (0x050) /* Overlay 1 Control Register 1 */
0029 #define OVL1C2      (0x060) /* Overlay 1 Control Register 2 */
0030 #define OVL2C1      (0x070) /* Overlay 2 Control Register 1 */
0031 #define OVL2C2      (0x080) /* Overlay 2 Control Register 2 */
0032
0033 #define CMDCR       (0x100) /* Command Control Register */
0034 #define PRSR        (0x104) /* Panel Read Status Register */
0035
0036 #define LCCR3_BPP(x)    ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
0037
0038 #define LCCR3_PDFOR_0   (0 << 30)
0039 #define LCCR3_PDFOR_1   (1 << 30)
0040 #define LCCR3_PDFOR_2   (2 << 30)
0041 #define LCCR3_PDFOR_3   (3 << 30)
0042
0043 #define LCCR4_PAL_FOR_0 (0 << 15)
0044 #define LCCR4_PAL_FOR_1 (1 << 15)
0045 #define LCCR4_PAL_FOR_2 (2 << 15)
0046 #define LCCR4_PAL_FOR_3 (3 << 15)
0047 #define LCCR4_PAL_FOR_MASK  (3 << 15)
0048
0049 #define FDADR0      (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
0050 #define FDADR1      (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
0051 #define FDADR2      (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
0052 #define FDADR3      (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
0053 #define FDADR4      (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
0054 #define FDADR5      (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
0055 #define FDADR6      (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
0056
0057 #define LCCR0_ENB   (1 << 0)    /* LCD Controller enable */
0058 #define LCCR0_CMS   (1 << 1)    /* Color/Monochrome Display Select */
0059 #define LCCR0_Color (LCCR0_CMS*0)   /*  Color display */
0060 #define LCCR0_Mono  (LCCR0_CMS*1)   /*  Monochrome display */
0061 #define LCCR0_SDS   (1 << 2)    /* Single/Dual Panel Display Select */
0062 #define LCCR0_Sngl  (LCCR0_SDS*0)   /*  Single panel display */
0063 #define LCCR0_Dual  (LCCR0_SDS*1)   /*  Dual panel display */
0064
0065 #define LCCR0_LDM   (1 << 3)    /* LCD Disable Done Mask */
0066 #define LCCR0_SFM   (1 << 4)    /* Start of frame mask */
0067 #define LCCR0_IUM   (1 << 5)    /* Input FIFO underrun mask */
0068 #define LCCR0_EFM   (1 << 6)    /* End of Frame mask */
0069 #define LCCR0_PAS   (1 << 7)    /* Passive/Active display Select */
0070 #define LCCR0_Pas   (LCCR0_PAS*0)   /*  Passive display (STN) */
0071 #define LCCR0_Act   (LCCR0_PAS*1)   /*  Active display (TFT) */
0072 #define LCCR0_DPD   (1 << 9)    /* Double Pixel Data (monochrome) */
0073 #define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome display */
0074 #define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome display */
0075 #define LCCR0_DIS   (1 << 10)   /* LCD Disable */
0076 #define LCCR0_QDM   (1 << 11)   /* LCD Quick Disable mask */
0077 #define LCCR0_PDD   (0xff << 12)    /* Palette DMA request delay */
0078 #define LCCR0_PDD_S 12
0079 #define LCCR0_BM    (1 << 20)   /* Branch mask */
0080 #define LCCR0_OUM   (1 << 21)   /* Output FIFO underrun mask */
0081 #define LCCR0_LCDT  (1 << 22)   /* LCD panel type */
0082 #define LCCR0_RDSTM (1 << 23)   /* Read status interrupt mask */
0083 #define LCCR0_CMDIM (1 << 24)   /* Command interrupt mask */
0084 #define LCCR0_OUC   (1 << 25)   /* Overlay Underlay control bit */
0085 #define LCCR0_LDDALT    (1 << 26)   /* LDD alternate mapping control */
0086
0087 #define Fld(Size, Shft) (((Size) << 16) + (Shft))
0088 #define FShft(Field)    ((Field) & 0x0000FFFF)
0089
0090 #define LCCR1_PPL   Fld (10, 0) /* Pixels Per Line - 1 */
0091 #define LCCR1_DisWdth(Pixel)    (((Pixel) - 1) << FShft (LCCR1_PPL))
0092
0093 #define LCCR1_HSW   Fld (6, 10) /* Horizontal Synchronization */
0094 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
0095
0096 #define LCCR1_ELW   Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
0097 #define LCCR1_EndLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_ELW))
0098
0099 #define LCCR1_BLW   Fld (8, 24) /* Beginning-of-Line pixel clock */
0100 #define LCCR1_BegLnDel(Tpix)    (((Tpix) - 1) << FShft (LCCR1_BLW))
0101
0102 #define LCCR2_LPP   Fld (10, 0) /* Line Per Panel - 1 */
0103 #define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
0104
0105 #define LCCR2_VSW   Fld (6, 10) /* Vertical Synchronization pulse - 1 */
0106 #define LCCR2_VrtSnchWdth(Tln)  (((Tln) - 1) << FShft (LCCR2_VSW))
0107
0108 #define LCCR2_EFW   Fld (8, 16) /* End-of-Frame line clock Wait */
0109 #define LCCR2_EndFrmDel(Tln)    ((Tln) << FShft (LCCR2_EFW))
0110
0111 #define LCCR2_BFW   Fld (8, 24) /* Beginning-of-Frame line clock */
0112 #define LCCR2_BegFrmDel(Tln)    ((Tln) << FShft (LCCR2_BFW))
0113
0114 #define LCCR3_API   (0xf << 16) /* AC Bias pin trasitions per interrupt */
0115 #define LCCR3_API_S 16
0116 #define LCCR3_VSP   (1 << 20)   /* vertical sync polarity */
0117 #define LCCR3_HSP   (1 << 21)   /* horizontal sync polarity */
0118 #define LCCR3_PCP   (1 << 22)   /* Pixel Clock Polarity (L_PCLK) */
0119 #define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge */
0120 #define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge */
0121
0122 #define LCCR3_OEP   (1 << 23)   /* Output Enable Polarity */
0123 #define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High */
0124 #define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low */
0125
0126 #define LCCR3_DPC   (1 << 27)   /* double pixel clock mode */
0127 #define LCCR3_PCD   Fld (8, 0)  /* Pixel Clock Divisor */
0128 #define LCCR3_PixClkDiv(Div)    (((Div) << FShft (LCCR3_PCD)))
0129
0130 #define LCCR3_ACB   Fld (8, 8)  /* AC Bias */
0131 #define LCCR3_Acb(Acb)  (((Acb) << FShft (LCCR3_ACB)))
0132
0133 #define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  HSP Active High */
0134 #define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  HSP Active Low */
0135
0136 #define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  VSP Active High */
0137 #define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  VSP Active Low */
0138
0139 #define LCCR5_IUM(x)    (1 << ((x) + 23)) /* input underrun mask */
0140 #define LCCR5_BSM(x)    (1 << ((x) + 15)) /* branch mask */
0141 #define LCCR5_EOFM(x)   (1 << ((x) + 7))  /* end of frame mask */
0142 #define LCCR5_SOFM(x)   (1 << ((x) + 0))  /* start of frame mask */
0143
0144 #define LCSR_LDD    (1 << 0)    /* LCD Disable Done */
0145 #define LCSR_SOF    (1 << 1)    /* Start of frame */
0146 #define LCSR_BER    (1 << 2)    /* Bus error */
0147 #define LCSR_ABC    (1 << 3)    /* AC Bias count */
0148 #define LCSR_IUL    (1 << 4)    /* input FIFO underrun Lower panel */
0149 #define LCSR_IUU    (1 << 5)    /* input FIFO underrun Upper panel */
0150 #define LCSR_OU     (1 << 6)    /* output FIFO underrun */
0151 #define LCSR_QD     (1 << 7)    /* quick disable */
0152 #define LCSR_EOF    (1 << 8)    /* end of frame */
0153 #define LCSR_BS     (1 << 9)    /* branch status */
0154 #define LCSR_SINT   (1 << 10)   /* subsequent interrupt */
0155 #define LCSR_RD_ST  (1 << 11)   /* read status */
0156 #define LCSR_CMD_INT    (1 << 12)   /* command interrupt */
0157
0158 #define LCSR1_IU(x) (1 << ((x) + 23)) /* Input FIFO underrun */
0159 #define LCSR1_BS(x) (1 << ((x) + 15)) /* Branch Status */
0160 #define LCSR1_EOF(x)    (1 << ((x) + 7))  /* End of Frame Status */
0161 #define LCSR1_SOF(x)    (1 << ((x) - 1))  /* Start of Frame Status */
0162
0163 #define LDCMD_PAL   (1 << 26)   /* instructs DMA to load palette buffer */
0164
0165 /* overlay control registers */
0166 #define OVLxC1_PPL(x)   ((((x) - 1) & 0x3ff) << 0)  /* Pixels Per Line */
0167 #define OVLxC1_LPO(x)   ((((x) - 1) & 0x3ff) << 10) /* Number of Lines */
0168 #define OVLxC1_BPP(x)   (((x) & 0xf) << 20) /* Bits Per Pixel */
0169 #define OVLxC1_OEN  (1 << 31)       /* Enable bit for Overlay */
0170 #define OVLxC2_XPOS(x)  (((x) & 0x3ff) << 0)    /* Horizontal Position */
0171 #define OVLxC2_YPOS(x)  (((x) & 0x3ff) << 10)   /* Vertical Position */
0172 #define OVL2C2_PFOR(x)  (((x) & 0x7) << 20) /* Pixel Format */
0173
0174 /* smartpanel related */
0175 #define PRSR_DATA(x)    ((x) & 0xff)    /* Panel Data */
0176 #define PRSR_A0     (1 << 8)    /* Read Data Source */
0177 #define PRSR_ST_OK  (1 << 9)    /* Status OK */
0178 #define PRSR_CON_NT (1 << 10)   /* Continue to Next Command */
0179
0180 #endif /* __ASM_ARCH_REGS_LCD_H */