omapfb/dss/video-pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 Texas Instruments Ltd
0004 */
0005
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/sched.h>
0013
0014 #include <video/omapfb_dss.h>
0015
0016 #include "dss.h"
0017 #include "dss_features.h"
0018
0019 struct dss_video_pll {
0020     struct dss_pll pll;
0021
0022     struct device *dev;
0023
0024     void __iomem *clkctrl_base;
0025 };
0026
0027 #define REG_MOD(reg, val, start, end) \
0028     writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
0029
0030 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
0031 {
0032     REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
0033 }
0034
0035 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
0036 {
0037     REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
0038 }
0039
0040 static void dss_dpll_power_enable(struct dss_video_pll *vpll)
0041 {
0042     REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
0043
0044     /*
0045      * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
0046      * so we have to use fixed delay here.
0047      */
0048     msleep(1);
0049 }
0050
0051 static void dss_dpll_power_disable(struct dss_video_pll *vpll)
0052 {
0053     REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
0054 }
0055
0056 static int dss_video_pll_enable(struct dss_pll *pll)
0057 {
0058     struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
0059     int r;
0060
0061     r = dss_runtime_get();
0062     if (r)
0063         return r;
0064
0065     dss_ctrl_pll_enable(pll->id, true);
0066
0067     dss_dpll_enable_scp_clk(vpll);
0068
0069     r = dss_pll_wait_reset_done(pll);
0070     if (r)
0071         goto err_reset;
0072
0073     dss_dpll_power_enable(vpll);
0074
0075     return 0;
0076
0077 err_reset:
0078     dss_dpll_disable_scp_clk(vpll);
0079     dss_ctrl_pll_enable(pll->id, false);
0080     dss_runtime_put();
0081
0082     return r;
0083 }
0084
0085 static void dss_video_pll_disable(struct dss_pll *pll)
0086 {
0087     struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
0088
0089     dss_dpll_power_disable(vpll);
0090
0091     dss_dpll_disable_scp_clk(vpll);
0092
0093     dss_ctrl_pll_enable(pll->id, false);
0094
0095     dss_runtime_put();
0096 }
0097
0098 static const struct dss_pll_ops dss_pll_ops = {
0099     .enable = dss_video_pll_enable,
0100     .disable = dss_video_pll_disable,
0101     .set_config = dss_pll_write_config_type_a,
0102 };
0103
0104 static const struct dss_pll_hw dss_dra7_video_pll_hw = {
0105     .n_max = (1 << 8) - 1,
0106     .m_max = (1 << 12) - 1,
0107     .mX_max = (1 << 5) - 1,
0108     .fint_min = 500000,
0109     .fint_max = 2500000,
0110     .clkdco_max = 1800000000,
0111
0112     .n_msb = 8,
0113     .n_lsb = 1,
0114     .m_msb = 20,
0115     .m_lsb = 9,
0116
0117     .mX_msb[0] = 25,
0118     .mX_lsb[0] = 21,
0119     .mX_msb[1] = 30,
0120     .mX_lsb[1] = 26,
0121
0122     .has_refsel = true,
0123 };
0124
0125 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
0126     struct regulator *regulator)
0127 {
0128     const char * const reg_name[] = { "pll1", "pll2" };
0129     const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
0130     const char * const clkin_name[] = { "video1_clk", "video2_clk" };
0131
0132     struct dss_video_pll *vpll;
0133     void __iomem *pll_base, *clkctrl_base;
0134     struct clk *clk;
0135     struct dss_pll *pll;
0136     int r;
0137
0138     /* PLL CONTROL */
0139
0140     pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);
0141     if (IS_ERR(pll_base)) {
0142         dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id);
0143         return ERR_CAST(pll_base);
0144     }
0145
0146     /* CLOCK CONTROL */
0147
0148     clkctrl_base = devm_platform_ioremap_resource_byname(pdev, clkctrl_name[id]);
0149     if (IS_ERR(clkctrl_base)) {
0150         dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id);
0151         return ERR_CAST(clkctrl_base);
0152     }
0153
0154     /* CLKIN */
0155
0156     clk = devm_clk_get(&pdev->dev, clkin_name[id]);
0157     if (IS_ERR(clk)) {
0158         DSSERR("can't get video pll clkin\n");
0159         return ERR_CAST(clk);
0160     }
0161
0162     vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
0163     if (!vpll)
0164         return ERR_PTR(-ENOMEM);
0165
0166     vpll->dev = &pdev->dev;
0167     vpll->clkctrl_base = clkctrl_base;
0168
0169     pll = &vpll->pll;
0170
0171     pll->name = id == 0 ? "video0" : "video1";
0172     pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
0173     pll->clkin = clk;
0174     pll->regulator = regulator;
0175     pll->base = pll_base;
0176     pll->hw = &dss_dra7_video_pll_hw;
0177     pll->ops = &dss_pll_ops;
0178
0179     r = dss_pll_register(pll);
0180     if (r)
0181         return ERR_PTR(r);
0182
0183     return pll;
0184 }
0185
0186 void dss_video_pll_uninit(struct dss_pll *pll)
0187 {
0188     dss_pll_unregister(pll);
0189 }