omapfb/dss/hdmi_pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * HDMI PLL
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated
0006  */
0007
0008 #define DSS_SUBSYS_NAME "HDMIPLL"
0009
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/err.h>
0013 #include <linux/io.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/clk.h>
0016 #include <linux/seq_file.h>
0017
0018 #include <video/omapfb_dss.h>
0019
0020 #include "dss.h"
0021 #include "hdmi.h"
0022
0023 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
0024 {
0025 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
0026         hdmi_read_reg(pll->base, r))
0027
0028     DUMPPLL(PLLCTRL_PLL_CONTROL);
0029     DUMPPLL(PLLCTRL_PLL_STATUS);
0030     DUMPPLL(PLLCTRL_PLL_GO);
0031     DUMPPLL(PLLCTRL_CFG1);
0032     DUMPPLL(PLLCTRL_CFG2);
0033     DUMPPLL(PLLCTRL_CFG3);
0034     DUMPPLL(PLLCTRL_SSC_CFG1);
0035     DUMPPLL(PLLCTRL_SSC_CFG2);
0036     DUMPPLL(PLLCTRL_CFG4);
0037 }
0038
0039 void hdmi_pll_compute(struct hdmi_pll_data *pll,
0040     unsigned long target_tmds, struct dss_pll_clock_info *pi)
0041 {
0042     unsigned long fint, clkdco, clkout;
0043     unsigned long target_bitclk, target_clkdco;
0044     unsigned long min_dco;
0045     unsigned n, m, mf, m2, sd;
0046     unsigned long clkin;
0047     const struct dss_pll_hw *hw = pll->pll.hw;
0048
0049     clkin = clk_get_rate(pll->pll.clkin);
0050
0051     DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
0052
0053     target_bitclk = target_tmds * 10;
0054
0055     /* Fint */
0056     n = DIV_ROUND_UP(clkin, hw->fint_max);
0057     fint = clkin / n;
0058
0059     /* adjust m2 so that the clkdco will be high enough */
0060     min_dco = roundup(hw->clkdco_min, fint);
0061     m2 = DIV_ROUND_UP(min_dco, target_bitclk);
0062     if (m2 == 0)
0063         m2 = 1;
0064
0065     target_clkdco = target_bitclk * m2;
0066     m = target_clkdco / fint;
0067
0068     clkdco = fint * m;
0069
0070     /* adjust clkdco with fractional mf */
0071     if (WARN_ON(target_clkdco - clkdco > fint))
0072         mf = 0;
0073     else
0074         mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
0075
0076     if (mf > 0)
0077         clkdco += (u32)div_u64((u64)mf * fint, 262144);
0078
0079     clkout = clkdco / m2;
0080
0081     /* sigma-delta */
0082     sd = DIV_ROUND_UP(fint * m, 250000000);
0083
0084     DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
0085         n, m, mf, m2, sd);
0086     DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
0087
0088     pi->n = n;
0089     pi->m = m;
0090     pi->mf = mf;
0091     pi->mX[0] = m2;
0092     pi->sd = sd;
0093
0094     pi->fint = fint;
0095     pi->clkdco = clkdco;
0096     pi->clkout[0] = clkout;
0097 }
0098
0099 static int hdmi_pll_enable(struct dss_pll *dsspll)
0100 {
0101     struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
0102     struct hdmi_wp_data *wp = pll->wp;
0103
0104     dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
0105
0106     return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
0107 }
0108
0109 static void hdmi_pll_disable(struct dss_pll *dsspll)
0110 {
0111     struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
0112     struct hdmi_wp_data *wp = pll->wp;
0113
0114     hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
0115
0116     dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
0117 }
0118
0119 static const struct dss_pll_ops dsi_pll_ops = {
0120     .enable = hdmi_pll_enable,
0121     .disable = hdmi_pll_disable,
0122     .set_config = dss_pll_write_config_type_b,
0123 };
0124
0125 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
0126     .n_max = 255,
0127     .m_min = 20,
0128     .m_max = 4095,
0129     .mX_max = 127,
0130     .fint_min = 500000,
0131     .fint_max = 2500000,
0132
0133     .clkdco_min = 500000000,
0134     .clkdco_low = 1000000000,
0135     .clkdco_max = 2000000000,
0136
0137     .n_msb = 8,
0138     .n_lsb = 1,
0139     .m_msb = 20,
0140     .m_lsb = 9,
0141
0142     .mX_msb[0] = 24,
0143     .mX_lsb[0] = 18,
0144
0145     .has_selfreqdco = true,
0146 };
0147
0148 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
0149     .n_max = 255,
0150     .m_min = 20,
0151     .m_max = 2045,
0152     .mX_max = 127,
0153     .fint_min = 620000,
0154     .fint_max = 2500000,
0155
0156     .clkdco_min = 750000000,
0157     .clkdco_low = 1500000000,
0158     .clkdco_max = 2500000000UL,
0159
0160     .n_msb = 8,
0161     .n_lsb = 1,
0162     .m_msb = 20,
0163     .m_lsb = 9,
0164
0165     .mX_msb[0] = 24,
0166     .mX_lsb[0] = 18,
0167
0168     .has_selfreqdco = true,
0169     .has_refsel = true,
0170 };
0171
0172 static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll)
0173 {
0174     struct dss_pll *pll = &hpll->pll;
0175     struct clk *clk;
0176
0177     clk = devm_clk_get(&pdev->dev, "sys_clk");
0178     if (IS_ERR(clk)) {
0179         DSSERR("can't get sys_clk\n");
0180         return PTR_ERR(clk);
0181     }
0182
0183     pll->name = "hdmi";
0184     pll->id = DSS_PLL_HDMI;
0185     pll->base = hpll->base;
0186     pll->clkin = clk;
0187
0188     switch (omapdss_get_version()) {
0189     case OMAPDSS_VER_OMAP4430_ES1:
0190     case OMAPDSS_VER_OMAP4430_ES2:
0191     case OMAPDSS_VER_OMAP4:
0192         pll->hw = &dss_omap4_hdmi_pll_hw;
0193         break;
0194
0195     case OMAPDSS_VER_OMAP5:
0196     case OMAPDSS_VER_DRA7xx:
0197         pll->hw = &dss_omap5_hdmi_pll_hw;
0198         break;
0199
0200     default:
0201         return -ENODEV;
0202     }
0203
0204     pll->ops = &dsi_pll_ops;
0205     return dss_pll_register(pll);
0206 }
0207
0208 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
0209     struct hdmi_wp_data *wp)
0210 {
0211     int r;
0212
0213     pll->wp = wp;
0214
0215     pll->base = devm_platform_ioremap_resource_byname(pdev, "pll");
0216     if (IS_ERR(pll->base)) {
0217         DSSERR("can't ioremap PLLCTRL\n");
0218         return PTR_ERR(pll->base);
0219     }
0220
0221     r = dsi_init_pll_data(pdev, pll);
0222     if (r) {
0223         DSSERR("failed to init HDMI PLL\n");
0224         return r;
0225     }
0226
0227     return 0;
0228 }
0229
0230 void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
0231 {
0232     struct dss_pll *pll = &hpll->pll;
0233
0234     dss_pll_unregister(pll);
0235 }