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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP5 HDMI CORE IP driver library
0004  *
0005  * Copyright (C) 2014 Texas Instruments Incorporated
0006  *
0007  * Authors:
0008  *  Yong Zhi
0009  *  Mythri pk
0010  *  Archit Taneja <archit@ti.com>
0011  *  Tomi Valkeinen <tomi.valkeinen@ti.com>
0012  */
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/err.h>
0017 #include <linux/io.h>
0018 #include <linux/delay.h>
0019 #include <linux/string.h>
0020 #include <linux/seq_file.h>
0021 #include <drm/drm_edid.h>
0022 #include <sound/asound.h>
0023 #include <sound/asoundef.h>
0024 
0025 #include "hdmi5_core.h"
0026 
0027 /* only 24 bit color depth used for now */
0028 static const struct csc_table csc_table_deepcolor[] = {
0029     /* HDMI_DEEP_COLOR_24BIT */
0030     [0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
0031     /* HDMI_DEEP_COLOR_30BIT */
0032     [1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
0033     /* HDMI_DEEP_COLOR_36BIT */
0034     [2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
0035     /* FULL RANGE */
0036     [3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
0037 };
0038 
0039 static void hdmi_core_ddc_init(struct hdmi_core_data *core)
0040 {
0041     void __iomem *base = core->base;
0042     const unsigned long long iclk = 266000000;  /* DSS L3 ICLK */
0043     const unsigned ss_scl_high = 4600;      /* ns */
0044     const unsigned ss_scl_low = 5400;       /* ns */
0045     const unsigned fs_scl_high = 600;       /* ns */
0046     const unsigned fs_scl_low = 1300;       /* ns */
0047     const unsigned sda_hold = 1000;         /* ns */
0048     const unsigned sfr_div = 10;
0049     unsigned long long sfr;
0050     unsigned v;
0051 
0052     sfr = iclk / sfr_div;   /* SFR_DIV */
0053     sfr /= 1000;        /* SFR clock in kHz */
0054 
0055     /* Reset */
0056     REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
0057     if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
0058                 0, 0, 1) != 1)
0059         DSSERR("HDMI I2CM reset failed\n");
0060 
0061     /* Standard (0) or Fast (1) Mode */
0062     REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
0063 
0064     /* Standard Mode SCL High counter */
0065     v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
0066     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
0067             (v >> 8) & 0xff, 7, 0);
0068     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
0069             v & 0xff, 7, 0);
0070 
0071     /* Standard Mode SCL Low counter */
0072     v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
0073     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
0074             (v >> 8) & 0xff, 7, 0);
0075     REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
0076             v & 0xff, 7, 0);
0077 
0078     /* Fast Mode SCL High Counter */
0079     v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
0080     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
0081             (v >> 8) & 0xff, 7, 0);
0082     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
0083             v & 0xff, 7, 0);
0084 
0085     /* Fast Mode SCL Low Counter */
0086     v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
0087     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
0088             (v >> 8) & 0xff, 7, 0);
0089     REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
0090             v & 0xff, 7, 0);
0091 
0092     /* SDA Hold Time */
0093     v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
0094     REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
0095 
0096     REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
0097     REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
0098 
0099     /* NACK_POL to high */
0100     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
0101 
0102     /* NACK_MASK to unmasked */
0103     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
0104 
0105     /* ARBITRATION_POL to high */
0106     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
0107 
0108     /* ARBITRATION_MASK to unmasked */
0109     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
0110 
0111     /* DONE_POL to high */
0112     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
0113 
0114     /* DONE_MASK to unmasked */
0115     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
0116 }
0117 
0118 static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
0119 {
0120     void __iomem *base = core->base;
0121 
0122     /* Mask I2C interrupts */
0123     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
0124     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
0125     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
0126 }
0127 
0128 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
0129 {
0130     void __iomem *base = core->base;
0131     u8 cur_addr;
0132     char checksum = 0;
0133     const int retries = 1000;
0134     u8 seg_ptr = ext / 2;
0135     u8 edidbase = ((ext % 2) * 0x80);
0136 
0137     REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
0138 
0139     /*
0140      * TODO: We use polling here, although we probably should use proper
0141      * interrupts.
0142      */
0143     for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
0144         int i;
0145 
0146         /* clear ERROR and DONE */
0147         REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
0148 
0149         REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
0150                 edidbase + cur_addr, 7, 0);
0151 
0152         if (seg_ptr)
0153             REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
0154         else
0155             REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
0156 
0157         for (i = 0; i < retries; ++i) {
0158             u32 stat;
0159 
0160             stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
0161 
0162             /* I2CM_ERROR */
0163             if (stat & 1) {
0164                 DSSERR("HDMI I2C Master Error\n");
0165                 return -EIO;
0166             }
0167 
0168             /* I2CM_DONE */
0169             if (stat & (1 << 1))
0170                 break;
0171 
0172             usleep_range(250, 1000);
0173         }
0174 
0175         if (i == retries) {
0176             DSSERR("HDMI I2C timeout reading EDID\n");
0177             return -EIO;
0178         }
0179 
0180         pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
0181         checksum += pedid[cur_addr];
0182     }
0183 
0184     return 0;
0185 
0186 }
0187 
0188 int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
0189 {
0190     int r, n, i;
0191     int max_ext_blocks = (len / 128) - 1;
0192 
0193     if (len < 128)
0194         return -EINVAL;
0195 
0196     hdmi_core_ddc_init(core);
0197 
0198     r = hdmi_core_ddc_edid(core, edid, 0);
0199     if (r)
0200         goto out;
0201 
0202     n = edid[0x7e];
0203 
0204     if (n > max_ext_blocks)
0205         n = max_ext_blocks;
0206 
0207     for (i = 1; i <= n; i++) {
0208         r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
0209         if (r)
0210             goto out;
0211     }
0212 
0213 out:
0214     hdmi_core_ddc_uninit(core);
0215 
0216     return r ? r : len;
0217 }
0218 
0219 void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
0220 {
0221 
0222 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
0223         hdmi_read_reg(core->base, r))
0224 
0225     DUMPCORE(HDMI_CORE_FC_INVIDCONF);
0226     DUMPCORE(HDMI_CORE_FC_INHACTIV0);
0227     DUMPCORE(HDMI_CORE_FC_INHACTIV1);
0228     DUMPCORE(HDMI_CORE_FC_INHBLANK0);
0229     DUMPCORE(HDMI_CORE_FC_INHBLANK1);
0230     DUMPCORE(HDMI_CORE_FC_INVACTIV0);
0231     DUMPCORE(HDMI_CORE_FC_INVACTIV1);
0232     DUMPCORE(HDMI_CORE_FC_INVBLANK);
0233     DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
0234     DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
0235     DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
0236     DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
0237     DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
0238     DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
0239     DUMPCORE(HDMI_CORE_FC_CTRLDUR);
0240     DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
0241     DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
0242     DUMPCORE(HDMI_CORE_FC_CH0PREAM);
0243     DUMPCORE(HDMI_CORE_FC_CH1PREAM);
0244     DUMPCORE(HDMI_CORE_FC_CH2PREAM);
0245     DUMPCORE(HDMI_CORE_FC_AVICONF0);
0246     DUMPCORE(HDMI_CORE_FC_AVICONF1);
0247     DUMPCORE(HDMI_CORE_FC_AVICONF2);
0248     DUMPCORE(HDMI_CORE_FC_AVIVID);
0249     DUMPCORE(HDMI_CORE_FC_PRCONF);
0250 
0251     DUMPCORE(HDMI_CORE_MC_CLKDIS);
0252     DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
0253     DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
0254     DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
0255     DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
0256 
0257     DUMPCORE(HDMI_CORE_I2CM_SLAVE);
0258     DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
0259     DUMPCORE(HDMI_CORE_I2CM_DATAO);
0260     DUMPCORE(HDMI_CORE_I2CM_DATAI);
0261     DUMPCORE(HDMI_CORE_I2CM_OPERATION);
0262     DUMPCORE(HDMI_CORE_I2CM_INT);
0263     DUMPCORE(HDMI_CORE_I2CM_CTLINT);
0264     DUMPCORE(HDMI_CORE_I2CM_DIV);
0265     DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
0266     DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
0267     DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
0268     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
0269     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
0270     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
0271     DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
0272     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
0273     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
0274     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
0275     DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
0276     DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
0277 }
0278 
0279 static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
0280             struct hdmi_config *cfg)
0281 {
0282     DSSDBG("hdmi_core_init\n");
0283 
0284     /* video core */
0285     video_cfg->data_enable_pol = 1; /* It is always 1*/
0286     video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
0287     video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
0288     video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
0289     video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
0290     video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
0291     video_cfg->hblank = cfg->timings.hfp +
0292                 cfg->timings.hbp + cfg->timings.hsw - 1;
0293     video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
0294     video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
0295     video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
0296     video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
0297     video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
0298     video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
0299     video_cfg->vblank = cfg->timings.vsw +
0300                 cfg->timings.vfp + cfg->timings.vbp;
0301     video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
0302     video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
0303 }
0304 
0305 /* DSS_HDMI_CORE_VIDEO_CONFIG */
0306 static void hdmi_core_video_config(struct hdmi_core_data *core,
0307             struct hdmi_core_vid_config *cfg)
0308 {
0309     void __iomem *base = core->base;
0310     unsigned char r = 0;
0311     bool vsync_pol, hsync_pol;
0312 
0313     vsync_pol =
0314         cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
0315     hsync_pol =
0316         cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
0317 
0318     /* Set hsync, vsync and data-enable polarity  */
0319     r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
0320     r = FLD_MOD(r, vsync_pol, 6, 6);
0321     r = FLD_MOD(r, hsync_pol, 5, 5);
0322     r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
0323     r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
0324     r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
0325     hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
0326 
0327     /* set x resolution */
0328     REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
0329             cfg->v_fc_config.timings.x_res >> 8, 4, 0);
0330     REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
0331             cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
0332 
0333     /* set y resolution */
0334     REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
0335             cfg->v_fc_config.timings.y_res >> 8, 4, 0);
0336     REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
0337             cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
0338 
0339     /* set horizontal blanking pixels */
0340     REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
0341     REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
0342 
0343     /* set vertial blanking pixels */
0344     REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
0345 
0346     /* set horizontal sync offset */
0347     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
0348             cfg->v_fc_config.timings.hfp >> 8, 4, 0);
0349     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
0350             cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
0351 
0352     /* set vertical sync offset */
0353     REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
0354             cfg->v_fc_config.timings.vfp, 7, 0);
0355 
0356     /* set horizontal sync pulse width */
0357     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
0358             (cfg->v_fc_config.timings.hsw >> 8), 1, 0);
0359     REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
0360             cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
0361 
0362     /*  set vertical sync pulse width */
0363     REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
0364             cfg->v_fc_config.timings.vsw, 5, 0);
0365 
0366     /* select DVI mode */
0367     REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
0368             cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
0369 }
0370 
0371 static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
0372 {
0373     void __iomem *base = core->base;
0374     int clr_depth = 0;  /* 24 bit color depth */
0375 
0376     /* COLOR_DEPTH */
0377     REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
0378     /* BYPASS_EN */
0379     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
0380     /* PP_EN */
0381     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
0382     /* YCC422_EN */
0383     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
0384     /* PP_STUFFING */
0385     REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
0386     /* YCC422_STUFFING */
0387     REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
0388     /* OUTPUT_SELECTOR */
0389     REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
0390 }
0391 
0392 static void hdmi_core_config_csc(struct hdmi_core_data *core)
0393 {
0394     int clr_depth = 0;  /* 24 bit color depth */
0395 
0396     /* CSC_COLORDEPTH */
0397     REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
0398 }
0399 
0400 static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
0401 {
0402     int video_mapping = 1;  /* for 24 bit color depth */
0403 
0404     /* VIDEO_MAPPING */
0405     REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
0406 }
0407 
0408 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
0409     struct hdmi_avi_infoframe *frame)
0410 {
0411     void __iomem *base = core->base;
0412     u8 data[HDMI_INFOFRAME_SIZE(AVI)];
0413     u8 *ptr;
0414     unsigned y, a, b, s;
0415     unsigned c, m, r;
0416     unsigned itc, ec, q, sc;
0417     unsigned vic;
0418     unsigned yq, cn, pr;
0419 
0420     hdmi_avi_infoframe_pack(frame, data, sizeof(data));
0421 
0422     print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
0423         HDMI_INFOFRAME_SIZE(AVI), false);
0424 
0425     ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
0426 
0427     y = (ptr[0] >> 5) & 0x3;
0428     a = (ptr[0] >> 4) & 0x1;
0429     b = (ptr[0] >> 2) & 0x3;
0430     s = (ptr[0] >> 0) & 0x3;
0431 
0432     c = (ptr[1] >> 6) & 0x3;
0433     m = (ptr[1] >> 4) & 0x3;
0434     r = (ptr[1] >> 0) & 0xf;
0435 
0436     itc = (ptr[2] >> 7) & 0x1;
0437     ec = (ptr[2] >> 4) & 0x7;
0438     q = (ptr[2] >> 2) & 0x3;
0439     sc = (ptr[2] >> 0) & 0x3;
0440 
0441     vic = ptr[3];
0442 
0443     yq = (ptr[4] >> 6) & 0x3;
0444     cn = (ptr[4] >> 4) & 0x3;
0445     pr = (ptr[4] >> 0) & 0xf;
0446 
0447     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
0448         (a << 6) | (s << 4) | (b << 2) | (y << 0));
0449 
0450     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
0451         (c << 6) | (m << 4) | (r << 0));
0452 
0453     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
0454         (itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
0455 
0456     hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
0457 
0458     hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
0459         (yq << 2) | (cn << 0));
0460 
0461     REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
0462 }
0463 
0464 static void hdmi_core_csc_config(struct hdmi_core_data *core,
0465         struct csc_table csc_coeff)
0466 {
0467     void __iomem *base = core->base;
0468 
0469     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
0470     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
0471     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
0472     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
0473     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
0474     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
0475     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
0476     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
0477     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
0478     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
0479     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
0480     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
0481     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
0482     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
0483     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
0484     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
0485     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
0486     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
0487     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
0488     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
0489     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
0490     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
0491     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
0492     REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
0493 
0494     REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
0495 }
0496 
0497 static void hdmi_core_configure_range(struct hdmi_core_data *core)
0498 {
0499     struct csc_table csc_coeff = { 0 };
0500 
0501     /* support limited range with 24 bit color depth for now */
0502     csc_coeff = csc_table_deepcolor[0];
0503 
0504     hdmi_core_csc_config(core, csc_coeff);
0505 }
0506 
0507 static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
0508 {
0509     void __iomem *base = core->base;
0510 
0511     DSSDBG("hdmi_core_enable_video_path\n");
0512 
0513     REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
0514     REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
0515     REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
0516     REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
0517     REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
0518     REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
0519     REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
0520     REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
0521 }
0522 
0523 static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
0524 {
0525     void __iomem *base = core->base;
0526 
0527     /* Master IRQ mask */
0528     REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
0529 
0530     /* Mask all the interrupts in HDMI core */
0531 
0532     REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
0533     REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
0534     REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
0535     REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
0536 
0537     REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
0538     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
0539 
0540     REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
0541 
0542     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
0543     REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
0544     REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
0545 
0546     REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
0547 
0548     REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
0549 
0550     /* Clear all the current interrupt bits */
0551 
0552     REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
0553     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
0554     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
0555     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
0556 
0557     REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
0558 
0559     REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
0560 
0561     REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
0562 
0563     REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
0564 }
0565 
0566 static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
0567 {
0568     /* Unmute interrupts */
0569     REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
0570 }
0571 
0572 int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
0573 {
0574     void __iomem *base = core->base;
0575 
0576     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
0577     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
0578     REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
0579     REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
0580     REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
0581     REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
0582     REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
0583     REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
0584     REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
0585 
0586     return 0;
0587 }
0588 
0589 void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
0590         struct hdmi_config *cfg)
0591 {
0592     struct omap_video_timings video_timing;
0593     struct hdmi_video_format video_format;
0594     struct hdmi_core_vid_config v_core_cfg;
0595 
0596     hdmi_core_mask_interrupts(core);
0597 
0598     hdmi_core_init(&v_core_cfg, cfg);
0599 
0600     hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
0601 
0602     hdmi_wp_video_config_timing(wp, &video_timing);
0603 
0604     /* video config */
0605     video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
0606 
0607     hdmi_wp_video_config_format(wp, &video_format);
0608 
0609     hdmi_wp_video_config_interface(wp, &video_timing);
0610 
0611     /* support limited range with 24 bit color depth for now */
0612     hdmi_core_configure_range(core);
0613     cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
0614 
0615     /*
0616      * configure core video part, set software reset in the core
0617      */
0618     v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
0619 
0620     hdmi_core_video_config(core, &v_core_cfg);
0621 
0622     hdmi_core_config_video_packetizer(core);
0623     hdmi_core_config_csc(core);
0624     hdmi_core_config_video_sampler(core);
0625 
0626     if (cfg->hdmi_dvi_mode == HDMI_HDMI)
0627         hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
0628 
0629     hdmi_core_enable_video_path(core);
0630 
0631     hdmi_core_enable_interrupts(core);
0632 }
0633 
0634 static void hdmi5_core_audio_config(struct hdmi_core_data *core,
0635             struct hdmi_core_audio_config *cfg)
0636 {
0637     void __iomem *base = core->base;
0638     u8 val;
0639 
0640     /* Mute audio before configuring */
0641     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
0642 
0643     /* Set the N parameter */
0644     REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
0645     REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
0646     REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
0647 
0648     /*
0649      * CTS manual mode. Automatic mode is not supported when using audio
0650      * parallel interface.
0651      */
0652     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
0653     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
0654     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
0655     REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
0656 
0657     /* Layout of Audio Sample Packets: 2-channel or multichannels */
0658     if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
0659         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
0660     else
0661         REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
0662 
0663     /* Configure IEC-609580 Validity bits */
0664     /* Channel 0 is valid */
0665     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
0666     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
0667 
0668     if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
0669         val = 1;
0670     else
0671         val = 0;
0672 
0673     /* Channels 1, 2 setting */
0674     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
0675     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
0676     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
0677     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
0678     /* Channel 3 setting */
0679     if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
0680         val = 1;
0681     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
0682     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
0683 
0684     /* Configure IEC-60958 User bits */
0685     /* TODO: should be set by user. */
0686     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
0687 
0688     /* Configure IEC-60958 Channel Status word */
0689     /* CGMSA */
0690     val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
0691     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
0692 
0693     /* Copyright */
0694     val = (cfg->iec60958_cfg->status[0] &
0695             IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
0696     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
0697 
0698     /* Category */
0699     hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
0700         cfg->iec60958_cfg->status[1]);
0701 
0702     /* PCM audio mode */
0703     val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
0704     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
0705 
0706     /* Source number */
0707     val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
0708     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
0709 
0710     /* Channel number right 0  */
0711     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
0712     /* Channel number right 1*/
0713     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
0714     /* Channel number right 2  */
0715     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
0716     /* Channel number right 3*/
0717     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
0718     /* Channel number left 0  */
0719     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
0720     /* Channel number left 1*/
0721     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
0722     /* Channel number left 2  */
0723     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
0724     /* Channel number left 3*/
0725     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
0726 
0727     /* Clock accuracy and sample rate */
0728     hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
0729         cfg->iec60958_cfg->status[3]);
0730 
0731     /* Original sample rate and word length */
0732     hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
0733         cfg->iec60958_cfg->status[4]);
0734 
0735     /* Enable FIFO empty and full interrupts */
0736     REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
0737 
0738     /* Configure GPA */
0739     /* select HBR/SPDIF interfaces */
0740     if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
0741         /* select HBR/SPDIF interfaces */
0742         REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
0743         /* enable two channels in GPA */
0744         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
0745     } else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
0746         /* select HBR/SPDIF interfaces */
0747         REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
0748         /* enable six channels in GPA */
0749         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
0750     } else {
0751         /* select HBR/SPDIF interfaces */
0752         REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
0753         /* enable eight channels in GPA */
0754         REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
0755     }
0756 
0757     /* disable HBR */
0758     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
0759     /* enable PCUV */
0760     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
0761     /* enable GPA FIFO full and empty mask */
0762     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
0763     /* set polarity of GPA FIFO empty interrupts */
0764     REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
0765 
0766     /* unmute audio */
0767     REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
0768 }
0769 
0770 static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
0771      struct snd_cea_861_aud_if *info_aud)
0772 {
0773     void __iomem *base = core->base;
0774 
0775     /* channel count and coding type fields in AUDICONF0 are swapped */
0776     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
0777         (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
0778         (info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
0779 
0780     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
0781     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
0782     hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
0783       (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
0784       (info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
0785 }
0786 
0787 int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
0788             struct omap_dss_audio *audio, u32 pclk)
0789 {
0790     struct hdmi_audio_format audio_format;
0791     struct hdmi_audio_dma audio_dma;
0792     struct hdmi_core_audio_config core_cfg;
0793     int n, cts, channel_count;
0794     unsigned int fs_nr;
0795     bool word_length_16b = false;
0796 
0797     if (!audio || !audio->iec || !audio->cea || !core)
0798         return -EINVAL;
0799 
0800     core_cfg.iec60958_cfg = audio->iec;
0801 
0802     if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
0803         (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
0804             word_length_16b = true;
0805 
0806     /* only 16-bit word length supported atm */
0807     if (!word_length_16b)
0808         return -EINVAL;
0809 
0810     switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
0811     case IEC958_AES3_CON_FS_32000:
0812         fs_nr = 32000;
0813         break;
0814     case IEC958_AES3_CON_FS_44100:
0815         fs_nr = 44100;
0816         break;
0817     case IEC958_AES3_CON_FS_48000:
0818         fs_nr = 48000;
0819         break;
0820     case IEC958_AES3_CON_FS_88200:
0821         fs_nr = 88200;
0822         break;
0823     case IEC958_AES3_CON_FS_96000:
0824         fs_nr = 96000;
0825         break;
0826     case IEC958_AES3_CON_FS_176400:
0827         fs_nr = 176400;
0828         break;
0829     case IEC958_AES3_CON_FS_192000:
0830         fs_nr = 192000;
0831         break;
0832     default:
0833         return -EINVAL;
0834     }
0835 
0836     hdmi_compute_acr(pclk, fs_nr, &n, &cts);
0837     core_cfg.n = n;
0838     core_cfg.cts = cts;
0839 
0840     /* Audio channels settings */
0841     channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
0842                 + 1;
0843 
0844     if (channel_count == 2)
0845         core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
0846     else if (channel_count == 6)
0847         core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
0848     else
0849         core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
0850 
0851     /* DMA settings */
0852     if (word_length_16b)
0853         audio_dma.transfer_size = 0x10;
0854     else
0855         audio_dma.transfer_size = 0x20;
0856     audio_dma.block_size = 0xC0;
0857     audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
0858     audio_dma.fifo_threshold = 0x20; /* in number of samples */
0859 
0860     /* audio FIFO format settings for 16-bit samples*/
0861     audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
0862     audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
0863     audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
0864     audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
0865 
0866     /* only LPCM atm */
0867     audio_format.type = HDMI_AUDIO_TYPE_LPCM;
0868 
0869     /* only allowed option */
0870     audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
0871 
0872     /* disable start/stop signals of IEC 60958 blocks */
0873     audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
0874 
0875     /* configure DMA and audio FIFO format*/
0876     hdmi_wp_audio_config_dma(wp, &audio_dma);
0877     hdmi_wp_audio_config_format(wp, &audio_format);
0878 
0879     /* configure the core */
0880     hdmi5_core_audio_config(core, &core_cfg);
0881 
0882     /* configure CEA 861 audio infoframe */
0883     hdmi5_core_audio_infoframe_cfg(core, audio->cea);
0884 
0885     return 0;
0886 }
0887 
0888 int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
0889 {
0890     core->base = devm_platform_ioremap_resource_byname(pdev, "core");
0891     if (IS_ERR(core->base)) {
0892         DSSERR("can't ioremap HDMI core\n");
0893         return PTR_ERR(core->base);
0894     }
0895 
0896     return 0;
0897 }
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