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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ti_hdmi_4xxx_ip.c
0004  *
0005  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
0006  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
0007  * Authors: Yong Zhi
0008  *  Mythri pk <mythripk@ti.com>
0009  */
0010 
0011 #define DSS_SUBSYS_NAME "HDMICORE"
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/err.h>
0016 #include <linux/io.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/mutex.h>
0019 #include <linux/delay.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/string.h>
0022 #include <linux/seq_file.h>
0023 #include <sound/asound.h>
0024 #include <sound/asoundef.h>
0025 
0026 #include "hdmi4_core.h"
0027 #include "dss_features.h"
0028 
0029 #define HDMI_CORE_AV        0x500
0030 
0031 static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)
0032 {
0033     return core->base + HDMI_CORE_AV;
0034 }
0035 
0036 static int hdmi_core_ddc_init(struct hdmi_core_data *core)
0037 {
0038     void __iomem *base = core->base;
0039 
0040     /* Turn on CLK for DDC */
0041     REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
0042 
0043     /* IN_PROG */
0044     if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
0045         /* Abort transaction */
0046         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
0047         /* IN_PROG */
0048         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
0049                     4, 4, 0) != 0) {
0050             DSSERR("Timeout aborting DDC transaction\n");
0051             return -ETIMEDOUT;
0052         }
0053     }
0054 
0055     /* Clk SCL Devices */
0056     REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
0057 
0058     /* HDMI_CORE_DDC_STATUS_IN_PROG */
0059     if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
0060                 4, 4, 0) != 0) {
0061         DSSERR("Timeout starting SCL clock\n");
0062         return -ETIMEDOUT;
0063     }
0064 
0065     /* Clear FIFO */
0066     REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
0067 
0068     /* HDMI_CORE_DDC_STATUS_IN_PROG */
0069     if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
0070                 4, 4, 0) != 0) {
0071         DSSERR("Timeout clearing DDC fifo\n");
0072         return -ETIMEDOUT;
0073     }
0074 
0075     return 0;
0076 }
0077 
0078 static int hdmi_core_ddc_edid(struct hdmi_core_data *core,
0079         u8 *pedid, int ext)
0080 {
0081     void __iomem *base = core->base;
0082     u32 i;
0083     char checksum;
0084     u32 offset = 0;
0085 
0086     /* HDMI_CORE_DDC_STATUS_IN_PROG */
0087     if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
0088                 4, 4, 0) != 0) {
0089         DSSERR("Timeout waiting DDC to be ready\n");
0090         return -ETIMEDOUT;
0091     }
0092 
0093     if (ext % 2 != 0)
0094         offset = 0x80;
0095 
0096     /* Load Segment Address Register */
0097     REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
0098 
0099     /* Load Slave Address Register */
0100     REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
0101 
0102     /* Load Offset Address Register */
0103     REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
0104 
0105     /* Load Byte Count */
0106     REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
0107     REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
0108 
0109     /* Set DDC_CMD */
0110     if (ext)
0111         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
0112     else
0113         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
0114 
0115     /* HDMI_CORE_DDC_STATUS_BUS_LOW */
0116     if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
0117         DSSERR("I2C Bus Low?\n");
0118         return -EIO;
0119     }
0120     /* HDMI_CORE_DDC_STATUS_NO_ACK */
0121     if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
0122         DSSERR("I2C No Ack\n");
0123         return -EIO;
0124     }
0125 
0126     for (i = 0; i < 0x80; ++i) {
0127         int t;
0128 
0129         /* IN_PROG */
0130         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
0131             DSSERR("operation stopped when reading edid\n");
0132             return -EIO;
0133         }
0134 
0135         t = 0;
0136         /* FIFO_EMPTY */
0137         while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
0138             if (t++ > 10000) {
0139                 DSSERR("timeout reading edid\n");
0140                 return -ETIMEDOUT;
0141             }
0142             udelay(1);
0143         }
0144 
0145         pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
0146     }
0147 
0148     checksum = 0;
0149     for (i = 0; i < 0x80; ++i)
0150         checksum += pedid[i];
0151 
0152     if (checksum != 0) {
0153         DSSERR("E-EDID checksum failed!!\n");
0154         return -EIO;
0155     }
0156 
0157     return 0;
0158 }
0159 
0160 int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
0161 {
0162     int r, l;
0163 
0164     if (len < 128)
0165         return -EINVAL;
0166 
0167     r = hdmi_core_ddc_init(core);
0168     if (r)
0169         return r;
0170 
0171     r = hdmi_core_ddc_edid(core, edid, 0);
0172     if (r)
0173         return r;
0174 
0175     l = 128;
0176 
0177     if (len >= 128 * 2 && edid[0x7e] > 0) {
0178         r = hdmi_core_ddc_edid(core, edid + 0x80, 1);
0179         if (r)
0180             return r;
0181         l += 128;
0182     }
0183 
0184     return l;
0185 }
0186 
0187 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
0188 {
0189     DSSDBG("Enter hdmi_core_init\n");
0190 
0191     /* video core */
0192     video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
0193     video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
0194     video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
0195     video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
0196     video_cfg->hdmi_dvi = HDMI_DVI;
0197     video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
0198 }
0199 
0200 static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
0201 {
0202     DSSDBG("Enter hdmi_core_powerdown_disable\n");
0203     REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
0204 }
0205 
0206 static void hdmi_core_swreset_release(struct hdmi_core_data *core)
0207 {
0208     DSSDBG("Enter hdmi_core_swreset_release\n");
0209     REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0);
0210 }
0211 
0212 static void hdmi_core_swreset_assert(struct hdmi_core_data *core)
0213 {
0214     DSSDBG("Enter hdmi_core_swreset_assert\n");
0215     REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0);
0216 }
0217 
0218 /* HDMI_CORE_VIDEO_CONFIG */
0219 static void hdmi_core_video_config(struct hdmi_core_data *core,
0220                 struct hdmi_core_video_config *cfg)
0221 {
0222     u32 r = 0;
0223     void __iomem *core_sys_base = core->base;
0224     void __iomem *core_av_base = hdmi_av_base(core);
0225 
0226     /* sys_ctrl1 default configuration not tunable */
0227     r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
0228     r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
0229     r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
0230     r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2);
0231     r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1);
0232     hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r);
0233 
0234     REG_FLD_MOD(core_sys_base,
0235             HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
0236 
0237     /* Vid_Mode */
0238     r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
0239 
0240     /* dither truncation configuration */
0241     if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
0242         r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
0243         r = FLD_MOD(r, 1, 5, 5);
0244     } else {
0245         r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
0246         r = FLD_MOD(r, 0, 5, 5);
0247     }
0248     hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
0249 
0250     /* HDMI_Ctrl */
0251     r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
0252     r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
0253     r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
0254     r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
0255     hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r);
0256 
0257     /* TMDS_CTRL */
0258     REG_FLD_MOD(core_sys_base,
0259             HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
0260 }
0261 
0262 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
0263     struct hdmi_avi_infoframe *frame)
0264 {
0265     void __iomem *av_base = hdmi_av_base(core);
0266     u8 data[HDMI_INFOFRAME_SIZE(AVI)];
0267     int i;
0268 
0269     hdmi_avi_infoframe_pack(frame, data, sizeof(data));
0270 
0271     print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
0272         HDMI_INFOFRAME_SIZE(AVI), false);
0273 
0274     for (i = 0; i < sizeof(data); ++i) {
0275         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4,
0276             data[i]);
0277     }
0278 }
0279 
0280 static void hdmi_core_av_packet_config(struct hdmi_core_data *core,
0281         struct hdmi_core_packet_enable_repeat repeat_cfg)
0282 {
0283     /* enable/repeat the infoframe */
0284     hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1,
0285         (repeat_cfg.audio_pkt << 5) |
0286         (repeat_cfg.audio_pkt_repeat << 4) |
0287         (repeat_cfg.avi_infoframe << 1) |
0288         (repeat_cfg.avi_infoframe_repeat));
0289 
0290     /* enable/repeat the packet */
0291     hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2,
0292         (repeat_cfg.gen_cntrl_pkt << 3) |
0293         (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
0294         (repeat_cfg.generic_pkt << 1) |
0295         (repeat_cfg.generic_pkt_repeat));
0296 }
0297 
0298 void hdmi4_configure(struct hdmi_core_data *core,
0299     struct hdmi_wp_data *wp, struct hdmi_config *cfg)
0300 {
0301     /* HDMI */
0302     struct omap_video_timings video_timing;
0303     struct hdmi_video_format video_format;
0304     /* HDMI core */
0305     struct hdmi_core_video_config v_core_cfg;
0306     struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 };
0307 
0308     hdmi_core_init(&v_core_cfg);
0309 
0310     hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
0311 
0312     hdmi_wp_video_config_timing(wp, &video_timing);
0313 
0314     /* video config */
0315     video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
0316 
0317     hdmi_wp_video_config_format(wp, &video_format);
0318 
0319     hdmi_wp_video_config_interface(wp, &video_timing);
0320 
0321     /*
0322      * configure core video part
0323      * set software reset in the core
0324      */
0325     hdmi_core_swreset_assert(core);
0326 
0327     /* power down off */
0328     hdmi_core_powerdown_disable(core);
0329 
0330     v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
0331     v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
0332 
0333     hdmi_core_video_config(core, &v_core_cfg);
0334 
0335     /* release software reset in the core */
0336     hdmi_core_swreset_release(core);
0337 
0338     if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
0339         hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
0340 
0341         /* enable/repeat the infoframe */
0342         repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
0343         repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
0344         /* wakeup */
0345         repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
0346         repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
0347     }
0348 
0349     hdmi_core_av_packet_config(core, repeat_cfg);
0350 }
0351 
0352 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s)
0353 {
0354     int i;
0355 
0356 #define CORE_REG(i, name) name(i)
0357 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
0358         hdmi_read_reg(core->base, r))
0359 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
0360         hdmi_read_reg(hdmi_av_base(core), r))
0361 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
0362         (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
0363         hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
0364 
0365     DUMPCORE(HDMI_CORE_SYS_VND_IDL);
0366     DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
0367     DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
0368     DUMPCORE(HDMI_CORE_SYS_DEV_REV);
0369     DUMPCORE(HDMI_CORE_SYS_SRST);
0370     DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
0371     DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
0372     DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);
0373     DUMPCORE(HDMI_CORE_SYS_DE_DLY);
0374     DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
0375     DUMPCORE(HDMI_CORE_SYS_DE_TOP);
0376     DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
0377     DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
0378     DUMPCORE(HDMI_CORE_SYS_DE_LINL);
0379     DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
0380     DUMPCORE(HDMI_CORE_SYS_HRES_L);
0381     DUMPCORE(HDMI_CORE_SYS_HRES_H);
0382     DUMPCORE(HDMI_CORE_SYS_VRES_L);
0383     DUMPCORE(HDMI_CORE_SYS_VRES_H);
0384     DUMPCORE(HDMI_CORE_SYS_IADJUST);
0385     DUMPCORE(HDMI_CORE_SYS_POLDETECT);
0386     DUMPCORE(HDMI_CORE_SYS_HWIDTH1);
0387     DUMPCORE(HDMI_CORE_SYS_HWIDTH2);
0388     DUMPCORE(HDMI_CORE_SYS_VWIDTH);
0389     DUMPCORE(HDMI_CORE_SYS_VID_CTRL);
0390     DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
0391     DUMPCORE(HDMI_CORE_SYS_VID_MODE);
0392     DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
0393     DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);
0394     DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
0395     DUMPCORE(HDMI_CORE_SYS_DC_HEADER);
0396     DUMPCORE(HDMI_CORE_SYS_VID_DITHER);
0397     DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);
0398     DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);
0399     DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);
0400     DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);
0401     DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);
0402     DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);
0403     DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);
0404     DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);
0405     DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);
0406     DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);
0407     DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);
0408     DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);
0409     DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);
0410     DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);
0411     DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);
0412     DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);
0413     DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);
0414     DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);
0415     DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);
0416     DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);
0417     DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);
0418     DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);
0419     DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);
0420     DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);
0421     DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);
0422     DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
0423     DUMPCORE(HDMI_CORE_SYS_INTR1);
0424     DUMPCORE(HDMI_CORE_SYS_INTR2);
0425     DUMPCORE(HDMI_CORE_SYS_INTR3);
0426     DUMPCORE(HDMI_CORE_SYS_INTR4);
0427     DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);
0428     DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);
0429     DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);
0430     DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);
0431     DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);
0432     DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
0433 
0434     DUMPCORE(HDMI_CORE_DDC_ADDR);
0435     DUMPCORE(HDMI_CORE_DDC_SEGM);
0436     DUMPCORE(HDMI_CORE_DDC_OFFSET);
0437     DUMPCORE(HDMI_CORE_DDC_COUNT1);
0438     DUMPCORE(HDMI_CORE_DDC_COUNT2);
0439     DUMPCORE(HDMI_CORE_DDC_STATUS);
0440     DUMPCORE(HDMI_CORE_DDC_CMD);
0441     DUMPCORE(HDMI_CORE_DDC_DATA);
0442 
0443     DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
0444     DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
0445     DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
0446     DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
0447     DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
0448     DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
0449     DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
0450     DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
0451     DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
0452     DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
0453     DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
0454     DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
0455     DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
0456     DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
0457     DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
0458     DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
0459     DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
0460     DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
0461     DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
0462     DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
0463     DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
0464     DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
0465     DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
0466     DUMPCOREAV(HDMI_CORE_AV_ASRC);
0467     DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
0468     DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
0469     DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
0470     DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
0471     DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
0472     DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
0473     DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
0474     DUMPCOREAV(HDMI_CORE_AV_DPD);
0475     DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
0476     DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
0477     DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
0478     DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
0479     DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
0480     DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
0481 
0482     for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
0483         DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
0484 
0485     DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
0486     DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
0487     DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
0488     DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
0489 
0490     for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
0491         DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
0492 
0493     DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
0494     DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
0495     DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
0496     DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
0497 
0498     for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
0499         DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
0500 
0501     DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
0502     DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
0503     DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
0504     DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
0505 
0506     for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
0507         DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
0508 
0509     for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
0510         DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
0511 
0512     DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
0513 
0514     for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
0515         DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
0516 
0517     DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
0518 }
0519 
0520 static void hdmi_core_audio_config(struct hdmi_core_data *core,
0521                     struct hdmi_core_audio_config *cfg)
0522 {
0523     u32 r;
0524     void __iomem *av_base = hdmi_av_base(core);
0525 
0526     /*
0527      * Parameters for generation of Audio Clock Recovery packets
0528      */
0529     REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
0530     REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
0531     REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
0532 
0533     if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
0534         REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
0535         REG_FLD_MOD(av_base,
0536                 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
0537         REG_FLD_MOD(av_base,
0538                 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
0539     } else {
0540         REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
0541                 cfg->aud_par_busclk, 7, 0);
0542         REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
0543                 (cfg->aud_par_busclk >> 8), 7, 0);
0544         REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
0545                 (cfg->aud_par_busclk >> 16), 7, 0);
0546     }
0547 
0548     /* Set ACR clock divisor */
0549     REG_FLD_MOD(av_base,
0550             HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
0551 
0552     r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
0553     /*
0554      * Use TMDS clock for ACR packets. For devices that use
0555      * the MCLK, this is the first part of the MCLK initialization.
0556      */
0557     r = FLD_MOD(r, 0, 2, 2);
0558 
0559     r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
0560     r = FLD_MOD(r, cfg->cts_mode, 0, 0);
0561     hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
0562 
0563     /* For devices using MCLK, this completes its initialization. */
0564     if (cfg->use_mclk)
0565         REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
0566 
0567     /* Override of SPDIF sample frequency with value in I2S_CHST4 */
0568     REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
0569                         cfg->fs_override, 1, 1);
0570 
0571     /*
0572      * Set IEC-60958-3 channel status word. It is passed to the IP
0573      * just as it is received. The user of the driver is responsible
0574      * for its contents.
0575      */
0576     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
0577                cfg->iec60958_cfg->status[0]);
0578     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
0579                cfg->iec60958_cfg->status[1]);
0580     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
0581                cfg->iec60958_cfg->status[2]);
0582     /* yes, this is correct: status[3] goes to CHST4 register */
0583     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
0584                cfg->iec60958_cfg->status[3]);
0585     /* yes, this is correct: status[4] goes to CHST5 register */
0586     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
0587                cfg->iec60958_cfg->status[4]);
0588 
0589     /* set I2S parameters */
0590     r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
0591     r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
0592     r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
0593     r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
0594     r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
0595     r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
0596     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
0597 
0598     REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
0599             cfg->i2s_cfg.in_length_bits, 3, 0);
0600 
0601     /* Audio channels and mode parameters */
0602     REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
0603     r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
0604     r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
0605     r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
0606     r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
0607     r = FLD_MOD(r, cfg->en_spdif, 1, 1);
0608     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
0609 
0610     /* Audio channel mappings */
0611     /* TODO: Make channel mapping dynamic. For now, map channels
0612      * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
0613      * HDMI speaker order is different. See CEA-861 Section 6.6.2.
0614      */
0615     hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
0616     REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
0617 }
0618 
0619 static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core,
0620         struct snd_cea_861_aud_if *info_aud)
0621 {
0622     u8 sum = 0, checksum = 0;
0623     void __iomem *av_base = hdmi_av_base(core);
0624 
0625     /*
0626      * Set audio info frame type, version and length as
0627      * described in HDMI 1.4a Section 8.2.2 specification.
0628      * Checksum calculation is defined in Section 5.3.5.
0629      */
0630     hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
0631     hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
0632     hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
0633     sum += 0x84 + 0x001 + 0x00a;
0634 
0635     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
0636                info_aud->db1_ct_cc);
0637     sum += info_aud->db1_ct_cc;
0638 
0639     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
0640                info_aud->db2_sf_ss);
0641     sum += info_aud->db2_sf_ss;
0642 
0643     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
0644     sum += info_aud->db3;
0645 
0646     /*
0647      * The OMAP HDMI IP requires to use the 8-channel channel code when
0648      * transmitting more than two channels.
0649      */
0650     if (info_aud->db4_ca != 0x00)
0651         info_aud->db4_ca = 0x13;
0652 
0653     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
0654     sum += info_aud->db4_ca;
0655 
0656     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
0657                info_aud->db5_dminh_lsv);
0658     sum += info_aud->db5_dminh_lsv;
0659 
0660     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
0661     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
0662     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
0663     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
0664     hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
0665 
0666     checksum = 0x100 - sum;
0667     hdmi_write_reg(av_base,
0668                     HDMI_CORE_AV_AUDIO_CHSUM, checksum);
0669 
0670     /*
0671      * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
0672      * is available.
0673      */
0674 }
0675 
0676 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
0677         struct omap_dss_audio *audio, u32 pclk)
0678 {
0679     struct hdmi_audio_format audio_format;
0680     struct hdmi_audio_dma audio_dma;
0681     struct hdmi_core_audio_config acore;
0682     int n, cts, channel_count;
0683     unsigned int fs_nr;
0684     bool word_length_16b = false;
0685 
0686     if (!audio || !audio->iec || !audio->cea || !core)
0687         return -EINVAL;
0688 
0689     acore.iec60958_cfg = audio->iec;
0690     /*
0691      * In the IEC-60958 status word, check if the audio sample word length
0692      * is 16-bit as several optimizations can be performed in such case.
0693      */
0694     if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
0695         if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
0696             word_length_16b = true;
0697 
0698     /* I2S configuration. See Phillips' specification */
0699     if (word_length_16b)
0700         acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
0701     else
0702         acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
0703     /*
0704      * The I2S input word length is twice the length given in the IEC-60958
0705      * status word. If the word size is greater than
0706      * 20 bits, increment by one.
0707      */
0708     acore.i2s_cfg.in_length_bits = audio->iec->status[4]
0709         & IEC958_AES4_CON_WORDLEN;
0710     if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
0711         acore.i2s_cfg.in_length_bits++;
0712     acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
0713     acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
0714     acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
0715     acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
0716 
0717     /* convert sample frequency to a number */
0718     switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
0719     case IEC958_AES3_CON_FS_32000:
0720         fs_nr = 32000;
0721         break;
0722     case IEC958_AES3_CON_FS_44100:
0723         fs_nr = 44100;
0724         break;
0725     case IEC958_AES3_CON_FS_48000:
0726         fs_nr = 48000;
0727         break;
0728     case IEC958_AES3_CON_FS_88200:
0729         fs_nr = 88200;
0730         break;
0731     case IEC958_AES3_CON_FS_96000:
0732         fs_nr = 96000;
0733         break;
0734     case IEC958_AES3_CON_FS_176400:
0735         fs_nr = 176400;
0736         break;
0737     case IEC958_AES3_CON_FS_192000:
0738         fs_nr = 192000;
0739         break;
0740     default:
0741         return -EINVAL;
0742     }
0743 
0744     hdmi_compute_acr(pclk, fs_nr, &n, &cts);
0745 
0746     /* Audio clock regeneration settings */
0747     acore.n = n;
0748     acore.cts = cts;
0749     if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
0750         acore.aud_par_busclk = 0;
0751         acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
0752         acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
0753     } else {
0754         acore.aud_par_busclk = (((128 * 31) - 1) << 8);
0755         acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
0756         acore.use_mclk = true;
0757     }
0758 
0759     if (acore.use_mclk)
0760         acore.mclk_mode = HDMI_AUDIO_MCLK_128FS;
0761 
0762     /* Audio channels settings */
0763     channel_count = (audio->cea->db1_ct_cc &
0764              CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
0765 
0766     switch (channel_count) {
0767     case 2:
0768         audio_format.active_chnnls_msk = 0x03;
0769         break;
0770     case 3:
0771         audio_format.active_chnnls_msk = 0x07;
0772         break;
0773     case 4:
0774         audio_format.active_chnnls_msk = 0x0f;
0775         break;
0776     case 5:
0777         audio_format.active_chnnls_msk = 0x1f;
0778         break;
0779     case 6:
0780         audio_format.active_chnnls_msk = 0x3f;
0781         break;
0782     case 7:
0783         audio_format.active_chnnls_msk = 0x7f;
0784         break;
0785     case 8:
0786         audio_format.active_chnnls_msk = 0xff;
0787         break;
0788     default:
0789         return -EINVAL;
0790     }
0791 
0792     /*
0793      * the HDMI IP needs to enable four stereo channels when transmitting
0794      * more than 2 audio channels.  Similarly, the channel count in the
0795      * Audio InfoFrame has to match the sample_present bits (some channels
0796      * are padded with zeroes)
0797      */
0798     if (channel_count == 2) {
0799         audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
0800         acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
0801         acore.layout = HDMI_AUDIO_LAYOUT_2CH;
0802     } else {
0803         audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
0804         acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
0805                 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
0806                 HDMI_AUDIO_I2S_SD3_EN;
0807         acore.layout = HDMI_AUDIO_LAYOUT_8CH;
0808         audio->cea->db1_ct_cc = 7;
0809     }
0810 
0811     acore.en_spdif = false;
0812     /* use sample frequency from channel status word */
0813     acore.fs_override = true;
0814     /* enable ACR packets */
0815     acore.en_acr_pkt = true;
0816     /* disable direct streaming digital audio */
0817     acore.en_dsd_audio = false;
0818     /* use parallel audio interface */
0819     acore.en_parallel_aud_input = true;
0820 
0821     /* DMA settings */
0822     if (word_length_16b)
0823         audio_dma.transfer_size = 0x10;
0824     else
0825         audio_dma.transfer_size = 0x20;
0826     audio_dma.block_size = 0xC0;
0827     audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
0828     audio_dma.fifo_threshold = 0x20; /* in number of samples */
0829 
0830     /* audio FIFO format settings */
0831     if (word_length_16b) {
0832         audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
0833         audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
0834         audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
0835     } else {
0836         audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
0837         audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
0838         audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
0839     }
0840     audio_format.type = HDMI_AUDIO_TYPE_LPCM;
0841     audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
0842     /* disable start/stop signals of IEC 60958 blocks */
0843     audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
0844 
0845     /* configure DMA and audio FIFO format*/
0846     hdmi_wp_audio_config_dma(wp, &audio_dma);
0847     hdmi_wp_audio_config_format(wp, &audio_format);
0848 
0849     /* configure the core*/
0850     hdmi_core_audio_config(core, &acore);
0851 
0852     /* configure CEA 861 audio infoframe*/
0853     hdmi_core_audio_infoframe_cfg(core, audio->cea);
0854 
0855     return 0;
0856 }
0857 
0858 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
0859 {
0860     REG_FLD_MOD(hdmi_av_base(core),
0861             HDMI_CORE_AV_AUD_MODE, true, 0, 0);
0862 
0863     hdmi_wp_audio_core_req_enable(wp, true);
0864 
0865     return 0;
0866 }
0867 
0868 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
0869 {
0870     REG_FLD_MOD(hdmi_av_base(core),
0871             HDMI_CORE_AV_AUD_MODE, false, 0, 0);
0872 
0873     hdmi_wp_audio_core_req_enable(wp, false);
0874 }
0875 
0876 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
0877 {
0878     core->base = devm_platform_ioremap_resource_byname(pdev, "core");
0879     if (IS_ERR(core->base)) {
0880         DSSERR("can't ioremap CORE\n");
0881         return PTR_ERR(core->base);
0882     }
0883 
0884     return 0;
0885 }
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