omapfb/dss/hdmi.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * HDMI driver definition for TI OMAP4 Processor.
0004  *
0005  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #ifndef _HDMI_H
0009 #define _HDMI_H
0010
0011 #include <linux/delay.h>
0012 #include <linux/io.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/hdmi.h>
0015 #include <video/omapfb_dss.h>
0016 #include <sound/omap-hdmi-audio.h>
0017
0018 #include "dss.h"
0019
0020 /* HDMI Wrapper */
0021
0022 #define HDMI_WP_REVISION            0x0
0023 #define HDMI_WP_SYSCONFIG           0x10
0024 #define HDMI_WP_IRQSTATUS_RAW           0x24
0025 #define HDMI_WP_IRQSTATUS           0x28
0026 #define HDMI_WP_IRQENABLE_SET           0x2C
0027 #define HDMI_WP_IRQENABLE_CLR           0x30
0028 #define HDMI_WP_IRQWAKEEN           0x34
0029 #define HDMI_WP_PWR_CTRL            0x40
0030 #define HDMI_WP_DEBOUNCE            0x44
0031 #define HDMI_WP_VIDEO_CFG           0x50
0032 #define HDMI_WP_VIDEO_SIZE          0x60
0033 #define HDMI_WP_VIDEO_TIMING_H          0x68
0034 #define HDMI_WP_VIDEO_TIMING_V          0x6C
0035 #define HDMI_WP_CLK             0x70
0036 #define HDMI_WP_AUDIO_CFG           0x80
0037 #define HDMI_WP_AUDIO_CFG2          0x84
0038 #define HDMI_WP_AUDIO_CTRL          0x88
0039 #define HDMI_WP_AUDIO_DATA          0x8C
0040
0041 /* HDMI WP IRQ flags */
0042 #define HDMI_IRQ_CORE               (1 << 0)
0043 #define HDMI_IRQ_OCP_TIMEOUT            (1 << 4)
0044 #define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW       (1 << 8)
0045 #define HDMI_IRQ_AUDIO_FIFO_OVERFLOW        (1 << 9)
0046 #define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ      (1 << 10)
0047 #define HDMI_IRQ_VIDEO_VSYNC            (1 << 16)
0048 #define HDMI_IRQ_VIDEO_FRAME_DONE       (1 << 17)
0049 #define HDMI_IRQ_PHY_LINE5V_ASSERT      (1 << 24)
0050 #define HDMI_IRQ_LINK_CONNECT           (1 << 25)
0051 #define HDMI_IRQ_LINK_DISCONNECT        (1 << 26)
0052 #define HDMI_IRQ_PLL_LOCK           (1 << 29)
0053 #define HDMI_IRQ_PLL_UNLOCK         (1 << 30)
0054 #define HDMI_IRQ_PLL_RECAL          (1 << 31)
0055
0056 /* HDMI PLL */
0057
0058 #define PLLCTRL_PLL_CONTROL         0x0
0059 #define PLLCTRL_PLL_STATUS          0x4
0060 #define PLLCTRL_PLL_GO              0x8
0061 #define PLLCTRL_CFG1                0xC
0062 #define PLLCTRL_CFG2                0x10
0063 #define PLLCTRL_CFG3                0x14
0064 #define PLLCTRL_SSC_CFG1            0x18
0065 #define PLLCTRL_SSC_CFG2            0x1C
0066 #define PLLCTRL_CFG4                0x20
0067
0068 /* HDMI PHY */
0069
0070 #define HDMI_TXPHY_TX_CTRL          0x0
0071 #define HDMI_TXPHY_DIGITAL_CTRL         0x4
0072 #define HDMI_TXPHY_POWER_CTRL           0x8
0073 #define HDMI_TXPHY_PAD_CFG_CTRL         0xC
0074 #define HDMI_TXPHY_BIST_CONTROL         0x1C
0075
0076 enum hdmi_pll_pwr {
0077     HDMI_PLLPWRCMD_ALLOFF = 0,
0078     HDMI_PLLPWRCMD_PLLONLY = 1,
0079     HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
0080     HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
0081 };
0082
0083 enum hdmi_phy_pwr {
0084     HDMI_PHYPWRCMD_OFF = 0,
0085     HDMI_PHYPWRCMD_LDOON = 1,
0086     HDMI_PHYPWRCMD_TXON = 2
0087 };
0088
0089 enum hdmi_core_hdmi_dvi {
0090     HDMI_DVI = 0,
0091     HDMI_HDMI = 1
0092 };
0093
0094 enum hdmi_packing_mode {
0095     HDMI_PACK_10b_RGB_YUV444 = 0,
0096     HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
0097     HDMI_PACK_20b_YUV422 = 2,
0098     HDMI_PACK_ALREADYPACKED = 7
0099 };
0100
0101 enum hdmi_stereo_channels {
0102     HDMI_AUDIO_STEREO_NOCHANNELS = 0,
0103     HDMI_AUDIO_STEREO_ONECHANNEL = 1,
0104     HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
0105     HDMI_AUDIO_STEREO_THREECHANNELS = 3,
0106     HDMI_AUDIO_STEREO_FOURCHANNELS = 4
0107 };
0108
0109 enum hdmi_audio_type {
0110     HDMI_AUDIO_TYPE_LPCM = 0,
0111     HDMI_AUDIO_TYPE_IEC = 1
0112 };
0113
0114 enum hdmi_audio_justify {
0115     HDMI_AUDIO_JUSTIFY_LEFT = 0,
0116     HDMI_AUDIO_JUSTIFY_RIGHT = 1
0117 };
0118
0119 enum hdmi_audio_sample_order {
0120     HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
0121     HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
0122 };
0123
0124 enum hdmi_audio_samples_perword {
0125     HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
0126     HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
0127 };
0128
0129 enum hdmi_audio_sample_size_omap {
0130     HDMI_AUDIO_SAMPLE_16BITS = 0,
0131     HDMI_AUDIO_SAMPLE_24BITS = 1
0132 };
0133
0134 enum hdmi_audio_transf_mode {
0135     HDMI_AUDIO_TRANSF_DMA = 0,
0136     HDMI_AUDIO_TRANSF_IRQ = 1
0137 };
0138
0139 enum hdmi_audio_blk_strt_end_sig {
0140     HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
0141     HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
0142 };
0143
0144 enum hdmi_core_audio_layout {
0145     HDMI_AUDIO_LAYOUT_2CH = 0,
0146     HDMI_AUDIO_LAYOUT_8CH = 1,
0147     HDMI_AUDIO_LAYOUT_6CH = 2
0148 };
0149
0150 enum hdmi_core_cts_mode {
0151     HDMI_AUDIO_CTS_MODE_HW = 0,
0152     HDMI_AUDIO_CTS_MODE_SW = 1
0153 };
0154
0155 enum hdmi_audio_mclk_mode {
0156     HDMI_AUDIO_MCLK_128FS = 0,
0157     HDMI_AUDIO_MCLK_256FS = 1,
0158     HDMI_AUDIO_MCLK_384FS = 2,
0159     HDMI_AUDIO_MCLK_512FS = 3,
0160     HDMI_AUDIO_MCLK_768FS = 4,
0161     HDMI_AUDIO_MCLK_1024FS = 5,
0162     HDMI_AUDIO_MCLK_1152FS = 6,
0163     HDMI_AUDIO_MCLK_192FS = 7
0164 };
0165
0166 struct hdmi_video_format {
0167     enum hdmi_packing_mode  packing_mode;
0168     u32         y_res;  /* Line per panel */
0169     u32         x_res;  /* pixel per line */
0170 };
0171
0172 struct hdmi_config {
0173     struct omap_video_timings timings;
0174     struct hdmi_avi_infoframe infoframe;
0175     enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
0176 };
0177
0178 struct hdmi_audio_format {
0179     enum hdmi_stereo_channels       stereo_channels;
0180     u8                  active_chnnls_msk;
0181     enum hdmi_audio_type            type;
0182     enum hdmi_audio_justify         justification;
0183     enum hdmi_audio_sample_order        sample_order;
0184     enum hdmi_audio_samples_perword     samples_per_word;
0185     enum hdmi_audio_sample_size_omap    sample_size;
0186     enum hdmi_audio_blk_strt_end_sig    en_sig_blk_strt_end;
0187 };
0188
0189 struct hdmi_audio_dma {
0190     u8              transfer_size;
0191     u8              block_size;
0192     enum hdmi_audio_transf_mode mode;
0193     u16             fifo_threshold;
0194 };
0195
0196 struct hdmi_core_audio_i2s_config {
0197     u8 in_length_bits;
0198     u8 justification;
0199     u8 sck_edge_mode;
0200     u8 vbit;
0201     u8 direction;
0202     u8 shift;
0203     u8 active_sds;
0204 };
0205
0206 struct hdmi_core_audio_config {
0207     struct hdmi_core_audio_i2s_config   i2s_cfg;
0208     struct snd_aes_iec958           *iec60958_cfg;
0209     bool                    fs_override;
0210     u32                 n;
0211     u32                 cts;
0212     u32                 aud_par_busclk;
0213     enum hdmi_core_audio_layout     layout;
0214     enum hdmi_core_cts_mode         cts_mode;
0215     bool                    use_mclk;
0216     enum hdmi_audio_mclk_mode       mclk_mode;
0217     bool                    en_acr_pkt;
0218     bool                    en_dsd_audio;
0219     bool                    en_parallel_aud_input;
0220     bool                    en_spdif;
0221 };
0222
0223 struct hdmi_wp_data {
0224     void __iomem *base;
0225     phys_addr_t phys_base;
0226 };
0227
0228 struct hdmi_pll_data {
0229     struct dss_pll pll;
0230
0231     void __iomem *base;
0232
0233     struct hdmi_wp_data *wp;
0234 };
0235
0236 struct hdmi_phy_data {
0237     void __iomem *base;
0238
0239     u8 lane_function[4];
0240     u8 lane_polarity[4];
0241 };
0242
0243 struct hdmi_core_data {
0244     void __iomem *base;
0245 };
0246
0247 static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
0248         u32 val)
0249 {
0250     __raw_writel(val, base_addr + idx);
0251 }
0252
0253 static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
0254 {
0255     return __raw_readl(base_addr + idx);
0256 }
0257
0258 #define REG_FLD_MOD(base, idx, val, start, end) \
0259     hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
0260                             val, start, end))
0261 #define REG_GET(base, idx, start, end) \
0262     FLD_GET(hdmi_read_reg(base, idx), start, end)
0263
0264 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
0265         const u32 idx, int b2, int b1, u32 val)
0266 {
0267     u32 t = 0, v;
0268     while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
0269         if (t++ > 10000)
0270             return v;
0271         udelay(1);
0272     }
0273     return v;
0274 }
0275
0276 /* HDMI wrapper funcs */
0277 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
0278 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
0279 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
0280 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
0281 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
0282 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
0283 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
0284 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
0285 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
0286 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
0287         struct hdmi_video_format *video_fmt);
0288 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
0289         struct omap_video_timings *timings);
0290 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
0291         struct omap_video_timings *timings);
0292 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
0293         struct omap_video_timings *timings, struct hdmi_config *param);
0294 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
0295 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
0296
0297 /* HDMI PLL funcs */
0298 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
0299 void hdmi_pll_compute(struct hdmi_pll_data *pll,
0300     unsigned long target_tmds, struct dss_pll_clock_info *pi);
0301 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
0302     struct hdmi_wp_data *wp);
0303 void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
0304
0305 /* HDMI PHY funcs */
0306 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
0307     unsigned long lfbitclk);
0308 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
0309 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
0310 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
0311
0312 /* HDMI common funcs */
0313 int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
0314     struct hdmi_phy_data *phy);
0315
0316 /* Audio funcs */
0317 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
0318 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
0319 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
0320 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
0321         struct hdmi_audio_format *aud_fmt);
0322 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
0323         struct hdmi_audio_dma *aud_dma);
0324 static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
0325 {
0326     return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
0327 }
0328
0329 /* HDMI DRV data */
0330 struct omap_hdmi {
0331     struct mutex lock;
0332     struct platform_device *pdev;
0333
0334     struct hdmi_wp_data wp;
0335     struct hdmi_pll_data    pll;
0336     struct hdmi_phy_data    phy;
0337     struct hdmi_core_data   core;
0338
0339     struct hdmi_config cfg;
0340
0341     struct regulator *vdda_reg;
0342
0343     bool core_enabled;
0344
0345     struct omap_dss_device output;
0346
0347     struct platform_device *audio_pdev;
0348     void (*audio_abort_cb)(struct device *dev);
0349     int wp_idlemode;
0350
0351     bool audio_configured;
0352     struct omap_dss_audio audio_config;
0353
0354     /* This lock should be taken when booleans bellow are touched. */
0355     spinlock_t audio_playing_lock;
0356     bool audio_playing;
0357     bool display_enabled;
0358 };
0359
0360 #endif