Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * linux/drivers/video/omap2/dss/dss.h
0004  *
0005  * Copyright (C) 2009 Nokia Corporation
0006  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
0007  *
0008  * Some code and ideas taken from drivers/video/omap/ driver
0009  * by Imre Deak.
0010  */
0011 
0012 #ifndef __OMAP2_DSS_H
0013 #define __OMAP2_DSS_H
0014 
0015 #include <linux/interrupt.h>
0016 
0017 #ifdef pr_fmt
0018 #undef pr_fmt
0019 #endif
0020 
0021 #ifdef DSS_SUBSYS_NAME
0022 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
0023 #else
0024 #define pr_fmt(fmt) fmt
0025 #endif
0026 
0027 #define DSSDBG(format, ...) \
0028     pr_debug(format, ## __VA_ARGS__)
0029 
0030 #ifdef DSS_SUBSYS_NAME
0031 #define DSSERR(format, ...) \
0032     printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
0033     ## __VA_ARGS__)
0034 #else
0035 #define DSSERR(format, ...) \
0036     printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
0037 #endif
0038 
0039 #ifdef DSS_SUBSYS_NAME
0040 #define DSSINFO(format, ...) \
0041     printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
0042     ## __VA_ARGS__)
0043 #else
0044 #define DSSINFO(format, ...) \
0045     printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
0046 #endif
0047 
0048 #ifdef DSS_SUBSYS_NAME
0049 #define DSSWARN(format, ...) \
0050     printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
0051     ## __VA_ARGS__)
0052 #else
0053 #define DSSWARN(format, ...) \
0054     printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
0055 #endif
0056 
0057 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
0058    number. For example 7:0 */
0059 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
0060 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
0061 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
0062 #define FLD_MOD(orig, val, start, end) \
0063     (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
0064 
0065 enum omap_dss_clk_source {
0066     OMAP_DSS_CLK_SRC_FCK = 0,       /* OMAP2/3: DSS1_ALWON_FCLK
0067                          * OMAP4: DSS_FCLK */
0068     OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,   /* OMAP3: DSI1_PLL_FCLK
0069                          * OMAP4: PLL1_CLK1 */
0070     OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
0071                          * OMAP4: PLL1_CLK2 */
0072     OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,  /* OMAP4: PLL2_CLK1 */
0073     OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,    /* OMAP4: PLL2_CLK2 */
0074 };
0075 
0076 enum dss_io_pad_mode {
0077     DSS_IO_PAD_MODE_RESET,
0078     DSS_IO_PAD_MODE_RFBI,
0079     DSS_IO_PAD_MODE_BYPASS,
0080 };
0081 
0082 enum dss_hdmi_venc_clk_source_select {
0083     DSS_VENC_TV_CLK = 0,
0084     DSS_HDMI_M_PCLK = 1,
0085 };
0086 
0087 enum dss_dsi_content_type {
0088     DSS_DSI_CONTENT_DCS,
0089     DSS_DSI_CONTENT_GENERIC,
0090 };
0091 
0092 enum dss_pll_id {
0093     DSS_PLL_DSI1,
0094     DSS_PLL_DSI2,
0095     DSS_PLL_HDMI,
0096     DSS_PLL_VIDEO1,
0097     DSS_PLL_VIDEO2,
0098 };
0099 
0100 struct dss_pll;
0101 
0102 #define DSS_PLL_MAX_HSDIVS 4
0103 
0104 /*
0105  * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
0106  * Type-B PLLs: clkout[0] refers to m2.
0107  */
0108 struct dss_pll_clock_info {
0109     /* rates that we get with dividers below */
0110     unsigned long fint;
0111     unsigned long clkdco;
0112     unsigned long clkout[DSS_PLL_MAX_HSDIVS];
0113 
0114     /* dividers */
0115     u16 n;
0116     u16 m;
0117     u32 mf;
0118     u16 mX[DSS_PLL_MAX_HSDIVS];
0119     u16 sd;
0120 };
0121 
0122 struct dss_pll_ops {
0123     int (*enable)(struct dss_pll *pll);
0124     void (*disable)(struct dss_pll *pll);
0125     int (*set_config)(struct dss_pll *pll,
0126         const struct dss_pll_clock_info *cinfo);
0127 };
0128 
0129 struct dss_pll_hw {
0130     unsigned n_max;
0131     unsigned m_min;
0132     unsigned m_max;
0133     unsigned mX_max;
0134 
0135     unsigned long fint_min, fint_max;
0136     unsigned long clkdco_min, clkdco_low, clkdco_max;
0137 
0138     u8 n_msb, n_lsb;
0139     u8 m_msb, m_lsb;
0140     u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
0141 
0142     bool has_stopmode;
0143     bool has_freqsel;
0144     bool has_selfreqdco;
0145     bool has_refsel;
0146 };
0147 
0148 struct dss_pll {
0149     const char *name;
0150     enum dss_pll_id id;
0151 
0152     struct clk *clkin;
0153     struct regulator *regulator;
0154 
0155     void __iomem *base;
0156 
0157     const struct dss_pll_hw *hw;
0158 
0159     const struct dss_pll_ops *ops;
0160 
0161     struct dss_pll_clock_info cinfo;
0162 };
0163 
0164 struct dispc_clock_info {
0165     /* rates that we get with dividers below */
0166     unsigned long lck;
0167     unsigned long pck;
0168 
0169     /* dividers */
0170     u16 lck_div;
0171     u16 pck_div;
0172 };
0173 
0174 struct dss_lcd_mgr_config {
0175     enum dss_io_pad_mode io_pad_mode;
0176 
0177     bool stallmode;
0178     bool fifohandcheck;
0179 
0180     struct dispc_clock_info clock_info;
0181 
0182     int video_port_width;
0183 
0184     int lcden_sig_polarity;
0185 };
0186 
0187 struct seq_file;
0188 struct platform_device;
0189 
0190 /* core */
0191 struct platform_device *dss_get_core_pdev(void);
0192 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
0193 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
0194 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
0195 void dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
0196 
0197 /* display */
0198 int dss_suspend_all_devices(void);
0199 int dss_resume_all_devices(void);
0200 void dss_disable_all_devices(void);
0201 
0202 int display_init_sysfs(struct platform_device *pdev);
0203 void display_uninit_sysfs(struct platform_device *pdev);
0204 
0205 /* manager */
0206 int dss_init_overlay_managers(void);
0207 void dss_uninit_overlay_managers(void);
0208 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
0209 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
0210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
0211         const struct omap_overlay_manager_info *info);
0212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
0213         const struct omap_video_timings *timings);
0214 int dss_mgr_check(struct omap_overlay_manager *mgr,
0215         struct omap_overlay_manager_info *info,
0216         const struct omap_video_timings *mgr_timings,
0217         const struct dss_lcd_mgr_config *config,
0218         struct omap_overlay_info **overlay_infos);
0219 
0220 static inline bool dss_mgr_is_lcd(enum omap_channel id)
0221 {
0222     if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
0223             id == OMAP_DSS_CHANNEL_LCD3)
0224         return true;
0225     else
0226         return false;
0227 }
0228 
0229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
0230         struct platform_device *pdev);
0231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
0232 
0233 /* overlay */
0234 void dss_init_overlays(struct platform_device *pdev);
0235 void dss_uninit_overlays(struct platform_device *pdev);
0236 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
0237 int dss_ovl_simple_check(struct omap_overlay *ovl,
0238         const struct omap_overlay_info *info);
0239 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
0240         const struct omap_video_timings *mgr_timings);
0241 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
0242         enum omap_color_mode mode);
0243 int dss_overlay_kobj_init(struct omap_overlay *ovl,
0244         struct platform_device *pdev);
0245 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
0246 
0247 /* DSS */
0248 int dss_init_platform_driver(void) __init;
0249 void dss_uninit_platform_driver(void);
0250 
0251 int dss_runtime_get(void);
0252 void dss_runtime_put(void);
0253 
0254 unsigned long dss_get_dispc_clk_rate(void);
0255 int dss_dpi_select_source(int port, enum omap_channel channel);
0256 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
0257 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
0258 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
0259 void dss_dump_clocks(struct seq_file *s);
0260 
0261 /* DSS VIDEO PLL */
0262 struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
0263     struct regulator *regulator);
0264 void dss_video_pll_uninit(struct dss_pll *pll);
0265 
0266 /* dss-of */
0267 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
0268 u32 dss_of_port_get_port_number(struct device_node *port);
0269 
0270 #if defined(CONFIG_FB_OMAP2_DSS_DEBUGFS)
0271 void dss_debug_dump_clocks(struct seq_file *s);
0272 #endif
0273 
0274 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
0275 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
0276     enum omap_channel channel);
0277 
0278 void dss_sdi_init(int datapairs);
0279 int dss_sdi_enable(void);
0280 void dss_sdi_disable(void);
0281 
0282 void dss_select_dsi_clk_source(int dsi_module,
0283         enum omap_dss_clk_source clk_src);
0284 void dss_select_lcd_clk_source(enum omap_channel channel,
0285         enum omap_dss_clk_source clk_src);
0286 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
0287 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
0288 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
0289 
0290 void dss_set_venc_output(enum omap_dss_venc_type type);
0291 void dss_set_dac_pwrdn_bgz(bool enable);
0292 
0293 int dss_set_fck_rate(unsigned long rate);
0294 
0295 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
0296 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
0297         dss_div_calc_func func, void *data);
0298 
0299 /* SDI */
0300 int sdi_init_platform_driver(void) __init;
0301 void sdi_uninit_platform_driver(void);
0302 
0303 #ifdef CONFIG_FB_OMAP2_DSS_SDI
0304 int sdi_init_port(struct platform_device *pdev, struct device_node *port);
0305 void sdi_uninit_port(struct device_node *port);
0306 #else
0307 static inline int sdi_init_port(struct platform_device *pdev,
0308         struct device_node *port)
0309 {
0310     return 0;
0311 }
0312 static inline void sdi_uninit_port(struct device_node *port)
0313 {
0314 }
0315 #endif
0316 
0317 /* DSI */
0318 
0319 #ifdef CONFIG_FB_OMAP2_DSS_DSI
0320 
0321 struct dentry;
0322 struct file_operations;
0323 
0324 int dsi_init_platform_driver(void) __init;
0325 void dsi_uninit_platform_driver(void);
0326 
0327 void dsi_dump_clocks(struct seq_file *s);
0328 
0329 void dsi_irq_handler(void);
0330 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
0331 
0332 #else
0333 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
0334 {
0335     WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
0336          __func__);
0337     return 0;
0338 }
0339 #endif
0340 
0341 /* DPI */
0342 int dpi_init_platform_driver(void) __init;
0343 void dpi_uninit_platform_driver(void);
0344 
0345 #ifdef CONFIG_FB_OMAP2_DSS_DPI
0346 int dpi_init_port(struct platform_device *pdev, struct device_node *port);
0347 void dpi_uninit_port(struct device_node *port);
0348 #else
0349 static inline int dpi_init_port(struct platform_device *pdev,
0350         struct device_node *port)
0351 {
0352     return 0;
0353 }
0354 static inline void dpi_uninit_port(struct device_node *port)
0355 {
0356 }
0357 #endif
0358 
0359 /* DISPC */
0360 int dispc_init_platform_driver(void) __init;
0361 void dispc_uninit_platform_driver(void);
0362 void dispc_dump_clocks(struct seq_file *s);
0363 
0364 void dispc_enable_sidle(void);
0365 void dispc_disable_sidle(void);
0366 
0367 void dispc_lcd_enable_signal(bool enable);
0368 void dispc_pck_free_enable(bool enable);
0369 void dispc_enable_fifomerge(bool enable);
0370 void dispc_enable_gamma_table(bool enable);
0371 
0372 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
0373         unsigned long pck, void *data);
0374 bool dispc_div_calc(unsigned long dispc,
0375         unsigned long pck_min, unsigned long pck_max,
0376         dispc_div_calc_func func, void *data);
0377 
0378 bool dispc_mgr_timings_ok(enum omap_channel channel,
0379         const struct omap_video_timings *timings);
0380 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
0381         struct dispc_clock_info *cinfo);
0382 
0383 
0384 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
0385 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
0386         u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
0387         bool manual_update);
0388 
0389 void dispc_mgr_set_clock_div(enum omap_channel channel,
0390         const struct dispc_clock_info *cinfo);
0391 int dispc_mgr_get_clock_div(enum omap_channel channel,
0392         struct dispc_clock_info *cinfo);
0393 void dispc_set_tv_pclk(unsigned long pclk);
0394 
0395 u32 dispc_read_irqstatus(void);
0396 void dispc_clear_irqstatus(u32 mask);
0397 u32 dispc_read_irqenable(void);
0398 void dispc_write_irqenable(u32 mask);
0399 
0400 int dispc_request_irq(irq_handler_t handler, void *dev_id);
0401 void dispc_free_irq(void *dev_id);
0402 
0403 int dispc_runtime_get(void);
0404 void dispc_runtime_put(void);
0405 
0406 void dispc_mgr_enable(enum omap_channel channel, bool enable);
0407 bool dispc_mgr_is_enabled(enum omap_channel channel);
0408 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
0409 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
0410 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
0411 bool dispc_mgr_go_busy(enum omap_channel channel);
0412 void dispc_mgr_go(enum omap_channel channel);
0413 void dispc_mgr_set_lcd_config(enum omap_channel channel,
0414         const struct dss_lcd_mgr_config *config);
0415 void dispc_mgr_set_timings(enum omap_channel channel,
0416         const struct omap_video_timings *timings);
0417 void dispc_mgr_setup(enum omap_channel channel,
0418         const struct omap_overlay_manager_info *info);
0419 
0420 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
0421         const struct omap_overlay_info *oi,
0422         const struct omap_video_timings *timings,
0423         int *x_predecim, int *y_predecim);
0424 
0425 int dispc_ovl_enable(enum omap_plane plane, bool enable);
0426 bool dispc_ovl_enabled(enum omap_plane plane);
0427 void dispc_ovl_set_channel_out(enum omap_plane plane,
0428         enum omap_channel channel);
0429 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
0430         bool replication, const struct omap_video_timings *mgr_timings,
0431         bool mem_to_mem);
0432 
0433 /* VENC */
0434 int venc_init_platform_driver(void) __init;
0435 void venc_uninit_platform_driver(void);
0436 
0437 /* HDMI */
0438 int hdmi4_init_platform_driver(void) __init;
0439 void hdmi4_uninit_platform_driver(void);
0440 
0441 int hdmi5_init_platform_driver(void) __init;
0442 void hdmi5_uninit_platform_driver(void);
0443 
0444 
0445 #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
0446 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
0447 {
0448     int b;
0449     for (b = 0; b < 32; ++b) {
0450         if (irqstatus & (1 << b))
0451             irq_arr[b]++;
0452     }
0453 }
0454 #endif
0455 
0456 /* PLL */
0457 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
0458         unsigned long clkdco, void *data);
0459 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
0460         void *data);
0461 
0462 int dss_pll_register(struct dss_pll *pll);
0463 void dss_pll_unregister(struct dss_pll *pll);
0464 struct dss_pll *dss_pll_find(const char *name);
0465 int dss_pll_enable(struct dss_pll *pll);
0466 void dss_pll_disable(struct dss_pll *pll);
0467 int dss_pll_set_config(struct dss_pll *pll,
0468         const struct dss_pll_clock_info *cinfo);
0469 
0470 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
0471         unsigned long out_min, unsigned long out_max,
0472         dss_hsdiv_calc_func func, void *data);
0473 bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
0474         unsigned long pll_min, unsigned long pll_max,
0475         dss_pll_calc_func func, void *data);
0476 int dss_pll_write_config_type_a(struct dss_pll *pll,
0477         const struct dss_pll_clock_info *cinfo);
0478 int dss_pll_write_config_type_b(struct dss_pll *pll,
0479         const struct dss_pll_clock_info *cinfo);
0480 int dss_pll_wait_reset_done(struct dss_pll *pll);
0481 
0482 /* compat */
0483 
0484 struct dss_mgr_ops {
0485     int (*connect)(struct omap_overlay_manager *mgr,
0486         struct omap_dss_device *dst);
0487     void (*disconnect)(struct omap_overlay_manager *mgr,
0488         struct omap_dss_device *dst);
0489 
0490     void (*start_update)(struct omap_overlay_manager *mgr);
0491     int (*enable)(struct omap_overlay_manager *mgr);
0492     void (*disable)(struct omap_overlay_manager *mgr);
0493     void (*set_timings)(struct omap_overlay_manager *mgr,
0494             const struct omap_video_timings *timings);
0495     void (*set_lcd_config)(struct omap_overlay_manager *mgr,
0496             const struct dss_lcd_mgr_config *config);
0497     int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
0498             void (*handler)(void *), void *data);
0499     void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
0500             void (*handler)(void *), void *data);
0501 };
0502 
0503 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
0504 void dss_uninstall_mgr_ops(void);
0505 
0506 int dss_mgr_connect(struct omap_overlay_manager *mgr,
0507         struct omap_dss_device *dst);
0508 void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
0509         struct omap_dss_device *dst);
0510 void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
0511         const struct omap_video_timings *timings);
0512 void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
0513         const struct dss_lcd_mgr_config *config);
0514 int dss_mgr_enable(struct omap_overlay_manager *mgr);
0515 void dss_mgr_disable(struct omap_overlay_manager *mgr);
0516 void dss_mgr_start_update(struct omap_overlay_manager *mgr);
0517 int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
0518         void (*handler)(void *), void *data);
0519 void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
0520         void (*handler)(void *), void *data);
0521 
0522 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!