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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * linux/drivers/video/omap2/dss/dispc.h
0004  *
0005  * Copyright (C) 2011 Texas Instruments
0006  * Author: Archit Taneja <archit@ti.com>
0007  */
0008 
0009 #ifndef __OMAP2_DISPC_REG_H
0010 #define __OMAP2_DISPC_REG_H
0011 
0012 /* DISPC common registers */
0013 #define DISPC_REVISION          0x0000
0014 #define DISPC_SYSCONFIG         0x0010
0015 #define DISPC_SYSSTATUS         0x0014
0016 #define DISPC_IRQSTATUS         0x0018
0017 #define DISPC_IRQENABLE         0x001C
0018 #define DISPC_CONTROL           0x0040
0019 #define DISPC_CONFIG            0x0044
0020 #define DISPC_CAPABLE           0x0048
0021 #define DISPC_LINE_STATUS       0x005C
0022 #define DISPC_LINE_NUMBER       0x0060
0023 #define DISPC_GLOBAL_ALPHA      0x0074
0024 #define DISPC_CONTROL2          0x0238
0025 #define DISPC_CONFIG2           0x0620
0026 #define DISPC_DIVISOR           0x0804
0027 #define DISPC_GLOBAL_BUFFER     0x0800
0028 #define DISPC_CONTROL3                  0x0848
0029 #define DISPC_CONFIG3                   0x084C
0030 #define DISPC_MSTANDBY_CTRL     0x0858
0031 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE    0x085C
0032 
0033 /* DISPC overlay registers */
0034 #define DISPC_OVL_BA0(n)        (DISPC_OVL_BASE(n) + \
0035                     DISPC_BA0_OFFSET(n))
0036 #define DISPC_OVL_BA1(n)        (DISPC_OVL_BASE(n) + \
0037                     DISPC_BA1_OFFSET(n))
0038 #define DISPC_OVL_BA0_UV(n)     (DISPC_OVL_BASE(n) + \
0039                     DISPC_BA0_UV_OFFSET(n))
0040 #define DISPC_OVL_BA1_UV(n)     (DISPC_OVL_BASE(n) + \
0041                     DISPC_BA1_UV_OFFSET(n))
0042 #define DISPC_OVL_POSITION(n)       (DISPC_OVL_BASE(n) + \
0043                     DISPC_POS_OFFSET(n))
0044 #define DISPC_OVL_SIZE(n)       (DISPC_OVL_BASE(n) + \
0045                     DISPC_SIZE_OFFSET(n))
0046 #define DISPC_OVL_ATTRIBUTES(n)     (DISPC_OVL_BASE(n) + \
0047                     DISPC_ATTR_OFFSET(n))
0048 #define DISPC_OVL_ATTRIBUTES2(n)    (DISPC_OVL_BASE(n) + \
0049                     DISPC_ATTR2_OFFSET(n))
0050 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
0051                     DISPC_FIFO_THRESH_OFFSET(n))
0052 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
0053                     DISPC_FIFO_SIZE_STATUS_OFFSET(n))
0054 #define DISPC_OVL_ROW_INC(n)        (DISPC_OVL_BASE(n) + \
0055                     DISPC_ROW_INC_OFFSET(n))
0056 #define DISPC_OVL_PIXEL_INC(n)      (DISPC_OVL_BASE(n) + \
0057                     DISPC_PIX_INC_OFFSET(n))
0058 #define DISPC_OVL_WINDOW_SKIP(n)    (DISPC_OVL_BASE(n) + \
0059                     DISPC_WINDOW_SKIP_OFFSET(n))
0060 #define DISPC_OVL_TABLE_BA(n)       (DISPC_OVL_BASE(n) + \
0061                     DISPC_TABLE_BA_OFFSET(n))
0062 #define DISPC_OVL_FIR(n)        (DISPC_OVL_BASE(n) + \
0063                     DISPC_FIR_OFFSET(n))
0064 #define DISPC_OVL_FIR2(n)       (DISPC_OVL_BASE(n) + \
0065                     DISPC_FIR2_OFFSET(n))
0066 #define DISPC_OVL_PICTURE_SIZE(n)   (DISPC_OVL_BASE(n) + \
0067                     DISPC_PIC_SIZE_OFFSET(n))
0068 #define DISPC_OVL_ACCU0(n)      (DISPC_OVL_BASE(n) + \
0069                     DISPC_ACCU0_OFFSET(n))
0070 #define DISPC_OVL_ACCU1(n)      (DISPC_OVL_BASE(n) + \
0071                     DISPC_ACCU1_OFFSET(n))
0072 #define DISPC_OVL_ACCU2_0(n)        (DISPC_OVL_BASE(n) + \
0073                     DISPC_ACCU2_0_OFFSET(n))
0074 #define DISPC_OVL_ACCU2_1(n)        (DISPC_OVL_BASE(n) + \
0075                     DISPC_ACCU2_1_OFFSET(n))
0076 #define DISPC_OVL_FIR_COEF_H(n, i)  (DISPC_OVL_BASE(n) + \
0077                     DISPC_FIR_COEF_H_OFFSET(n, i))
0078 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
0079                     DISPC_FIR_COEF_HV_OFFSET(n, i))
0080 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
0081                     DISPC_FIR_COEF_H2_OFFSET(n, i))
0082 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
0083                     DISPC_FIR_COEF_HV2_OFFSET(n, i))
0084 #define DISPC_OVL_CONV_COEF(n, i)   (DISPC_OVL_BASE(n) + \
0085                     DISPC_CONV_COEF_OFFSET(n, i))
0086 #define DISPC_OVL_FIR_COEF_V(n, i)  (DISPC_OVL_BASE(n) + \
0087                     DISPC_FIR_COEF_V_OFFSET(n, i))
0088 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
0089                     DISPC_FIR_COEF_V2_OFFSET(n, i))
0090 #define DISPC_OVL_PRELOAD(n)        (DISPC_OVL_BASE(n) + \
0091                     DISPC_PRELOAD_OFFSET(n))
0092 #define DISPC_OVL_MFLAG_THRESHOLD(n)    DISPC_MFLAG_THRESHOLD_OFFSET(n)
0093 
0094 /* DISPC up/downsampling FIR filter coefficient structure */
0095 struct dispc_coef {
0096     s8 hc4_vc22;
0097     s8 hc3_vc2;
0098     u8 hc2_vc1;
0099     s8 hc1_vc0;
0100     s8 hc0_vc00;
0101 };
0102 
0103 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
0104 
0105 /* DISPC manager/channel specific registers */
0106 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
0107 {
0108     switch (channel) {
0109     case OMAP_DSS_CHANNEL_LCD:
0110         return 0x004C;
0111     case OMAP_DSS_CHANNEL_DIGIT:
0112         return 0x0050;
0113     case OMAP_DSS_CHANNEL_LCD2:
0114         return 0x03AC;
0115     case OMAP_DSS_CHANNEL_LCD3:
0116         return 0x0814;
0117     default:
0118         BUG();
0119         return 0;
0120     }
0121 }
0122 
0123 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
0124 {
0125     switch (channel) {
0126     case OMAP_DSS_CHANNEL_LCD:
0127         return 0x0054;
0128     case OMAP_DSS_CHANNEL_DIGIT:
0129         return 0x0058;
0130     case OMAP_DSS_CHANNEL_LCD2:
0131         return 0x03B0;
0132     case OMAP_DSS_CHANNEL_LCD3:
0133         return 0x0818;
0134     default:
0135         BUG();
0136         return 0;
0137     }
0138 }
0139 
0140 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
0141 {
0142     switch (channel) {
0143     case OMAP_DSS_CHANNEL_LCD:
0144         return 0x0064;
0145     case OMAP_DSS_CHANNEL_DIGIT:
0146         BUG();
0147         return 0;
0148     case OMAP_DSS_CHANNEL_LCD2:
0149         return 0x0400;
0150     case OMAP_DSS_CHANNEL_LCD3:
0151         return 0x0840;
0152     default:
0153         BUG();
0154         return 0;
0155     }
0156 }
0157 
0158 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
0159 {
0160     switch (channel) {
0161     case OMAP_DSS_CHANNEL_LCD:
0162         return 0x0068;
0163     case OMAP_DSS_CHANNEL_DIGIT:
0164         BUG();
0165         return 0;
0166     case OMAP_DSS_CHANNEL_LCD2:
0167         return 0x0404;
0168     case OMAP_DSS_CHANNEL_LCD3:
0169         return 0x0844;
0170     default:
0171         BUG();
0172         return 0;
0173     }
0174 }
0175 
0176 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
0177 {
0178     switch (channel) {
0179     case OMAP_DSS_CHANNEL_LCD:
0180         return 0x006C;
0181     case OMAP_DSS_CHANNEL_DIGIT:
0182         BUG();
0183         return 0;
0184     case OMAP_DSS_CHANNEL_LCD2:
0185         return 0x0408;
0186     case OMAP_DSS_CHANNEL_LCD3:
0187         return 0x083C;
0188     default:
0189         BUG();
0190         return 0;
0191     }
0192 }
0193 
0194 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
0195 {
0196     switch (channel) {
0197     case OMAP_DSS_CHANNEL_LCD:
0198         return 0x0070;
0199     case OMAP_DSS_CHANNEL_DIGIT:
0200         BUG();
0201         return 0;
0202     case OMAP_DSS_CHANNEL_LCD2:
0203         return 0x040C;
0204     case OMAP_DSS_CHANNEL_LCD3:
0205         return 0x0838;
0206     default:
0207         BUG();
0208         return 0;
0209     }
0210 }
0211 
0212 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
0213 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
0214 {
0215     switch (channel) {
0216     case OMAP_DSS_CHANNEL_LCD:
0217         return 0x007C;
0218     case OMAP_DSS_CHANNEL_DIGIT:
0219         return 0x0078;
0220     case OMAP_DSS_CHANNEL_LCD2:
0221         return 0x03CC;
0222     case OMAP_DSS_CHANNEL_LCD3:
0223         return 0x0834;
0224     default:
0225         BUG();
0226         return 0;
0227     }
0228 }
0229 
0230 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
0231 {
0232     switch (channel) {
0233     case OMAP_DSS_CHANNEL_LCD:
0234         return 0x01D4;
0235     case OMAP_DSS_CHANNEL_DIGIT:
0236         BUG();
0237         return 0;
0238     case OMAP_DSS_CHANNEL_LCD2:
0239         return 0x03C0;
0240     case OMAP_DSS_CHANNEL_LCD3:
0241         return 0x0828;
0242     default:
0243         BUG();
0244         return 0;
0245     }
0246 }
0247 
0248 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
0249 {
0250     switch (channel) {
0251     case OMAP_DSS_CHANNEL_LCD:
0252         return 0x01D8;
0253     case OMAP_DSS_CHANNEL_DIGIT:
0254         BUG();
0255         return 0;
0256     case OMAP_DSS_CHANNEL_LCD2:
0257         return 0x03C4;
0258     case OMAP_DSS_CHANNEL_LCD3:
0259         return 0x082C;
0260     default:
0261         BUG();
0262         return 0;
0263     }
0264 }
0265 
0266 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
0267 {
0268     switch (channel) {
0269     case OMAP_DSS_CHANNEL_LCD:
0270         return 0x01DC;
0271     case OMAP_DSS_CHANNEL_DIGIT:
0272         BUG();
0273         return 0;
0274     case OMAP_DSS_CHANNEL_LCD2:
0275         return 0x03C8;
0276     case OMAP_DSS_CHANNEL_LCD3:
0277         return 0x0830;
0278     default:
0279         BUG();
0280         return 0;
0281     }
0282 }
0283 
0284 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
0285 {
0286     switch (channel) {
0287     case OMAP_DSS_CHANNEL_LCD:
0288         return 0x0220;
0289     case OMAP_DSS_CHANNEL_DIGIT:
0290         BUG();
0291         return 0;
0292     case OMAP_DSS_CHANNEL_LCD2:
0293         return 0x03BC;
0294     case OMAP_DSS_CHANNEL_LCD3:
0295         return 0x0824;
0296     default:
0297         BUG();
0298         return 0;
0299     }
0300 }
0301 
0302 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
0303 {
0304     switch (channel) {
0305     case OMAP_DSS_CHANNEL_LCD:
0306         return 0x0224;
0307     case OMAP_DSS_CHANNEL_DIGIT:
0308         BUG();
0309         return 0;
0310     case OMAP_DSS_CHANNEL_LCD2:
0311         return 0x03B8;
0312     case OMAP_DSS_CHANNEL_LCD3:
0313         return 0x0820;
0314     default:
0315         BUG();
0316         return 0;
0317     }
0318 }
0319 
0320 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
0321 {
0322     switch (channel) {
0323     case OMAP_DSS_CHANNEL_LCD:
0324         return 0x0228;
0325     case OMAP_DSS_CHANNEL_DIGIT:
0326         BUG();
0327         return 0;
0328     case OMAP_DSS_CHANNEL_LCD2:
0329         return 0x03B4;
0330     case OMAP_DSS_CHANNEL_LCD3:
0331         return 0x081C;
0332     default:
0333         BUG();
0334         return 0;
0335     }
0336 }
0337 
0338 /* DISPC overlay register base addresses */
0339 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
0340 {
0341     switch (plane) {
0342     case OMAP_DSS_GFX:
0343         return 0x0080;
0344     case OMAP_DSS_VIDEO1:
0345         return 0x00BC;
0346     case OMAP_DSS_VIDEO2:
0347         return 0x014C;
0348     case OMAP_DSS_VIDEO3:
0349         return 0x0300;
0350     case OMAP_DSS_WB:
0351         return 0x0500;
0352     default:
0353         BUG();
0354         return 0;
0355     }
0356 }
0357 
0358 /* DISPC overlay register offsets */
0359 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
0360 {
0361     switch (plane) {
0362     case OMAP_DSS_GFX:
0363     case OMAP_DSS_VIDEO1:
0364     case OMAP_DSS_VIDEO2:
0365         return 0x0000;
0366     case OMAP_DSS_VIDEO3:
0367     case OMAP_DSS_WB:
0368         return 0x0008;
0369     default:
0370         BUG();
0371         return 0;
0372     }
0373 }
0374 
0375 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
0376 {
0377     switch (plane) {
0378     case OMAP_DSS_GFX:
0379     case OMAP_DSS_VIDEO1:
0380     case OMAP_DSS_VIDEO2:
0381         return 0x0004;
0382     case OMAP_DSS_VIDEO3:
0383     case OMAP_DSS_WB:
0384         return 0x000C;
0385     default:
0386         BUG();
0387         return 0;
0388     }
0389 }
0390 
0391 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
0392 {
0393     switch (plane) {
0394     case OMAP_DSS_GFX:
0395         BUG();
0396         return 0;
0397     case OMAP_DSS_VIDEO1:
0398         return 0x0544;
0399     case OMAP_DSS_VIDEO2:
0400         return 0x04BC;
0401     case OMAP_DSS_VIDEO3:
0402         return 0x0310;
0403     case OMAP_DSS_WB:
0404         return 0x0118;
0405     default:
0406         BUG();
0407         return 0;
0408     }
0409 }
0410 
0411 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
0412 {
0413     switch (plane) {
0414     case OMAP_DSS_GFX:
0415         BUG();
0416         return 0;
0417     case OMAP_DSS_VIDEO1:
0418         return 0x0548;
0419     case OMAP_DSS_VIDEO2:
0420         return 0x04C0;
0421     case OMAP_DSS_VIDEO3:
0422         return 0x0314;
0423     case OMAP_DSS_WB:
0424         return 0x011C;
0425     default:
0426         BUG();
0427         return 0;
0428     }
0429 }
0430 
0431 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
0432 {
0433     switch (plane) {
0434     case OMAP_DSS_GFX:
0435     case OMAP_DSS_VIDEO1:
0436     case OMAP_DSS_VIDEO2:
0437         return 0x0008;
0438     case OMAP_DSS_VIDEO3:
0439         return 0x009C;
0440     default:
0441         BUG();
0442         return 0;
0443     }
0444 }
0445 
0446 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
0447 {
0448     switch (plane) {
0449     case OMAP_DSS_GFX:
0450     case OMAP_DSS_VIDEO1:
0451     case OMAP_DSS_VIDEO2:
0452         return 0x000C;
0453     case OMAP_DSS_VIDEO3:
0454     case OMAP_DSS_WB:
0455         return 0x00A8;
0456     default:
0457         BUG();
0458         return 0;
0459     }
0460 }
0461 
0462 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
0463 {
0464     switch (plane) {
0465     case OMAP_DSS_GFX:
0466         return 0x0020;
0467     case OMAP_DSS_VIDEO1:
0468     case OMAP_DSS_VIDEO2:
0469         return 0x0010;
0470     case OMAP_DSS_VIDEO3:
0471     case OMAP_DSS_WB:
0472         return 0x0070;
0473     default:
0474         BUG();
0475         return 0;
0476     }
0477 }
0478 
0479 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
0480 {
0481     switch (plane) {
0482     case OMAP_DSS_GFX:
0483         BUG();
0484         return 0;
0485     case OMAP_DSS_VIDEO1:
0486         return 0x0568;
0487     case OMAP_DSS_VIDEO2:
0488         return 0x04DC;
0489     case OMAP_DSS_VIDEO3:
0490         return 0x032C;
0491     case OMAP_DSS_WB:
0492         return 0x0310;
0493     default:
0494         BUG();
0495         return 0;
0496     }
0497 }
0498 
0499 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
0500 {
0501     switch (plane) {
0502     case OMAP_DSS_GFX:
0503         return 0x0024;
0504     case OMAP_DSS_VIDEO1:
0505     case OMAP_DSS_VIDEO2:
0506         return 0x0014;
0507     case OMAP_DSS_VIDEO3:
0508     case OMAP_DSS_WB:
0509         return 0x008C;
0510     default:
0511         BUG();
0512         return 0;
0513     }
0514 }
0515 
0516 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
0517 {
0518     switch (plane) {
0519     case OMAP_DSS_GFX:
0520         return 0x0028;
0521     case OMAP_DSS_VIDEO1:
0522     case OMAP_DSS_VIDEO2:
0523         return 0x0018;
0524     case OMAP_DSS_VIDEO3:
0525     case OMAP_DSS_WB:
0526         return 0x0088;
0527     default:
0528         BUG();
0529         return 0;
0530     }
0531 }
0532 
0533 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
0534 {
0535     switch (plane) {
0536     case OMAP_DSS_GFX:
0537         return 0x002C;
0538     case OMAP_DSS_VIDEO1:
0539     case OMAP_DSS_VIDEO2:
0540         return 0x001C;
0541     case OMAP_DSS_VIDEO3:
0542     case OMAP_DSS_WB:
0543         return 0x00A4;
0544     default:
0545         BUG();
0546         return 0;
0547     }
0548 }
0549 
0550 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
0551 {
0552     switch (plane) {
0553     case OMAP_DSS_GFX:
0554         return 0x0030;
0555     case OMAP_DSS_VIDEO1:
0556     case OMAP_DSS_VIDEO2:
0557         return 0x0020;
0558     case OMAP_DSS_VIDEO3:
0559     case OMAP_DSS_WB:
0560         return 0x0098;
0561     default:
0562         BUG();
0563         return 0;
0564     }
0565 }
0566 
0567 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
0568 {
0569     switch (plane) {
0570     case OMAP_DSS_GFX:
0571         return 0x0034;
0572     case OMAP_DSS_VIDEO1:
0573     case OMAP_DSS_VIDEO2:
0574     case OMAP_DSS_VIDEO3:
0575         BUG();
0576         return 0;
0577     default:
0578         BUG();
0579         return 0;
0580     }
0581 }
0582 
0583 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
0584 {
0585     switch (plane) {
0586     case OMAP_DSS_GFX:
0587         return 0x0038;
0588     case OMAP_DSS_VIDEO1:
0589     case OMAP_DSS_VIDEO2:
0590     case OMAP_DSS_VIDEO3:
0591         BUG();
0592         return 0;
0593     default:
0594         BUG();
0595         return 0;
0596     }
0597 }
0598 
0599 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
0600 {
0601     switch (plane) {
0602     case OMAP_DSS_GFX:
0603         BUG();
0604         return 0;
0605     case OMAP_DSS_VIDEO1:
0606     case OMAP_DSS_VIDEO2:
0607         return 0x0024;
0608     case OMAP_DSS_VIDEO3:
0609     case OMAP_DSS_WB:
0610         return 0x0090;
0611     default:
0612         BUG();
0613         return 0;
0614     }
0615 }
0616 
0617 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
0618 {
0619     switch (plane) {
0620     case OMAP_DSS_GFX:
0621         BUG();
0622         return 0;
0623     case OMAP_DSS_VIDEO1:
0624         return 0x0580;
0625     case OMAP_DSS_VIDEO2:
0626         return 0x055C;
0627     case OMAP_DSS_VIDEO3:
0628         return 0x0424;
0629     case OMAP_DSS_WB:
0630         return 0x290;
0631     default:
0632         BUG();
0633         return 0;
0634     }
0635 }
0636 
0637 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
0638 {
0639     switch (plane) {
0640     case OMAP_DSS_GFX:
0641         BUG();
0642         return 0;
0643     case OMAP_DSS_VIDEO1:
0644     case OMAP_DSS_VIDEO2:
0645         return 0x0028;
0646     case OMAP_DSS_VIDEO3:
0647     case OMAP_DSS_WB:
0648         return 0x0094;
0649     default:
0650         BUG();
0651         return 0;
0652     }
0653 }
0654 
0655 
0656 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
0657 {
0658     switch (plane) {
0659     case OMAP_DSS_GFX:
0660         BUG();
0661         return 0;
0662     case OMAP_DSS_VIDEO1:
0663     case OMAP_DSS_VIDEO2:
0664         return 0x002C;
0665     case OMAP_DSS_VIDEO3:
0666     case OMAP_DSS_WB:
0667         return 0x0000;
0668     default:
0669         BUG();
0670         return 0;
0671     }
0672 }
0673 
0674 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
0675 {
0676     switch (plane) {
0677     case OMAP_DSS_GFX:
0678         BUG();
0679         return 0;
0680     case OMAP_DSS_VIDEO1:
0681         return 0x0584;
0682     case OMAP_DSS_VIDEO2:
0683         return 0x0560;
0684     case OMAP_DSS_VIDEO3:
0685         return 0x0428;
0686     case OMAP_DSS_WB:
0687         return 0x0294;
0688     default:
0689         BUG();
0690         return 0;
0691     }
0692 }
0693 
0694 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
0695 {
0696     switch (plane) {
0697     case OMAP_DSS_GFX:
0698         BUG();
0699         return 0;
0700     case OMAP_DSS_VIDEO1:
0701     case OMAP_DSS_VIDEO2:
0702         return 0x0030;
0703     case OMAP_DSS_VIDEO3:
0704     case OMAP_DSS_WB:
0705         return 0x0004;
0706     default:
0707         BUG();
0708         return 0;
0709     }
0710 }
0711 
0712 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
0713 {
0714     switch (plane) {
0715     case OMAP_DSS_GFX:
0716         BUG();
0717         return 0;
0718     case OMAP_DSS_VIDEO1:
0719         return 0x0588;
0720     case OMAP_DSS_VIDEO2:
0721         return 0x0564;
0722     case OMAP_DSS_VIDEO3:
0723         return 0x042C;
0724     case OMAP_DSS_WB:
0725         return 0x0298;
0726     default:
0727         BUG();
0728         return 0;
0729     }
0730 }
0731 
0732 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0733 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
0734 {
0735     switch (plane) {
0736     case OMAP_DSS_GFX:
0737         BUG();
0738         return 0;
0739     case OMAP_DSS_VIDEO1:
0740     case OMAP_DSS_VIDEO2:
0741         return 0x0034 + i * 0x8;
0742     case OMAP_DSS_VIDEO3:
0743     case OMAP_DSS_WB:
0744         return 0x0010 + i * 0x8;
0745     default:
0746         BUG();
0747         return 0;
0748     }
0749 }
0750 
0751 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0752 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
0753 {
0754     switch (plane) {
0755     case OMAP_DSS_GFX:
0756         BUG();
0757         return 0;
0758     case OMAP_DSS_VIDEO1:
0759         return 0x058C + i * 0x8;
0760     case OMAP_DSS_VIDEO2:
0761         return 0x0568 + i * 0x8;
0762     case OMAP_DSS_VIDEO3:
0763         return 0x0430 + i * 0x8;
0764     case OMAP_DSS_WB:
0765         return 0x02A0 + i * 0x8;
0766     default:
0767         BUG();
0768         return 0;
0769     }
0770 }
0771 
0772 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0773 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
0774 {
0775     switch (plane) {
0776     case OMAP_DSS_GFX:
0777         BUG();
0778         return 0;
0779     case OMAP_DSS_VIDEO1:
0780     case OMAP_DSS_VIDEO2:
0781         return 0x0038 + i * 0x8;
0782     case OMAP_DSS_VIDEO3:
0783     case OMAP_DSS_WB:
0784         return 0x0014 + i * 0x8;
0785     default:
0786         BUG();
0787         return 0;
0788     }
0789 }
0790 
0791 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0792 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
0793 {
0794     switch (plane) {
0795     case OMAP_DSS_GFX:
0796         BUG();
0797         return 0;
0798     case OMAP_DSS_VIDEO1:
0799         return 0x0590 + i * 8;
0800     case OMAP_DSS_VIDEO2:
0801         return 0x056C + i * 0x8;
0802     case OMAP_DSS_VIDEO3:
0803         return 0x0434 + i * 0x8;
0804     case OMAP_DSS_WB:
0805         return 0x02A4 + i * 0x8;
0806     default:
0807         BUG();
0808         return 0;
0809     }
0810 }
0811 
0812 /* coef index i = {0, 1, 2, 3, 4,} */
0813 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
0814 {
0815     switch (plane) {
0816     case OMAP_DSS_GFX:
0817         BUG();
0818         return 0;
0819     case OMAP_DSS_VIDEO1:
0820     case OMAP_DSS_VIDEO2:
0821     case OMAP_DSS_VIDEO3:
0822     case OMAP_DSS_WB:
0823         return 0x0074 + i * 0x4;
0824     default:
0825         BUG();
0826         return 0;
0827     }
0828 }
0829 
0830 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0831 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
0832 {
0833     switch (plane) {
0834     case OMAP_DSS_GFX:
0835         BUG();
0836         return 0;
0837     case OMAP_DSS_VIDEO1:
0838         return 0x0124 + i * 0x4;
0839     case OMAP_DSS_VIDEO2:
0840         return 0x00B4 + i * 0x4;
0841     case OMAP_DSS_VIDEO3:
0842     case OMAP_DSS_WB:
0843         return 0x0050 + i * 0x4;
0844     default:
0845         BUG();
0846         return 0;
0847     }
0848 }
0849 
0850 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
0851 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
0852 {
0853     switch (plane) {
0854     case OMAP_DSS_GFX:
0855         BUG();
0856         return 0;
0857     case OMAP_DSS_VIDEO1:
0858         return 0x05CC + i * 0x4;
0859     case OMAP_DSS_VIDEO2:
0860         return 0x05A8 + i * 0x4;
0861     case OMAP_DSS_VIDEO3:
0862         return 0x0470 + i * 0x4;
0863     case OMAP_DSS_WB:
0864         return 0x02E0 + i * 0x4;
0865     default:
0866         BUG();
0867         return 0;
0868     }
0869 }
0870 
0871 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
0872 {
0873     switch (plane) {
0874     case OMAP_DSS_GFX:
0875         return 0x01AC;
0876     case OMAP_DSS_VIDEO1:
0877         return 0x0174;
0878     case OMAP_DSS_VIDEO2:
0879         return 0x00E8;
0880     case OMAP_DSS_VIDEO3:
0881         return 0x00A0;
0882     default:
0883         BUG();
0884         return 0;
0885     }
0886 }
0887 
0888 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
0889 {
0890     switch (plane) {
0891     case OMAP_DSS_GFX:
0892         return 0x0860;
0893     case OMAP_DSS_VIDEO1:
0894         return 0x0864;
0895     case OMAP_DSS_VIDEO2:
0896         return 0x0868;
0897     case OMAP_DSS_VIDEO3:
0898         return 0x086c;
0899     case OMAP_DSS_WB:
0900         return 0x0870;
0901     default:
0902         BUG();
0903         return 0;
0904     }
0905 }
0906 
0907 #endif
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