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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Epson HWA742 LCD controller driver
0004  *
0005  * Copyright (C) 2004-2005 Nokia Corporation
0006  * Authors:     Juha Yrjölä   <juha.yrjola@nokia.com>
0007  *          Imre Deak     <imre.deak@nokia.com>
0008  * YUV support: Jussi Laako   <jussi.laako@nokia.com>
0009  */
0010 #include <linux/module.h>
0011 #include <linux/mm.h>
0012 #include <linux/fb.h>
0013 #include <linux/delay.h>
0014 #include <linux/clk.h>
0015 #include <linux/interrupt.h>
0016 
0017 #include "omapfb.h"
0018 
0019 #define HWA742_REV_CODE_REG       0x0
0020 #define HWA742_CONFIG_REG         0x2
0021 #define HWA742_PLL_DIV_REG        0x4
0022 #define HWA742_PLL_0_REG          0x6
0023 #define HWA742_PLL_1_REG          0x8
0024 #define HWA742_PLL_2_REG          0xa
0025 #define HWA742_PLL_3_REG          0xc
0026 #define HWA742_PLL_4_REG          0xe
0027 #define HWA742_CLK_SRC_REG        0x12
0028 #define HWA742_PANEL_TYPE_REG     0x14
0029 #define HWA742_H_DISP_REG         0x16
0030 #define HWA742_H_NDP_REG          0x18
0031 #define HWA742_V_DISP_1_REG       0x1a
0032 #define HWA742_V_DISP_2_REG       0x1c
0033 #define HWA742_V_NDP_REG          0x1e
0034 #define HWA742_HS_W_REG           0x20
0035 #define HWA742_HP_S_REG           0x22
0036 #define HWA742_VS_W_REG           0x24
0037 #define HWA742_VP_S_REG           0x26
0038 #define HWA742_PCLK_POL_REG       0x28
0039 #define HWA742_INPUT_MODE_REG     0x2a
0040 #define HWA742_TRANSL_MODE_REG1   0x2e
0041 #define HWA742_DISP_MODE_REG      0x34
0042 #define HWA742_WINDOW_TYPE        0x36
0043 #define HWA742_WINDOW_X_START_0   0x38
0044 #define HWA742_WINDOW_X_START_1   0x3a
0045 #define HWA742_WINDOW_Y_START_0   0x3c
0046 #define HWA742_WINDOW_Y_START_1   0x3e
0047 #define HWA742_WINDOW_X_END_0     0x40
0048 #define HWA742_WINDOW_X_END_1     0x42
0049 #define HWA742_WINDOW_Y_END_0     0x44
0050 #define HWA742_WINDOW_Y_END_1     0x46
0051 #define HWA742_MEMORY_WRITE_LSB   0x48
0052 #define HWA742_MEMORY_WRITE_MSB   0x49
0053 #define HWA742_MEMORY_READ_0      0x4a
0054 #define HWA742_MEMORY_READ_1      0x4c
0055 #define HWA742_MEMORY_READ_2      0x4e
0056 #define HWA742_POWER_SAVE         0x56
0057 #define HWA742_NDP_CTRL           0x58
0058 
0059 #define HWA742_AUTO_UPDATE_TIME     (HZ / 20)
0060 
0061 /* Reserve 4 request slots for requests in irq context */
0062 #define REQ_POOL_SIZE           24
0063 #define IRQ_REQ_POOL_SIZE       4
0064 
0065 #define REQ_FROM_IRQ_POOL 0x01
0066 
0067 #define REQ_COMPLETE    0
0068 #define REQ_PENDING 1
0069 
0070 struct update_param {
0071     int x, y, width, height;
0072     int color_mode;
0073     int flags;
0074 };
0075 
0076 struct hwa742_request {
0077     struct list_head entry;
0078     unsigned int     flags;
0079 
0080     int      (*handler)(struct hwa742_request *req);
0081     void         (*complete)(void *data);
0082     void         *complete_data;
0083 
0084     union {
0085         struct update_param update;
0086         struct completion   *sync;
0087     } par;
0088 };
0089 
0090 struct {
0091     enum omapfb_update_mode update_mode;
0092     enum omapfb_update_mode update_mode_before_suspend;
0093 
0094     struct timer_list   auto_update_timer;
0095     int         stop_auto_update;
0096     struct omapfb_update_window auto_update_window;
0097     unsigned        te_connected:1;
0098     unsigned        vsync_only:1;
0099 
0100     struct hwa742_request   req_pool[REQ_POOL_SIZE];
0101     struct list_head    pending_req_list;
0102     struct list_head    free_req_list;
0103 
0104     /*
0105      * @req_lock: protect request slots pool and its tracking lists
0106      * @req_sema: counter; slot allocators from task contexts must
0107      *            push it down before acquiring a slot. This
0108      *            guarantees that atomic contexts will always have
0109      *            a minimum of IRQ_REQ_POOL_SIZE slots available.
0110      */
0111     struct semaphore    req_sema;
0112     spinlock_t      req_lock;
0113 
0114     struct extif_timings    reg_timings, lut_timings;
0115 
0116     int         prev_color_mode;
0117     int         prev_flags;
0118     int         window_type;
0119 
0120     u32         max_transmit_size;
0121     u32         extif_clk_period;
0122     unsigned long       pix_tx_time;
0123     unsigned long       line_upd_time;
0124 
0125 
0126     struct omapfb_device    *fbdev;
0127     struct lcd_ctrl_extif   *extif;
0128     const struct lcd_ctrl   *int_ctrl;
0129 
0130     struct clk      *sys_ck;
0131 } hwa742;
0132 
0133 struct lcd_ctrl hwa742_ctrl;
0134 
0135 static u8 hwa742_read_reg(u8 reg)
0136 {
0137     u8 data;
0138 
0139     hwa742.extif->set_bits_per_cycle(8);
0140     hwa742.extif->write_command(&reg, 1);
0141     hwa742.extif->read_data(&data, 1);
0142 
0143     return data;
0144 }
0145 
0146 static void hwa742_write_reg(u8 reg, u8 data)
0147 {
0148     hwa742.extif->set_bits_per_cycle(8);
0149     hwa742.extif->write_command(&reg, 1);
0150     hwa742.extif->write_data(&data, 1);
0151 }
0152 
0153 static void set_window_regs(int x_start, int y_start, int x_end, int y_end)
0154 {
0155     u8 tmp[8];
0156     u8 cmd;
0157 
0158     x_end--;
0159     y_end--;
0160     tmp[0] = x_start;
0161     tmp[1] = x_start >> 8;
0162     tmp[2] = y_start;
0163     tmp[3] = y_start >> 8;
0164     tmp[4] = x_end;
0165     tmp[5] = x_end >> 8;
0166     tmp[6] = y_end;
0167     tmp[7] = y_end >> 8;
0168 
0169     hwa742.extif->set_bits_per_cycle(8);
0170     cmd = HWA742_WINDOW_X_START_0;
0171 
0172     hwa742.extif->write_command(&cmd, 1);
0173 
0174     hwa742.extif->write_data(tmp, 8);
0175 }
0176 
0177 static void set_format_regs(int conv, int transl, int flags)
0178 {
0179     if (flags & OMAPFB_FORMAT_FLAG_DOUBLE) {
0180         hwa742.window_type = ((hwa742.window_type & 0xfc) | 0x01);
0181 #ifdef VERBOSE
0182         dev_dbg(hwa742.fbdev->dev, "hwa742: enabled pixel doubling\n");
0183 #endif
0184     } else {
0185         hwa742.window_type = (hwa742.window_type & 0xfc);
0186 #ifdef VERBOSE
0187         dev_dbg(hwa742.fbdev->dev, "hwa742: disabled pixel doubling\n");
0188 #endif
0189     }
0190 
0191     hwa742_write_reg(HWA742_INPUT_MODE_REG, conv);
0192     hwa742_write_reg(HWA742_TRANSL_MODE_REG1, transl);
0193     hwa742_write_reg(HWA742_WINDOW_TYPE, hwa742.window_type);
0194 }
0195 
0196 static void enable_tearsync(int y, int width, int height, int screen_height,
0197                 int force_vsync)
0198 {
0199     u8 b;
0200 
0201     b = hwa742_read_reg(HWA742_NDP_CTRL);
0202     b |= 1 << 2;
0203     hwa742_write_reg(HWA742_NDP_CTRL, b);
0204 
0205     if (likely(hwa742.vsync_only || force_vsync)) {
0206         hwa742.extif->enable_tearsync(1, 0);
0207         return;
0208     }
0209 
0210     if (width * hwa742.pix_tx_time < hwa742.line_upd_time) {
0211         hwa742.extif->enable_tearsync(1, 0);
0212         return;
0213     }
0214 
0215     if ((width * hwa742.pix_tx_time / 1000) * height <
0216         (y + height) * (hwa742.line_upd_time / 1000)) {
0217         hwa742.extif->enable_tearsync(1, 0);
0218         return;
0219     }
0220 
0221     hwa742.extif->enable_tearsync(1, y + 1);
0222 }
0223 
0224 static void disable_tearsync(void)
0225 {
0226     u8 b;
0227 
0228     hwa742.extif->enable_tearsync(0, 0);
0229 
0230     b = hwa742_read_reg(HWA742_NDP_CTRL);
0231     b &= ~(1 << 2);
0232     hwa742_write_reg(HWA742_NDP_CTRL, b);
0233 }
0234 
0235 static inline struct hwa742_request *alloc_req(bool can_sleep)
0236 {
0237     unsigned long flags;
0238     struct hwa742_request *req;
0239     int req_flags = 0;
0240 
0241     if (can_sleep)
0242         down(&hwa742.req_sema);
0243     else
0244         req_flags = REQ_FROM_IRQ_POOL;
0245 
0246     spin_lock_irqsave(&hwa742.req_lock, flags);
0247     BUG_ON(list_empty(&hwa742.free_req_list));
0248     req = list_entry(hwa742.free_req_list.next,
0249              struct hwa742_request, entry);
0250     list_del(&req->entry);
0251     spin_unlock_irqrestore(&hwa742.req_lock, flags);
0252 
0253     INIT_LIST_HEAD(&req->entry);
0254     req->flags = req_flags;
0255 
0256     return req;
0257 }
0258 
0259 static inline void free_req(struct hwa742_request *req)
0260 {
0261     unsigned long flags;
0262 
0263     spin_lock_irqsave(&hwa742.req_lock, flags);
0264 
0265     list_move(&req->entry, &hwa742.free_req_list);
0266     if (!(req->flags & REQ_FROM_IRQ_POOL))
0267         up(&hwa742.req_sema);
0268 
0269     spin_unlock_irqrestore(&hwa742.req_lock, flags);
0270 }
0271 
0272 static void process_pending_requests(void)
0273 {
0274     unsigned long flags;
0275 
0276     spin_lock_irqsave(&hwa742.req_lock, flags);
0277 
0278     while (!list_empty(&hwa742.pending_req_list)) {
0279         struct hwa742_request *req;
0280         void (*complete)(void *);
0281         void *complete_data;
0282 
0283         req = list_entry(hwa742.pending_req_list.next,
0284                  struct hwa742_request, entry);
0285         spin_unlock_irqrestore(&hwa742.req_lock, flags);
0286 
0287         if (req->handler(req) == REQ_PENDING)
0288             return;
0289 
0290         complete = req->complete;
0291         complete_data = req->complete_data;
0292         free_req(req);
0293 
0294         if (complete)
0295             complete(complete_data);
0296 
0297         spin_lock_irqsave(&hwa742.req_lock, flags);
0298     }
0299 
0300     spin_unlock_irqrestore(&hwa742.req_lock, flags);
0301 }
0302 
0303 static void submit_req_list(struct list_head *head)
0304 {
0305     unsigned long flags;
0306     int process = 1;
0307 
0308     spin_lock_irqsave(&hwa742.req_lock, flags);
0309     if (likely(!list_empty(&hwa742.pending_req_list)))
0310         process = 0;
0311     list_splice_init(head, hwa742.pending_req_list.prev);
0312     spin_unlock_irqrestore(&hwa742.req_lock, flags);
0313 
0314     if (process)
0315         process_pending_requests();
0316 }
0317 
0318 static void request_complete(void *data)
0319 {
0320     struct hwa742_request   *req = (struct hwa742_request *)data;
0321     void            (*complete)(void *);
0322     void            *complete_data;
0323 
0324     complete = req->complete;
0325     complete_data = req->complete_data;
0326 
0327     free_req(req);
0328 
0329     if (complete)
0330         complete(complete_data);
0331 
0332     process_pending_requests();
0333 }
0334 
0335 static int send_frame_handler(struct hwa742_request *req)
0336 {
0337     struct update_param *par = &req->par.update;
0338     int x = par->x;
0339     int y = par->y;
0340     int w = par->width;
0341     int h = par->height;
0342     int bpp;
0343     int conv, transl;
0344     unsigned long offset;
0345     int color_mode = par->color_mode;
0346     int flags = par->flags;
0347     int scr_width = hwa742.fbdev->panel->x_res;
0348     int scr_height = hwa742.fbdev->panel->y_res;
0349 
0350 #ifdef VERBOSE
0351     dev_dbg(hwa742.fbdev->dev, "x %d y %d w %d h %d scr_width %d "
0352         "color_mode %d flags %d\n",
0353         x, y, w, h, scr_width, color_mode, flags);
0354 #endif
0355 
0356     switch (color_mode) {
0357     case OMAPFB_COLOR_YUV422:
0358         bpp = 16;
0359         conv = 0x08;
0360         transl = 0x25;
0361         break;
0362     case OMAPFB_COLOR_YUV420:
0363         bpp = 12;
0364         conv = 0x09;
0365         transl = 0x25;
0366         break;
0367     case OMAPFB_COLOR_RGB565:
0368         bpp = 16;
0369         conv = 0x01;
0370         transl = 0x05;
0371         break;
0372     default:
0373         return -EINVAL;
0374     }
0375 
0376     if (hwa742.prev_flags != flags ||
0377         hwa742.prev_color_mode != color_mode) {
0378         set_format_regs(conv, transl, flags);
0379         hwa742.prev_color_mode = color_mode;
0380         hwa742.prev_flags = flags;
0381     }
0382     flags = req->par.update.flags;
0383     if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
0384         enable_tearsync(y, scr_width, h, scr_height,
0385                 flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
0386     else
0387         disable_tearsync();
0388 
0389     set_window_regs(x, y, x + w, y + h);
0390 
0391     offset = (scr_width * y + x) * bpp / 8;
0392 
0393     hwa742.int_ctrl->setup_plane(OMAPFB_PLANE_GFX,
0394             OMAPFB_CHANNEL_OUT_LCD, offset, scr_width, 0, 0, w, h,
0395             color_mode);
0396 
0397     hwa742.extif->set_bits_per_cycle(16);
0398 
0399     hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 1);
0400     hwa742.extif->transfer_area(w, h, request_complete, req);
0401 
0402     return REQ_PENDING;
0403 }
0404 
0405 static void send_frame_complete(void *data)
0406 {
0407     hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 0);
0408 }
0409 
0410 #define ADD_PREQ(_x, _y, _w, _h, can_sleep) do {\
0411     req = alloc_req(can_sleep);     \
0412     req->handler    = send_frame_handler;   \
0413     req->complete   = send_frame_complete;  \
0414     req->par.update.x = _x;         \
0415     req->par.update.y = _y;         \
0416     req->par.update.width  = _w;        \
0417     req->par.update.height = _h;        \
0418     req->par.update.color_mode = color_mode;\
0419     req->par.update.flags     = flags;  \
0420     list_add_tail(&req->entry, req_head);   \
0421 } while(0)
0422 
0423 static void create_req_list(struct omapfb_update_window *win,
0424                 struct list_head *req_head,
0425                 bool can_sleep)
0426 {
0427     struct hwa742_request *req;
0428     int x = win->x;
0429     int y = win->y;
0430     int width = win->width;
0431     int height = win->height;
0432     int color_mode;
0433     int flags;
0434 
0435     flags = win->format & ~OMAPFB_FORMAT_MASK;
0436     color_mode = win->format & OMAPFB_FORMAT_MASK;
0437 
0438     if (x & 1) {
0439         ADD_PREQ(x, y, 1, height, can_sleep);
0440         width--;
0441         x++;
0442         flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
0443     }
0444     if (width & ~1) {
0445         unsigned int xspan = width & ~1;
0446         unsigned int ystart = y;
0447         unsigned int yspan = height;
0448 
0449         if (xspan * height * 2 > hwa742.max_transmit_size) {
0450             yspan = hwa742.max_transmit_size / (xspan * 2);
0451             ADD_PREQ(x, ystart, xspan, yspan, can_sleep);
0452             ystart += yspan;
0453             yspan = height - yspan;
0454             flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
0455         }
0456 
0457         ADD_PREQ(x, ystart, xspan, yspan, can_sleep);
0458         x += xspan;
0459         width -= xspan;
0460         flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
0461     }
0462     if (width)
0463         ADD_PREQ(x, y, 1, height, can_sleep);
0464 }
0465 
0466 static void auto_update_complete(void *data)
0467 {
0468     if (!hwa742.stop_auto_update)
0469         mod_timer(&hwa742.auto_update_timer,
0470               jiffies + HWA742_AUTO_UPDATE_TIME);
0471 }
0472 
0473 static void __hwa742_update_window_auto(bool can_sleep)
0474 {
0475     LIST_HEAD(req_list);
0476     struct hwa742_request *last;
0477 
0478     create_req_list(&hwa742.auto_update_window, &req_list, can_sleep);
0479     last = list_entry(req_list.prev, struct hwa742_request, entry);
0480 
0481     last->complete = auto_update_complete;
0482     last->complete_data = NULL;
0483 
0484     submit_req_list(&req_list);
0485 }
0486 
0487 static void hwa742_update_window_auto(struct timer_list *unused)
0488 {
0489     __hwa742_update_window_auto(false);
0490 }
0491 
0492 static int hwa742_update_window_async(struct fb_info *fbi,
0493                  struct omapfb_update_window *win,
0494                  void (*complete_callback)(void *arg),
0495                  void *complete_callback_data)
0496 {
0497     LIST_HEAD(req_list);
0498     struct hwa742_request *last;
0499     int r = 0;
0500 
0501     if (hwa742.update_mode != OMAPFB_MANUAL_UPDATE) {
0502         dev_dbg(hwa742.fbdev->dev, "invalid update mode\n");
0503         r = -EINVAL;
0504         goto out;
0505     }
0506     if (unlikely(win->format &
0507         ~(0x03 | OMAPFB_FORMAT_FLAG_DOUBLE |
0508         OMAPFB_FORMAT_FLAG_TEARSYNC | OMAPFB_FORMAT_FLAG_FORCE_VSYNC))) {
0509         dev_dbg(hwa742.fbdev->dev, "invalid window flag\n");
0510         r = -EINVAL;
0511         goto out;
0512     }
0513 
0514     create_req_list(win, &req_list, true);
0515     last = list_entry(req_list.prev, struct hwa742_request, entry);
0516 
0517     last->complete = complete_callback;
0518     last->complete_data = (void *)complete_callback_data;
0519 
0520     submit_req_list(&req_list);
0521 
0522 out:
0523     return r;
0524 }
0525 
0526 static int hwa742_setup_plane(int plane, int channel_out,
0527                   unsigned long offset, int screen_width,
0528                   int pos_x, int pos_y, int width, int height,
0529                   int color_mode)
0530 {
0531     if (plane != OMAPFB_PLANE_GFX ||
0532         channel_out != OMAPFB_CHANNEL_OUT_LCD)
0533         return -EINVAL;
0534 
0535     return 0;
0536 }
0537 
0538 static int hwa742_enable_plane(int plane, int enable)
0539 {
0540     if (plane != 0)
0541         return -EINVAL;
0542 
0543     hwa742.int_ctrl->enable_plane(plane, enable);
0544 
0545     return 0;
0546 }
0547 
0548 static int sync_handler(struct hwa742_request *req)
0549 {
0550     complete(req->par.sync);
0551     return REQ_COMPLETE;
0552 }
0553 
0554 static void hwa742_sync(void)
0555 {
0556     LIST_HEAD(req_list);
0557     struct hwa742_request *req;
0558     struct completion comp;
0559 
0560     req = alloc_req(true);
0561 
0562     req->handler = sync_handler;
0563     req->complete = NULL;
0564     init_completion(&comp);
0565     req->par.sync = &comp;
0566 
0567     list_add(&req->entry, &req_list);
0568     submit_req_list(&req_list);
0569 
0570     wait_for_completion(&comp);
0571 }
0572 
0573 static void hwa742_bind_client(struct omapfb_notifier_block *nb)
0574 {
0575     dev_dbg(hwa742.fbdev->dev, "update_mode %d\n", hwa742.update_mode);
0576     if (hwa742.update_mode == OMAPFB_MANUAL_UPDATE) {
0577         omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
0578     }
0579 }
0580 
0581 static int hwa742_set_update_mode(enum omapfb_update_mode mode)
0582 {
0583     if (mode != OMAPFB_MANUAL_UPDATE && mode != OMAPFB_AUTO_UPDATE &&
0584         mode != OMAPFB_UPDATE_DISABLED)
0585         return -EINVAL;
0586 
0587     if (mode == hwa742.update_mode)
0588         return 0;
0589 
0590     dev_info(hwa742.fbdev->dev, "HWA742: setting update mode to %s\n",
0591             mode == OMAPFB_UPDATE_DISABLED ? "disabled" :
0592             (mode == OMAPFB_AUTO_UPDATE ? "auto" : "manual"));
0593 
0594     switch (hwa742.update_mode) {
0595     case OMAPFB_MANUAL_UPDATE:
0596         omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_DISABLED);
0597         break;
0598     case OMAPFB_AUTO_UPDATE:
0599         hwa742.stop_auto_update = 1;
0600         del_timer_sync(&hwa742.auto_update_timer);
0601         break;
0602     case OMAPFB_UPDATE_DISABLED:
0603         break;
0604     }
0605 
0606     hwa742.update_mode = mode;
0607     hwa742_sync();
0608     hwa742.stop_auto_update = 0;
0609 
0610     switch (mode) {
0611     case OMAPFB_MANUAL_UPDATE:
0612         omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
0613         break;
0614     case OMAPFB_AUTO_UPDATE:
0615         __hwa742_update_window_auto(true);
0616         break;
0617     case OMAPFB_UPDATE_DISABLED:
0618         break;
0619     }
0620 
0621     return 0;
0622 }
0623 
0624 static enum omapfb_update_mode hwa742_get_update_mode(void)
0625 {
0626     return hwa742.update_mode;
0627 }
0628 
0629 static unsigned long round_to_extif_ticks(unsigned long ps, int div)
0630 {
0631     int bus_tick = hwa742.extif_clk_period * div;
0632     return (ps + bus_tick - 1) / bus_tick * bus_tick;
0633 }
0634 
0635 static int calc_reg_timing(unsigned long sysclk, int div)
0636 {
0637     struct extif_timings *t;
0638     unsigned long systim;
0639 
0640     /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
0641      * AccessTime 2 ns + 12.2 ns (regs),
0642      * WEOffTime = WEOnTime + 1 ns,
0643      * REOffTime = REOnTime + 16 ns (regs),
0644      * CSOffTime = REOffTime + 1 ns
0645      * ReadCycle = 2ns + 2*SYSCLK  (regs),
0646      * WriteCycle = 2*SYSCLK + 2 ns,
0647      * CSPulseWidth = 10 ns */
0648     systim = 1000000000 / (sysclk / 1000);
0649     dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
0650           "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
0651 
0652     t = &hwa742.reg_timings;
0653     memset(t, 0, sizeof(*t));
0654     t->clk_div = div;
0655     t->cs_on_time = 0;
0656     t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
0657     t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
0658     t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div);
0659     t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
0660     t->re_off_time = round_to_extif_ticks(t->re_on_time + 16000, div);
0661     t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
0662     t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
0663     if (t->we_cycle_time < t->we_off_time)
0664         t->we_cycle_time = t->we_off_time;
0665     t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
0666     if (t->re_cycle_time < t->re_off_time)
0667         t->re_cycle_time = t->re_off_time;
0668     t->cs_pulse_width = 0;
0669 
0670     dev_dbg(hwa742.fbdev->dev, "[reg]cson %d csoff %d reon %d reoff %d\n",
0671          t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
0672     dev_dbg(hwa742.fbdev->dev, "[reg]weon %d weoff %d recyc %d wecyc %d\n",
0673          t->we_on_time, t->we_off_time, t->re_cycle_time,
0674          t->we_cycle_time);
0675     dev_dbg(hwa742.fbdev->dev, "[reg]rdaccess %d cspulse %d\n",
0676          t->access_time, t->cs_pulse_width);
0677 
0678     return hwa742.extif->convert_timings(t);
0679 }
0680 
0681 static int calc_lut_timing(unsigned long sysclk, int div)
0682 {
0683     struct extif_timings *t;
0684     unsigned long systim;
0685 
0686     /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
0687      * AccessTime 2 ns + 4 * SYSCLK + 26 (lut),
0688      * WEOffTime = WEOnTime + 1 ns,
0689      * REOffTime = REOnTime + 4*SYSCLK + 26 ns (lut),
0690      * CSOffTime = REOffTime + 1 ns
0691      * ReadCycle = 2ns + 4*SYSCLK + 26 ns (lut),
0692      * WriteCycle = 2*SYSCLK + 2 ns,
0693      * CSPulseWidth = 10 ns
0694      */
0695     systim = 1000000000 / (sysclk / 1000);
0696     dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
0697           "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
0698 
0699     t = &hwa742.lut_timings;
0700     memset(t, 0, sizeof(*t));
0701 
0702     t->clk_div = div;
0703 
0704     t->cs_on_time = 0;
0705     t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
0706     t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
0707     t->access_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
0708                           26000, div);
0709     t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
0710     t->re_off_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
0711                           26000, div);
0712     t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
0713     t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
0714     if (t->we_cycle_time < t->we_off_time)
0715         t->we_cycle_time = t->we_off_time;
0716     t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div);
0717     if (t->re_cycle_time < t->re_off_time)
0718         t->re_cycle_time = t->re_off_time;
0719     t->cs_pulse_width = 0;
0720 
0721     dev_dbg(hwa742.fbdev->dev, "[lut]cson %d csoff %d reon %d reoff %d\n",
0722          t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
0723     dev_dbg(hwa742.fbdev->dev, "[lut]weon %d weoff %d recyc %d wecyc %d\n",
0724          t->we_on_time, t->we_off_time, t->re_cycle_time,
0725          t->we_cycle_time);
0726     dev_dbg(hwa742.fbdev->dev, "[lut]rdaccess %d cspulse %d\n",
0727          t->access_time, t->cs_pulse_width);
0728 
0729     return hwa742.extif->convert_timings(t);
0730 }
0731 
0732 static int calc_extif_timings(unsigned long sysclk, int *extif_mem_div)
0733 {
0734     int max_clk_div;
0735     int div;
0736 
0737     hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);
0738     for (div = 1; div < max_clk_div; div++) {
0739         if (calc_reg_timing(sysclk, div) == 0)
0740             break;
0741     }
0742     if (div >= max_clk_div)
0743         goto err;
0744 
0745     *extif_mem_div = div;
0746 
0747     for (div = 1; div < max_clk_div; div++) {
0748         if (calc_lut_timing(sysclk, div) == 0)
0749             break;
0750     }
0751 
0752     if (div >= max_clk_div)
0753         goto err;
0754 
0755     return 0;
0756 
0757 err:
0758     dev_err(hwa742.fbdev->dev, "can't setup timings\n");
0759     return -1;
0760 }
0761 
0762 static void calc_hwa742_clk_rates(unsigned long ext_clk,
0763                 unsigned long *sys_clk, unsigned long *pix_clk)
0764 {
0765     int pix_clk_src;
0766     int sys_div = 0, sys_mul = 0;
0767     int pix_div;
0768 
0769     pix_clk_src = hwa742_read_reg(HWA742_CLK_SRC_REG);
0770     pix_div = ((pix_clk_src >> 3) & 0x1f) + 1;
0771     if ((pix_clk_src & (0x3 << 1)) == 0) {
0772         /* Source is the PLL */
0773         sys_div = (hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x3f) + 1;
0774         sys_mul = (hwa742_read_reg(HWA742_PLL_4_REG) & 0x7f) + 1;
0775         *sys_clk = ext_clk * sys_mul / sys_div;
0776     } else  /* else source is ext clk, or oscillator */
0777         *sys_clk = ext_clk;
0778 
0779     *pix_clk = *sys_clk / pix_div;          /* HZ */
0780     dev_dbg(hwa742.fbdev->dev,
0781         "ext_clk %ld pix_src %d pix_div %d sys_div %d sys_mul %d\n",
0782         ext_clk, pix_clk_src & (0x3 << 1), pix_div, sys_div, sys_mul);
0783     dev_dbg(hwa742.fbdev->dev, "sys_clk %ld pix_clk %ld\n",
0784         *sys_clk, *pix_clk);
0785 }
0786 
0787 
0788 static int setup_tearsync(unsigned long pix_clk, int extif_div)
0789 {
0790     int hdisp, vdisp;
0791     int hndp, vndp;
0792     int hsw, vsw;
0793     int hs, vs;
0794     int hs_pol_inv, vs_pol_inv;
0795     int use_hsvs, use_ndp;
0796     u8  b;
0797 
0798     hsw = hwa742_read_reg(HWA742_HS_W_REG);
0799     vsw = hwa742_read_reg(HWA742_VS_W_REG);
0800     hs_pol_inv = !(hsw & 0x80);
0801     vs_pol_inv = !(vsw & 0x80);
0802     hsw = hsw & 0x7f;
0803     vsw = vsw & 0x3f;
0804 
0805     hdisp = (hwa742_read_reg(HWA742_H_DISP_REG) & 0x7f) * 8;
0806     vdisp = hwa742_read_reg(HWA742_V_DISP_1_REG) +
0807         ((hwa742_read_reg(HWA742_V_DISP_2_REG) & 0x3) << 8);
0808 
0809     hndp = hwa742_read_reg(HWA742_H_NDP_REG) & 0x7f;
0810     vndp = hwa742_read_reg(HWA742_V_NDP_REG);
0811 
0812     /* time to transfer one pixel (16bpp) in ps */
0813     hwa742.pix_tx_time = hwa742.reg_timings.we_cycle_time;
0814     if (hwa742.extif->get_max_tx_rate != NULL) {
0815         /*
0816          * The external interface might have a rate limitation,
0817          * if so, we have to maximize our transfer rate.
0818          */
0819         unsigned long min_tx_time;
0820         unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();
0821 
0822         dev_dbg(hwa742.fbdev->dev, "max_tx_rate %ld HZ\n",
0823             max_tx_rate);
0824         min_tx_time = 1000000000 / (max_tx_rate / 1000);  /* ps */
0825         if (hwa742.pix_tx_time < min_tx_time)
0826             hwa742.pix_tx_time = min_tx_time;
0827     }
0828 
0829     /* time to update one line in ps */
0830     hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000);
0831     hwa742.line_upd_time *= 1000;
0832     if (hdisp * hwa742.pix_tx_time > hwa742.line_upd_time)
0833         /*
0834          * transfer speed too low, we might have to use both
0835          * HS and VS
0836          */
0837         use_hsvs = 1;
0838     else
0839         /* decent transfer speed, we'll always use only VS */
0840         use_hsvs = 0;
0841 
0842     if (use_hsvs && (hs_pol_inv || vs_pol_inv)) {
0843         /*
0844          * HS or'ed with VS doesn't work, use the active high
0845          * TE signal based on HNDP / VNDP
0846          */
0847         use_ndp = 1;
0848         hs_pol_inv = 0;
0849         vs_pol_inv = 0;
0850         hs = hndp;
0851         vs = vndp;
0852     } else {
0853         /*
0854          * Use HS or'ed with VS as a TE signal if both are needed
0855          * or VNDP if only vsync is needed.
0856          */
0857         use_ndp = 0;
0858         hs = hsw;
0859         vs = vsw;
0860         if (!use_hsvs) {
0861             hs_pol_inv = 0;
0862             vs_pol_inv = 0;
0863         }
0864     }
0865 
0866     hs = hs * 1000000 / (pix_clk / 1000);           /* ps */
0867     hs *= 1000;
0868 
0869     vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000);  /* ps */
0870     vs *= 1000;
0871 
0872     if (vs <= hs)
0873         return -EDOM;
0874     /* set VS to 120% of HS to minimize VS detection time */
0875     vs = hs * 12 / 10;
0876     /* minimize HS too */
0877     hs = 10000;
0878 
0879     b = hwa742_read_reg(HWA742_NDP_CTRL);
0880     b &= ~0x3;
0881     b |= use_hsvs ? 1 : 0;
0882     b |= (use_ndp && use_hsvs) ? 0 : 2;
0883     hwa742_write_reg(HWA742_NDP_CTRL, b);
0884 
0885     hwa742.vsync_only = !use_hsvs;
0886 
0887     dev_dbg(hwa742.fbdev->dev,
0888         "pix_clk %ld HZ pix_tx_time %ld ps line_upd_time %ld ps\n",
0889         pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time);
0890     dev_dbg(hwa742.fbdev->dev,
0891         "hs %d ps vs %d ps mode %d vsync_only %d\n",
0892         hs, vs, (b & 0x3), !use_hsvs);
0893 
0894     return hwa742.extif->setup_tearsync(1, hs, vs,
0895                         hs_pol_inv, vs_pol_inv, extif_div);
0896 }
0897 
0898 static void hwa742_get_caps(int plane, struct omapfb_caps *caps)
0899 {
0900     hwa742.int_ctrl->get_caps(plane, caps);
0901     caps->ctrl |= OMAPFB_CAPS_MANUAL_UPDATE |
0902               OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE;
0903     if (hwa742.te_connected)
0904         caps->ctrl |= OMAPFB_CAPS_TEARSYNC;
0905     caps->wnd_color |= (1 << OMAPFB_COLOR_RGB565) |
0906                (1 << OMAPFB_COLOR_YUV420);
0907 }
0908 
0909 static void hwa742_suspend(void)
0910 {
0911     hwa742.update_mode_before_suspend = hwa742.update_mode;
0912     hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
0913     /* Enable sleep mode */
0914     hwa742_write_reg(HWA742_POWER_SAVE, 1 << 1);
0915     clk_disable(hwa742.sys_ck);
0916 }
0917 
0918 static void hwa742_resume(void)
0919 {
0920     clk_enable(hwa742.sys_ck);
0921 
0922     /* Disable sleep mode */
0923     hwa742_write_reg(HWA742_POWER_SAVE, 0);
0924     while (1) {
0925         /* Loop until PLL output is stabilized */
0926         if (hwa742_read_reg(HWA742_PLL_DIV_REG) & (1 << 7))
0927             break;
0928         set_current_state(TASK_UNINTERRUPTIBLE);
0929         schedule_timeout(msecs_to_jiffies(5));
0930     }
0931     hwa742_set_update_mode(hwa742.update_mode_before_suspend);
0932 }
0933 
0934 static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
0935                struct omapfb_mem_desc *req_vram)
0936 {
0937     int r = 0, i;
0938     u8 rev, conf;
0939     unsigned long ext_clk;
0940     unsigned long sys_clk, pix_clk;
0941     int extif_mem_div;
0942     struct omapfb_platform_data *omapfb_conf;
0943 
0944     BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
0945 
0946     hwa742.fbdev = fbdev;
0947     hwa742.extif = fbdev->ext_if;
0948     hwa742.int_ctrl = fbdev->int_ctrl;
0949 
0950     omapfb_conf = dev_get_platdata(fbdev->dev);
0951 
0952     hwa742.sys_ck = clk_get(NULL, "hwa_sys_ck");
0953 
0954     spin_lock_init(&hwa742.req_lock);
0955 
0956     if ((r = hwa742.int_ctrl->init(fbdev, 1, req_vram)) < 0)
0957         goto err1;
0958 
0959     if ((r = hwa742.extif->init(fbdev)) < 0)
0960         goto err2;
0961 
0962     ext_clk = clk_get_rate(hwa742.sys_ck);
0963     if ((r = calc_extif_timings(ext_clk, &extif_mem_div)) < 0)
0964         goto err3;
0965     hwa742.extif->set_timings(&hwa742.reg_timings);
0966     clk_prepare_enable(hwa742.sys_ck);
0967 
0968     calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk);
0969     if ((r = calc_extif_timings(sys_clk, &extif_mem_div)) < 0)
0970         goto err4;
0971     hwa742.extif->set_timings(&hwa742.reg_timings);
0972 
0973     rev = hwa742_read_reg(HWA742_REV_CODE_REG);
0974     if ((rev & 0xfc) != 0x80) {
0975         dev_err(fbdev->dev, "HWA742: invalid revision %02x\n", rev);
0976         r = -ENODEV;
0977         goto err4;
0978     }
0979 
0980 
0981     if (!(hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x80)) {
0982         dev_err(fbdev->dev,
0983               "HWA742: controller not initialized by the bootloader\n");
0984         r = -ENODEV;
0985         goto err4;
0986     }
0987 
0988     if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
0989         dev_err(hwa742.fbdev->dev,
0990             "HWA742: can't setup tearing synchronization\n");
0991         goto err4;
0992     }
0993     hwa742.te_connected = 1;
0994 
0995     hwa742.max_transmit_size = hwa742.extif->max_transmit_size;
0996 
0997     hwa742.update_mode = OMAPFB_UPDATE_DISABLED;
0998 
0999     hwa742.auto_update_window.x = 0;
1000     hwa742.auto_update_window.y = 0;
1001     hwa742.auto_update_window.width = fbdev->panel->x_res;
1002     hwa742.auto_update_window.height = fbdev->panel->y_res;
1003     hwa742.auto_update_window.format = 0;
1004 
1005     timer_setup(&hwa742.auto_update_timer, hwa742_update_window_auto, 0);
1006 
1007     hwa742.prev_color_mode = -1;
1008     hwa742.prev_flags = 0;
1009 
1010     hwa742.fbdev = fbdev;
1011 
1012     INIT_LIST_HEAD(&hwa742.free_req_list);
1013     INIT_LIST_HEAD(&hwa742.pending_req_list);
1014     for (i = 0; i < ARRAY_SIZE(hwa742.req_pool); i++)
1015         list_add(&hwa742.req_pool[i].entry, &hwa742.free_req_list);
1016     BUG_ON(i <= IRQ_REQ_POOL_SIZE);
1017     sema_init(&hwa742.req_sema, i - IRQ_REQ_POOL_SIZE);
1018 
1019     conf = hwa742_read_reg(HWA742_CONFIG_REG);
1020     dev_info(fbdev->dev, ": Epson HWA742 LCD controller rev %d "
1021             "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
1022 
1023     return 0;
1024 err4:
1025     clk_disable_unprepare(hwa742.sys_ck);
1026 err3:
1027     hwa742.extif->cleanup();
1028 err2:
1029     hwa742.int_ctrl->cleanup();
1030 err1:
1031     return r;
1032 }
1033 
1034 static void hwa742_cleanup(void)
1035 {
1036     hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
1037     hwa742.extif->cleanup();
1038     hwa742.int_ctrl->cleanup();
1039     clk_disable_unprepare(hwa742.sys_ck);
1040 }
1041 
1042 struct lcd_ctrl hwa742_ctrl = {
1043     .name           = "hwa742",
1044     .init           = hwa742_init,
1045     .cleanup        = hwa742_cleanup,
1046     .bind_client        = hwa742_bind_client,
1047     .get_caps       = hwa742_get_caps,
1048     .set_update_mode    = hwa742_set_update_mode,
1049     .get_update_mode    = hwa742_get_update_mode,
1050     .setup_plane        = hwa742_setup_plane,
1051     .enable_plane       = hwa742_enable_plane,
1052     .update_window      = hwa742_update_window_async,
1053     .sync           = hwa742_sync,
1054     .suspend        = hwa742_suspend,
1055     .resume         = hwa742_resume,
1056 };
1057
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