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0001 /*
0002  * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
0003  *
0004  * Copyright 2004 Antonino Daplas <adaplas@pol.net>
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file COPYING in the main directory of this archive
0008  * for more details.
0009  *
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/errno.h>
0015 #include <linux/string.h>
0016 #include <linux/mm.h>
0017 #include <linux/slab.h>
0018 #include <linux/delay.h>
0019 #include <linux/fb.h>
0020 #include <linux/init.h>
0021 #include <linux/pci.h>
0022 #include <linux/console.h>
0023 #include <linux/backlight.h>
0024 #ifdef CONFIG_BOOTX_TEXT
0025 #include <asm/btext.h>
0026 #endif
0027 
0028 #include "nv_local.h"
0029 #include "nv_type.h"
0030 #include "nv_proto.h"
0031 #include "nv_dma.h"
0032 
0033 #ifdef CONFIG_FB_NVIDIA_DEBUG
0034 #define NVTRACE          printk
0035 #else
0036 #define NVTRACE          if (0) printk
0037 #endif
0038 
0039 #define NVTRACE_ENTER(...)  NVTRACE("%s START\n", __func__)
0040 #define NVTRACE_LEAVE(...)  NVTRACE("%s END\n", __func__)
0041 
0042 #ifdef CONFIG_FB_NVIDIA_DEBUG
0043 #define assert(expr) \
0044     if (!(expr)) { \
0045     printk( "Assertion failed! %s,%s,%s,line=%d\n",\
0046     #expr,__FILE__,__func__,__LINE__); \
0047     BUG(); \
0048     }
0049 #else
0050 #define assert(expr)
0051 #endif
0052 
0053 #define PFX "nvidiafb: "
0054 
0055 /* HW cursor parameters */
0056 #define MAX_CURS        32
0057 
0058 static const struct pci_device_id nvidiafb_pci_tbl[] = {
0059     {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0060      PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
0061     { 0, }
0062 };
0063 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
0064 
0065 /* command line data, set in nvidiafb_setup() */
0066 static int flatpanel = -1;  /* Autodetect later */
0067 static int fpdither = -1;
0068 static int forceCRTC = -1;
0069 static int hwcur = 0;
0070 static int noaccel = 0;
0071 static int noscale = 0;
0072 static int paneltweak = 0;
0073 static int vram = 0;
0074 static int bpp = 8;
0075 static int reverse_i2c;
0076 static bool nomtrr = false;
0077 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
0078 
0079 static char *mode_option = NULL;
0080 
0081 static struct fb_fix_screeninfo nvidiafb_fix = {
0082     .type = FB_TYPE_PACKED_PIXELS,
0083     .xpanstep = 8,
0084     .ypanstep = 1,
0085 };
0086 
0087 static struct fb_var_screeninfo nvidiafb_default_var = {
0088     .xres = 640,
0089     .yres = 480,
0090     .xres_virtual = 640,
0091     .yres_virtual = 480,
0092     .bits_per_pixel = 8,
0093     .red = {0, 8, 0},
0094     .green = {0, 8, 0},
0095     .blue = {0, 8, 0},
0096     .transp = {0, 0, 0},
0097     .activate = FB_ACTIVATE_NOW,
0098     .height = -1,
0099     .width = -1,
0100     .pixclock = 39721,
0101     .left_margin = 40,
0102     .right_margin = 24,
0103     .upper_margin = 32,
0104     .lower_margin = 11,
0105     .hsync_len = 96,
0106     .vsync_len = 2,
0107     .vmode = FB_VMODE_NONINTERLACED
0108 };
0109 
0110 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
0111                        u16 bg, u16 fg, u32 w, u32 h)
0112 {
0113     u32 *data = (u32 *) data8;
0114     int i, j, k = 0;
0115     u32 b, tmp;
0116 
0117     w = (w + 1) & ~1;
0118 
0119     for (i = 0; i < h; i++) {
0120         b = *data++;
0121         reverse_order(&b);
0122 
0123         for (j = 0; j < w / 2; j++) {
0124             tmp = 0;
0125 #if defined (__BIG_ENDIAN)
0126             tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
0127             b <<= 1;
0128             tmp |= (b & (1 << 31)) ? fg : bg;
0129             b <<= 1;
0130 #else
0131             tmp = (b & 1) ? fg : bg;
0132             b >>= 1;
0133             tmp |= (b & 1) ? fg << 16 : bg << 16;
0134             b >>= 1;
0135 #endif
0136             NV_WR32(&par->CURSOR[k++], 0, tmp);
0137         }
0138         k += (MAX_CURS - w) / 2;
0139     }
0140 }
0141 
0142 static void nvidia_write_clut(struct nvidia_par *par,
0143                   u8 regnum, u8 red, u8 green, u8 blue)
0144 {
0145     NVWriteDacMask(par, 0xff);
0146     NVWriteDacWriteAddr(par, regnum);
0147     NVWriteDacData(par, red);
0148     NVWriteDacData(par, green);
0149     NVWriteDacData(par, blue);
0150 }
0151 
0152 static void nvidia_read_clut(struct nvidia_par *par,
0153                  u8 regnum, u8 * red, u8 * green, u8 * blue)
0154 {
0155     NVWriteDacMask(par, 0xff);
0156     NVWriteDacReadAddr(par, regnum);
0157     *red = NVReadDacData(par);
0158     *green = NVReadDacData(par);
0159     *blue = NVReadDacData(par);
0160 }
0161 
0162 static int nvidia_panel_tweak(struct nvidia_par *par,
0163                   struct _riva_hw_state *state)
0164 {
0165     int tweak = 0;
0166 
0167     if (par->paneltweak) {
0168         tweak = par->paneltweak;
0169     } else {
0170         /* Begin flat panel hacks.
0171          * This is unfortunate, but some chips need this register
0172          * tweaked or else you get artifacts where adjacent pixels are
0173          * swapped.  There are no hard rules for what to set here so all
0174          * we can do is experiment and apply hacks.
0175          */
0176         if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
0177             /* At least one NV34 laptop needs this workaround. */
0178             tweak = -1;
0179         }
0180 
0181         if ((par->Chipset & 0xfff0) == 0x0310)
0182             tweak = 1;
0183         /* end flat panel hacks */
0184     }
0185 
0186     return tweak;
0187 }
0188 
0189 static void nvidia_screen_off(struct nvidia_par *par, int on)
0190 {
0191     unsigned char tmp;
0192 
0193     if (on) {
0194         /*
0195          * Turn off screen and disable sequencer.
0196          */
0197         tmp = NVReadSeq(par, 0x01);
0198 
0199         NVWriteSeq(par, 0x00, 0x01);        /* Synchronous Reset */
0200         NVWriteSeq(par, 0x01, tmp | 0x20);  /* disable the display */
0201     } else {
0202         /*
0203          * Reenable sequencer, then turn on screen.
0204          */
0205 
0206         tmp = NVReadSeq(par, 0x01);
0207 
0208         NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
0209         NVWriteSeq(par, 0x00, 0x03);        /* End Reset */
0210     }
0211 }
0212 
0213 static void nvidia_save_vga(struct nvidia_par *par,
0214                 struct _riva_hw_state *state)
0215 {
0216     int i;
0217 
0218     NVTRACE_ENTER();
0219     NVLockUnlock(par, 0);
0220 
0221     NVUnloadStateExt(par, state);
0222 
0223     state->misc_output = NVReadMiscOut(par);
0224 
0225     for (i = 0; i < NUM_CRT_REGS; i++)
0226         state->crtc[i] = NVReadCrtc(par, i);
0227 
0228     for (i = 0; i < NUM_ATC_REGS; i++)
0229         state->attr[i] = NVReadAttr(par, i);
0230 
0231     for (i = 0; i < NUM_GRC_REGS; i++)
0232         state->gra[i] = NVReadGr(par, i);
0233 
0234     for (i = 0; i < NUM_SEQ_REGS; i++)
0235         state->seq[i] = NVReadSeq(par, i);
0236     NVTRACE_LEAVE();
0237 }
0238 
0239 #undef DUMP_REG
0240 
0241 static void nvidia_write_regs(struct nvidia_par *par,
0242                   struct _riva_hw_state *state)
0243 {
0244     int i;
0245 
0246     NVTRACE_ENTER();
0247 
0248     NVLoadStateExt(par, state);
0249 
0250     NVWriteMiscOut(par, state->misc_output);
0251 
0252     for (i = 1; i < NUM_SEQ_REGS; i++) {
0253 #ifdef DUMP_REG
0254         printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
0255 #endif
0256         NVWriteSeq(par, i, state->seq[i]);
0257     }
0258 
0259     /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
0260     NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
0261 
0262     for (i = 0; i < NUM_CRT_REGS; i++) {
0263         switch (i) {
0264         case 0x19:
0265         case 0x20 ... 0x40:
0266             break;
0267         default:
0268 #ifdef DUMP_REG
0269             printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
0270 #endif
0271             NVWriteCrtc(par, i, state->crtc[i]);
0272         }
0273     }
0274 
0275     for (i = 0; i < NUM_GRC_REGS; i++) {
0276 #ifdef DUMP_REG
0277         printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
0278 #endif
0279         NVWriteGr(par, i, state->gra[i]);
0280     }
0281 
0282     for (i = 0; i < NUM_ATC_REGS; i++) {
0283 #ifdef DUMP_REG
0284         printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
0285 #endif
0286         NVWriteAttr(par, i, state->attr[i]);
0287     }
0288 
0289     NVTRACE_LEAVE();
0290 }
0291 
0292 static int nvidia_calc_regs(struct fb_info *info)
0293 {
0294     struct nvidia_par *par = info->par;
0295     struct _riva_hw_state *state = &par->ModeReg;
0296     int i, depth = fb_get_color_depth(&info->var, &info->fix);
0297     int h_display = info->var.xres / 8 - 1;
0298     int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
0299     int h_end = (info->var.xres + info->var.right_margin +
0300              info->var.hsync_len) / 8 - 1;
0301     int h_total = (info->var.xres + info->var.right_margin +
0302                info->var.hsync_len + info->var.left_margin) / 8 - 5;
0303     int h_blank_s = h_display;
0304     int h_blank_e = h_total + 4;
0305     int v_display = info->var.yres - 1;
0306     int v_start = info->var.yres + info->var.lower_margin - 1;
0307     int v_end = (info->var.yres + info->var.lower_margin +
0308              info->var.vsync_len) - 1;
0309     int v_total = (info->var.yres + info->var.lower_margin +
0310                info->var.vsync_len + info->var.upper_margin) - 2;
0311     int v_blank_s = v_display;
0312     int v_blank_e = v_total + 1;
0313 
0314     /*
0315      * Set all CRTC values.
0316      */
0317 
0318     if (info->var.vmode & FB_VMODE_INTERLACED)
0319         v_total |= 1;
0320 
0321     if (par->FlatPanel == 1) {
0322         v_start = v_total - 3;
0323         v_end = v_total - 2;
0324         v_blank_s = v_start;
0325         h_start = h_total - 5;
0326         h_end = h_total - 2;
0327         h_blank_e = h_total + 4;
0328     }
0329 
0330     state->crtc[0x0] = Set8Bits(h_total);
0331     state->crtc[0x1] = Set8Bits(h_display);
0332     state->crtc[0x2] = Set8Bits(h_blank_s);
0333     state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
0334         | SetBit(7);
0335     state->crtc[0x4] = Set8Bits(h_start);
0336     state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
0337         | SetBitField(h_end, 4: 0, 4:0);
0338     state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
0339     state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
0340         | SetBitField(v_display, 8: 8, 1:1)
0341         | SetBitField(v_start, 8: 8, 2:2)
0342         | SetBitField(v_blank_s, 8: 8, 3:3)
0343         | SetBit(4)
0344         | SetBitField(v_total, 9: 9, 5:5)
0345         | SetBitField(v_display, 9: 9, 6:6)
0346         | SetBitField(v_start, 9: 9, 7:7);
0347     state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
0348         | SetBit(6)
0349         | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
0350     state->crtc[0x10] = Set8Bits(v_start);
0351     state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
0352     state->crtc[0x12] = Set8Bits(v_display);
0353     state->crtc[0x13] = ((info->var.xres_virtual / 8) *
0354                  (info->var.bits_per_pixel / 8));
0355     state->crtc[0x15] = Set8Bits(v_blank_s);
0356     state->crtc[0x16] = Set8Bits(v_blank_e);
0357 
0358     state->attr[0x10] = 0x01;
0359 
0360     if (par->Television)
0361         state->attr[0x11] = 0x00;
0362 
0363     state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
0364         | SetBitField(v_blank_s, 10: 10, 3:3)
0365         | SetBitField(v_start, 10: 10, 2:2)
0366         | SetBitField(v_display, 10: 10, 1:1)
0367         | SetBitField(v_total, 10: 10, 0:0);
0368 
0369     state->horiz = SetBitField(h_total, 8: 8, 0:0)
0370         | SetBitField(h_display, 8: 8, 1:1)
0371         | SetBitField(h_blank_s, 8: 8, 2:2)
0372         | SetBitField(h_start, 8: 8, 3:3);
0373 
0374     state->extra = SetBitField(v_total, 11: 11, 0:0)
0375         | SetBitField(v_display, 11: 11, 2:2)
0376         | SetBitField(v_start, 11: 11, 4:4)
0377         | SetBitField(v_blank_s, 11: 11, 6:6);
0378 
0379     if (info->var.vmode & FB_VMODE_INTERLACED) {
0380         h_total = (h_total >> 1) & ~1;
0381         state->interlace = Set8Bits(h_total);
0382         state->horiz |= SetBitField(h_total, 8: 8, 4:4);
0383     } else {
0384         state->interlace = 0xff;    /* interlace off */
0385     }
0386 
0387     /*
0388      * Calculate the extended registers.
0389      */
0390 
0391     if (depth < 24)
0392         i = depth;
0393     else
0394         i = 32;
0395 
0396     if (par->Architecture >= NV_ARCH_10)
0397         par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
0398                                par->CursorStart);
0399 
0400     if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
0401         state->misc_output &= ~0x40;
0402     else
0403         state->misc_output |= 0x40;
0404     if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
0405         state->misc_output &= ~0x80;
0406     else
0407         state->misc_output |= 0x80;
0408 
0409     NVCalcStateExt(par, state, i, info->var.xres_virtual,
0410                info->var.xres, info->var.yres_virtual,
0411                1000000000 / info->var.pixclock, info->var.vmode);
0412 
0413     state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
0414     if (par->FlatPanel == 1) {
0415         state->pixel |= (1 << 7);
0416 
0417         if (!par->fpScaler || (par->fpWidth <= info->var.xres)
0418             || (par->fpHeight <= info->var.yres)) {
0419             state->scale |= (1 << 8);
0420         }
0421 
0422         if (!par->crtcSync_read) {
0423             state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
0424             par->crtcSync_read = 1;
0425         }
0426 
0427         par->PanelTweak = nvidia_panel_tweak(par, state);
0428     }
0429 
0430     state->vpll = state->pll;
0431     state->vpll2 = state->pll;
0432     state->vpllB = state->pllB;
0433     state->vpll2B = state->pllB;
0434 
0435     VGA_WR08(par->PCIO, 0x03D4, 0x1C);
0436     state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
0437 
0438     if (par->CRTCnumber) {
0439         state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
0440         state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
0441         state->crtcOwner = 3;
0442         state->pllsel |= 0x20000800;
0443         state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
0444         if (par->twoStagePLL)
0445             state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
0446     } else if (par->twoHeads) {
0447         state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
0448         state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
0449         state->crtcOwner = 0;
0450         state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
0451         if (par->twoStagePLL)
0452             state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
0453     }
0454 
0455     state->cursorConfig = 0x00000100;
0456 
0457     if (info->var.vmode & FB_VMODE_DOUBLE)
0458         state->cursorConfig |= (1 << 4);
0459 
0460     if (par->alphaCursor) {
0461         if ((par->Chipset & 0x0ff0) != 0x0110)
0462             state->cursorConfig |= 0x04011000;
0463         else
0464             state->cursorConfig |= 0x14011000;
0465         state->general |= (1 << 29);
0466     } else
0467         state->cursorConfig |= 0x02000000;
0468 
0469     if (par->twoHeads) {
0470         if ((par->Chipset & 0x0ff0) == 0x0110) {
0471             state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
0472                 ~0x00010000;
0473             if (par->FPDither)
0474                 state->dither |= 0x00010000;
0475         } else {
0476             state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
0477             if (par->FPDither)
0478                 state->dither |= 1;
0479         }
0480     }
0481 
0482     state->timingH = 0;
0483     state->timingV = 0;
0484     state->displayV = info->var.xres;
0485 
0486     return 0;
0487 }
0488 
0489 static void nvidia_init_vga(struct fb_info *info)
0490 {
0491     struct nvidia_par *par = info->par;
0492     struct _riva_hw_state *state = &par->ModeReg;
0493     int i;
0494 
0495     for (i = 0; i < 0x10; i++)
0496         state->attr[i] = i;
0497     state->attr[0x10] = 0x41;
0498     state->attr[0x11] = 0xff;
0499     state->attr[0x12] = 0x0f;
0500     state->attr[0x13] = 0x00;
0501     state->attr[0x14] = 0x00;
0502 
0503     memset(state->crtc, 0x00, NUM_CRT_REGS);
0504     state->crtc[0x0a] = 0x20;
0505     state->crtc[0x17] = 0xe3;
0506     state->crtc[0x18] = 0xff;
0507     state->crtc[0x28] = 0x40;
0508 
0509     memset(state->gra, 0x00, NUM_GRC_REGS);
0510     state->gra[0x05] = 0x40;
0511     state->gra[0x06] = 0x05;
0512     state->gra[0x07] = 0x0f;
0513     state->gra[0x08] = 0xff;
0514 
0515     state->seq[0x00] = 0x03;
0516     state->seq[0x01] = 0x01;
0517     state->seq[0x02] = 0x0f;
0518     state->seq[0x03] = 0x00;
0519     state->seq[0x04] = 0x0e;
0520 
0521     state->misc_output = 0xeb;
0522 }
0523 
0524 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
0525 {
0526     struct nvidia_par *par = info->par;
0527     u8 data[MAX_CURS * MAX_CURS / 8];
0528     int i, set = cursor->set;
0529     u16 fg, bg;
0530 
0531     if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
0532         return -ENXIO;
0533 
0534     NVShowHideCursor(par, 0);
0535 
0536     if (par->cursor_reset) {
0537         set = FB_CUR_SETALL;
0538         par->cursor_reset = 0;
0539     }
0540 
0541     if (set & FB_CUR_SETSIZE)
0542         memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
0543 
0544     if (set & FB_CUR_SETPOS) {
0545         u32 xx, yy, temp;
0546 
0547         yy = cursor->image.dy - info->var.yoffset;
0548         xx = cursor->image.dx - info->var.xoffset;
0549         temp = xx & 0xFFFF;
0550         temp |= yy << 16;
0551 
0552         NV_WR32(par->PRAMDAC, 0x0000300, temp);
0553     }
0554 
0555     if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
0556         u32 bg_idx = cursor->image.bg_color;
0557         u32 fg_idx = cursor->image.fg_color;
0558         u32 s_pitch = (cursor->image.width + 7) >> 3;
0559         u32 d_pitch = MAX_CURS / 8;
0560         u8 *dat = (u8 *) cursor->image.data;
0561         u8 *msk = (u8 *) cursor->mask;
0562         u8 *src;
0563 
0564         src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
0565 
0566         if (src) {
0567             switch (cursor->rop) {
0568             case ROP_XOR:
0569                 for (i = 0; i < s_pitch * cursor->image.height; i++)
0570                     src[i] = dat[i] ^ msk[i];
0571                 break;
0572             case ROP_COPY:
0573             default:
0574                 for (i = 0; i < s_pitch * cursor->image.height; i++)
0575                     src[i] = dat[i] & msk[i];
0576                 break;
0577             }
0578 
0579             fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
0580                         cursor->image.height);
0581 
0582             bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
0583                 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
0584                 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
0585 
0586             fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
0587                 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
0588                 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
0589 
0590             NVLockUnlock(par, 0);
0591 
0592             nvidiafb_load_cursor_image(par, data, bg, fg,
0593                            cursor->image.width,
0594                            cursor->image.height);
0595             kfree(src);
0596         }
0597     }
0598 
0599     if (cursor->enable)
0600         NVShowHideCursor(par, 1);
0601 
0602     return 0;
0603 }
0604 
0605 static struct fb_ops nvidia_fb_ops;
0606 
0607 static int nvidiafb_set_par(struct fb_info *info)
0608 {
0609     struct nvidia_par *par = info->par;
0610 
0611     NVTRACE_ENTER();
0612 
0613     NVLockUnlock(par, 1);
0614     if (!par->FlatPanel || !par->twoHeads)
0615         par->FPDither = 0;
0616 
0617     if (par->FPDither < 0) {
0618         if ((par->Chipset & 0x0ff0) == 0x0110)
0619             par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
0620                        & 0x00010000);
0621         else
0622             par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
0623         printk(KERN_INFO PFX "Flat panel dithering %s\n",
0624                par->FPDither ? "enabled" : "disabled");
0625     }
0626 
0627     info->fix.visual = (info->var.bits_per_pixel == 8) ?
0628         FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
0629 
0630     nvidia_init_vga(info);
0631     nvidia_calc_regs(info);
0632 
0633     NVLockUnlock(par, 0);
0634     if (par->twoHeads) {
0635         VGA_WR08(par->PCIO, 0x03D4, 0x44);
0636         VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
0637         NVLockUnlock(par, 0);
0638     }
0639 
0640     nvidia_screen_off(par, 1);
0641 
0642     nvidia_write_regs(par, &par->ModeReg);
0643     NVSetStartAddress(par, 0);
0644 
0645 #if defined (__BIG_ENDIAN)
0646     /* turn on LFB swapping */
0647     {
0648         unsigned char tmp;
0649 
0650         VGA_WR08(par->PCIO, 0x3d4, 0x46);
0651         tmp = VGA_RD08(par->PCIO, 0x3d5);
0652         tmp |= (1 << 7);
0653         VGA_WR08(par->PCIO, 0x3d5, tmp);
0654     }
0655 #endif
0656 
0657     info->fix.line_length = (info->var.xres_virtual *
0658                  info->var.bits_per_pixel) >> 3;
0659     if (info->var.accel_flags) {
0660         nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit;
0661         nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect;
0662         nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea;
0663         nvidia_fb_ops.fb_sync = nvidiafb_sync;
0664         info->pixmap.scan_align = 4;
0665         info->flags &= ~FBINFO_HWACCEL_DISABLED;
0666         info->flags |= FBINFO_READS_FAST;
0667         NVResetGraphics(info);
0668     } else {
0669         nvidia_fb_ops.fb_imageblit = cfb_imageblit;
0670         nvidia_fb_ops.fb_fillrect = cfb_fillrect;
0671         nvidia_fb_ops.fb_copyarea = cfb_copyarea;
0672         nvidia_fb_ops.fb_sync = NULL;
0673         info->pixmap.scan_align = 1;
0674         info->flags |= FBINFO_HWACCEL_DISABLED;
0675         info->flags &= ~FBINFO_READS_FAST;
0676     }
0677 
0678     par->cursor_reset = 1;
0679 
0680     nvidia_screen_off(par, 0);
0681 
0682 #ifdef CONFIG_BOOTX_TEXT
0683     /* Update debug text engine */
0684     btext_update_display(info->fix.smem_start,
0685                  info->var.xres, info->var.yres,
0686                  info->var.bits_per_pixel, info->fix.line_length);
0687 #endif
0688 
0689     NVLockUnlock(par, 0);
0690     NVTRACE_LEAVE();
0691     return 0;
0692 }
0693 
0694 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
0695                   unsigned blue, unsigned transp,
0696                   struct fb_info *info)
0697 {
0698     struct nvidia_par *par = info->par;
0699     int i;
0700 
0701     NVTRACE_ENTER();
0702     if (regno >= (1 << info->var.green.length))
0703         return -EINVAL;
0704 
0705     if (info->var.grayscale) {
0706         /* gray = 0.30*R + 0.59*G + 0.11*B */
0707         red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
0708     }
0709 
0710     if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
0711         ((u32 *) info->pseudo_palette)[regno] =
0712             (regno << info->var.red.offset) |
0713             (regno << info->var.green.offset) |
0714             (regno << info->var.blue.offset);
0715     }
0716 
0717     switch (info->var.bits_per_pixel) {
0718     case 8:
0719         /* "transparent" stuff is completely ignored. */
0720         nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
0721         break;
0722     case 16:
0723         if (info->var.green.length == 5) {
0724             for (i = 0; i < 8; i++) {
0725                 nvidia_write_clut(par, regno * 8 + i, red >> 8,
0726                           green >> 8, blue >> 8);
0727             }
0728         } else {
0729             u8 r, g, b;
0730 
0731             if (regno < 32) {
0732                 for (i = 0; i < 8; i++) {
0733                     nvidia_write_clut(par, regno * 8 + i,
0734                               red >> 8, green >> 8,
0735                               blue >> 8);
0736                 }
0737             }
0738 
0739             nvidia_read_clut(par, regno * 4, &r, &g, &b);
0740 
0741             for (i = 0; i < 4; i++)
0742                 nvidia_write_clut(par, regno * 4 + i, r,
0743                           green >> 8, b);
0744         }
0745         break;
0746     case 32:
0747         nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
0748         break;
0749     default:
0750         /* do nothing */
0751         break;
0752     }
0753 
0754     NVTRACE_LEAVE();
0755     return 0;
0756 }
0757 
0758 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
0759                   struct fb_info *info)
0760 {
0761     struct nvidia_par *par = info->par;
0762     int memlen, vramlen, mode_valid = 0;
0763     int pitch, err = 0;
0764 
0765     NVTRACE_ENTER();
0766 
0767     var->transp.offset = 0;
0768     var->transp.length = 0;
0769 
0770     var->xres &= ~7;
0771 
0772     if (var->bits_per_pixel <= 8)
0773         var->bits_per_pixel = 8;
0774     else if (var->bits_per_pixel <= 16)
0775         var->bits_per_pixel = 16;
0776     else
0777         var->bits_per_pixel = 32;
0778 
0779     switch (var->bits_per_pixel) {
0780     case 8:
0781         var->red.offset = 0;
0782         var->red.length = 8;
0783         var->green.offset = 0;
0784         var->green.length = 8;
0785         var->blue.offset = 0;
0786         var->blue.length = 8;
0787         var->transp.offset = 0;
0788         var->transp.length = 0;
0789         break;
0790     case 16:
0791         var->green.length = (var->green.length < 6) ? 5 : 6;
0792         var->red.length = 5;
0793         var->blue.length = 5;
0794         var->transp.length = 6 - var->green.length;
0795         var->blue.offset = 0;
0796         var->green.offset = 5;
0797         var->red.offset = 5 + var->green.length;
0798         var->transp.offset = (5 + var->red.offset) & 15;
0799         break;
0800     case 32:        /* RGBA 8888 */
0801         var->red.offset = 16;
0802         var->red.length = 8;
0803         var->green.offset = 8;
0804         var->green.length = 8;
0805         var->blue.offset = 0;
0806         var->blue.length = 8;
0807         var->transp.length = 8;
0808         var->transp.offset = 24;
0809         break;
0810     }
0811 
0812     var->red.msb_right = 0;
0813     var->green.msb_right = 0;
0814     var->blue.msb_right = 0;
0815     var->transp.msb_right = 0;
0816 
0817     if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
0818         !info->monspecs.dclkmax || !fb_validate_mode(var, info))
0819         mode_valid = 1;
0820 
0821     /* calculate modeline if supported by monitor */
0822     if (!mode_valid && info->monspecs.gtf) {
0823         if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
0824             mode_valid = 1;
0825     }
0826 
0827     if (!mode_valid) {
0828         const struct fb_videomode *mode;
0829 
0830         mode = fb_find_best_mode(var, &info->modelist);
0831         if (mode) {
0832             fb_videomode_to_var(var, mode);
0833             mode_valid = 1;
0834         }
0835     }
0836 
0837     if (!mode_valid && info->monspecs.modedb_len)
0838         return -EINVAL;
0839 
0840     /*
0841      * If we're on a flat panel, check if the mode is outside of the
0842      * panel dimensions. If so, cap it and try for the next best mode
0843      * before bailing out.
0844      */
0845     if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
0846                           par->fpHeight < var->yres)) {
0847         const struct fb_videomode *mode;
0848 
0849         var->xres = par->fpWidth;
0850         var->yres = par->fpHeight;
0851 
0852         mode = fb_find_best_mode(var, &info->modelist);
0853         if (!mode) {
0854             printk(KERN_ERR PFX "mode out of range of flat "
0855                    "panel dimensions\n");
0856             return -EINVAL;
0857         }
0858 
0859         fb_videomode_to_var(var, mode);
0860     }
0861 
0862     if (var->yres_virtual < var->yres)
0863         var->yres_virtual = var->yres;
0864 
0865     if (var->xres_virtual < var->xres)
0866         var->xres_virtual = var->xres;
0867 
0868     var->xres_virtual = (var->xres_virtual + 63) & ~63;
0869 
0870     vramlen = info->screen_size;
0871     pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
0872     memlen = pitch * var->yres_virtual;
0873 
0874     if (memlen > vramlen) {
0875         var->yres_virtual = vramlen / pitch;
0876 
0877         if (var->yres_virtual < var->yres) {
0878             var->yres_virtual = var->yres;
0879             var->xres_virtual = vramlen / var->yres_virtual;
0880             var->xres_virtual /= var->bits_per_pixel / 8;
0881             var->xres_virtual &= ~63;
0882             pitch = (var->xres_virtual *
0883                  var->bits_per_pixel + 7) / 8;
0884             memlen = pitch * var->yres;
0885 
0886             if (var->xres_virtual < var->xres) {
0887                 printk("nvidiafb: required video memory, "
0888                        "%d bytes, for %dx%d-%d (virtual) "
0889                        "is out of range\n",
0890                        memlen, var->xres_virtual,
0891                        var->yres_virtual, var->bits_per_pixel);
0892                 err = -ENOMEM;
0893             }
0894         }
0895     }
0896 
0897     if (var->accel_flags) {
0898         if (var->yres_virtual > 0x7fff)
0899             var->yres_virtual = 0x7fff;
0900         if (var->xres_virtual > 0x7fff)
0901             var->xres_virtual = 0x7fff;
0902     }
0903 
0904     var->xres_virtual &= ~63;
0905 
0906     NVTRACE_LEAVE();
0907 
0908     return err;
0909 }
0910 
0911 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
0912                 struct fb_info *info)
0913 {
0914     struct nvidia_par *par = info->par;
0915     u32 total;
0916 
0917     total = var->yoffset * info->fix.line_length + var->xoffset;
0918 
0919     NVSetStartAddress(par, total);
0920 
0921     return 0;
0922 }
0923 
0924 static int nvidiafb_blank(int blank, struct fb_info *info)
0925 {
0926     struct nvidia_par *par = info->par;
0927     unsigned char tmp, vesa;
0928 
0929     tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
0930     vesa = NVReadCrtc(par, 0x1a) & ~0xc0;   /* sync on/off */
0931 
0932     NVTRACE_ENTER();
0933 
0934     if (blank)
0935         tmp |= 0x20;
0936 
0937     switch (blank) {
0938     case FB_BLANK_UNBLANK:
0939     case FB_BLANK_NORMAL:
0940         break;
0941     case FB_BLANK_VSYNC_SUSPEND:
0942         vesa |= 0x80;
0943         break;
0944     case FB_BLANK_HSYNC_SUSPEND:
0945         vesa |= 0x40;
0946         break;
0947     case FB_BLANK_POWERDOWN:
0948         vesa |= 0xc0;
0949         break;
0950     }
0951 
0952     NVWriteSeq(par, 0x01, tmp);
0953     NVWriteCrtc(par, 0x1a, vesa);
0954 
0955     NVTRACE_LEAVE();
0956 
0957     return 0;
0958 }
0959 
0960 /*
0961  * Because the VGA registers are not mapped linearly in its MMIO space,
0962  * restrict VGA register saving and restore to x86 only, where legacy VGA IO
0963  * access is legal. Consequently, we must also check if the device is the
0964  * primary display.
0965  */
0966 #ifdef CONFIG_X86
0967 static void save_vga_x86(struct nvidia_par *par)
0968 {
0969     struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
0970 
0971     if (res && res->flags & IORESOURCE_ROM_SHADOW) {
0972         memset(&par->vgastate, 0, sizeof(par->vgastate));
0973         par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
0974             VGA_SAVE_CMAP;
0975         save_vga(&par->vgastate);
0976     }
0977 }
0978 
0979 static void restore_vga_x86(struct nvidia_par *par)
0980 {
0981     struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
0982 
0983     if (res && res->flags & IORESOURCE_ROM_SHADOW)
0984         restore_vga(&par->vgastate);
0985 }
0986 #else
0987 #define save_vga_x86(x) do {} while (0)
0988 #define restore_vga_x86(x) do {} while (0)
0989 #endif /* X86 */
0990 
0991 static int nvidiafb_open(struct fb_info *info, int user)
0992 {
0993     struct nvidia_par *par = info->par;
0994 
0995     if (!par->open_count) {
0996         save_vga_x86(par);
0997         nvidia_save_vga(par, &par->initial_state);
0998     }
0999 
1000     par->open_count++;
1001     return 0;
1002 }
1003 
1004 static int nvidiafb_release(struct fb_info *info, int user)
1005 {
1006     struct nvidia_par *par = info->par;
1007     int err = 0;
1008 
1009     if (!par->open_count) {
1010         err = -EINVAL;
1011         goto done;
1012     }
1013 
1014     if (par->open_count == 1) {
1015         nvidia_write_regs(par, &par->initial_state);
1016         restore_vga_x86(par);
1017     }
1018 
1019     par->open_count--;
1020 done:
1021     return err;
1022 }
1023 
1024 static struct fb_ops nvidia_fb_ops = {
1025     .owner          = THIS_MODULE,
1026     .fb_open        = nvidiafb_open,
1027     .fb_release     = nvidiafb_release,
1028     .fb_check_var   = nvidiafb_check_var,
1029     .fb_set_par     = nvidiafb_set_par,
1030     .fb_setcolreg   = nvidiafb_setcolreg,
1031     .fb_pan_display = nvidiafb_pan_display,
1032     .fb_blank       = nvidiafb_blank,
1033     .fb_fillrect    = nvidiafb_fillrect,
1034     .fb_copyarea    = nvidiafb_copyarea,
1035     .fb_imageblit   = nvidiafb_imageblit,
1036     .fb_cursor      = nvidiafb_cursor,
1037     .fb_sync        = nvidiafb_sync,
1038 };
1039 
1040 static int nvidiafb_suspend_late(struct device *dev, pm_message_t mesg)
1041 {
1042     struct fb_info *info = dev_get_drvdata(dev);
1043     struct nvidia_par *par = info->par;
1044 
1045     if (mesg.event == PM_EVENT_PRETHAW)
1046         mesg.event = PM_EVENT_FREEZE;
1047     console_lock();
1048     par->pm_state = mesg.event;
1049 
1050     if (mesg.event & PM_EVENT_SLEEP) {
1051         fb_set_suspend(info, 1);
1052         nvidiafb_blank(FB_BLANK_POWERDOWN, info);
1053         nvidia_write_regs(par, &par->SavedReg);
1054     }
1055     dev->power.power_state = mesg;
1056 
1057     console_unlock();
1058     return 0;
1059 }
1060 
1061 static int __maybe_unused nvidiafb_suspend(struct device *dev)
1062 {
1063     return nvidiafb_suspend_late(dev, PMSG_SUSPEND);
1064 }
1065 
1066 static int __maybe_unused nvidiafb_hibernate(struct device *dev)
1067 {
1068     return nvidiafb_suspend_late(dev, PMSG_HIBERNATE);
1069 }
1070 
1071 static int __maybe_unused nvidiafb_freeze(struct device *dev)
1072 {
1073     return nvidiafb_suspend_late(dev, PMSG_FREEZE);
1074 }
1075 
1076 static int __maybe_unused nvidiafb_resume(struct device *dev)
1077 {
1078     struct fb_info *info = dev_get_drvdata(dev);
1079     struct nvidia_par *par = info->par;
1080 
1081     console_lock();
1082 
1083     par->pm_state = PM_EVENT_ON;
1084     nvidiafb_set_par(info);
1085     fb_set_suspend (info, 0);
1086     nvidiafb_blank(FB_BLANK_UNBLANK, info);
1087 
1088     console_unlock();
1089     return 0;
1090 }
1091 
1092 static const struct dev_pm_ops nvidiafb_pm_ops = {
1093 #ifdef CONFIG_PM_SLEEP
1094     .suspend    = nvidiafb_suspend,
1095     .resume     = nvidiafb_resume,
1096     .freeze     = nvidiafb_freeze,
1097     .thaw       = nvidiafb_resume,
1098     .poweroff   = nvidiafb_hibernate,
1099     .restore    = nvidiafb_resume,
1100 #endif /* CONFIG_PM_SLEEP */
1101 };
1102 
1103 static int nvidia_set_fbinfo(struct fb_info *info)
1104 {
1105     struct fb_monspecs *specs = &info->monspecs;
1106     struct fb_videomode modedb;
1107     struct nvidia_par *par = info->par;
1108     int lpitch;
1109 
1110     NVTRACE_ENTER();
1111     info->flags = FBINFO_DEFAULT
1112         | FBINFO_HWACCEL_IMAGEBLIT
1113         | FBINFO_HWACCEL_FILLRECT
1114         | FBINFO_HWACCEL_COPYAREA
1115         | FBINFO_HWACCEL_YPAN;
1116 
1117     fb_videomode_to_modelist(info->monspecs.modedb,
1118                  info->monspecs.modedb_len, &info->modelist);
1119     fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1120 
1121     switch (bpp) {
1122     case 0 ... 8:
1123         bpp = 8;
1124         break;
1125     case 9 ... 16:
1126         bpp = 16;
1127         break;
1128     default:
1129         bpp = 32;
1130         break;
1131     }
1132 
1133     if (specs->modedb != NULL) {
1134         const struct fb_videomode *mode;
1135 
1136         mode = fb_find_best_display(specs, &info->modelist);
1137         fb_videomode_to_var(&nvidiafb_default_var, mode);
1138         nvidiafb_default_var.bits_per_pixel = bpp;
1139     } else if (par->fpWidth && par->fpHeight) {
1140         char buf[16];
1141 
1142         memset(buf, 0, 16);
1143         snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1144         fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1145                  specs->modedb_len, &modedb, bpp);
1146     }
1147 
1148     if (mode_option)
1149         fb_find_mode(&nvidiafb_default_var, info, mode_option,
1150                  specs->modedb, specs->modedb_len, &modedb, bpp);
1151 
1152     info->var = nvidiafb_default_var;
1153     info->fix.visual = (info->var.bits_per_pixel == 8) ?
1154         FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1155     info->pseudo_palette = par->pseudo_palette;
1156     fb_alloc_cmap(&info->cmap, 256, 0);
1157     fb_destroy_modedb(info->monspecs.modedb);
1158     info->monspecs.modedb = NULL;
1159 
1160     /* maximize virtual vertical length */
1161     lpitch = info->var.xres_virtual *
1162         ((info->var.bits_per_pixel + 7) >> 3);
1163     info->var.yres_virtual = info->screen_size / lpitch;
1164 
1165     info->pixmap.scan_align = 4;
1166     info->pixmap.buf_align = 4;
1167     info->pixmap.access_align = 32;
1168     info->pixmap.size = 8 * 1024;
1169     info->pixmap.flags = FB_PIXMAP_SYSTEM;
1170 
1171     if (!hwcur)
1172         nvidia_fb_ops.fb_cursor = NULL;
1173 
1174     info->var.accel_flags = (!noaccel);
1175 
1176     switch (par->Architecture) {
1177     case NV_ARCH_04:
1178         info->fix.accel = FB_ACCEL_NV4;
1179         break;
1180     case NV_ARCH_10:
1181         info->fix.accel = FB_ACCEL_NV_10;
1182         break;
1183     case NV_ARCH_20:
1184         info->fix.accel = FB_ACCEL_NV_20;
1185         break;
1186     case NV_ARCH_30:
1187         info->fix.accel = FB_ACCEL_NV_30;
1188         break;
1189     case NV_ARCH_40:
1190         info->fix.accel = FB_ACCEL_NV_40;
1191         break;
1192     }
1193 
1194     NVTRACE_LEAVE();
1195 
1196     return nvidiafb_check_var(&info->var, info);
1197 }
1198 
1199 static u32 nvidia_get_chipset(struct fb_info *info)
1200 {
1201     struct nvidia_par *par = info->par;
1202     u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1203 
1204     printk(KERN_INFO PFX "Device ID: %x \n", id);
1205 
1206     if ((id & 0xfff0) == 0x00f0 ||
1207         (id & 0xfff0) == 0x02e0) {
1208         /* pci-e */
1209         id = NV_RD32(par->REGS, 0x1800);
1210 
1211         if ((id & 0x0000ffff) == 0x000010DE)
1212             id = 0x10DE0000 | (id >> 16);
1213         else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1214             id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1215                             ((id >> 8) & 0x000000ff);
1216         printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1217     }
1218 
1219     return id;
1220 }
1221 
1222 static u32 nvidia_get_arch(struct fb_info *info)
1223 {
1224     struct nvidia_par *par = info->par;
1225     u32 arch = 0;
1226 
1227     switch (par->Chipset & 0x0ff0) {
1228     case 0x0100:        /* GeForce 256 */
1229     case 0x0110:        /* GeForce2 MX */
1230     case 0x0150:        /* GeForce2 */
1231     case 0x0170:        /* GeForce4 MX */
1232     case 0x0180:        /* GeForce4 MX (8x AGP) */
1233     case 0x01A0:        /* nForce */
1234     case 0x01F0:        /* nForce2 */
1235         arch = NV_ARCH_10;
1236         break;
1237     case 0x0200:        /* GeForce3 */
1238     case 0x0250:        /* GeForce4 Ti */
1239     case 0x0280:        /* GeForce4 Ti (8x AGP) */
1240         arch = NV_ARCH_20;
1241         break;
1242     case 0x0300:        /* GeForceFX 5800 */
1243     case 0x0310:        /* GeForceFX 5600 */
1244     case 0x0320:        /* GeForceFX 5200 */
1245     case 0x0330:        /* GeForceFX 5900 */
1246     case 0x0340:        /* GeForceFX 5700 */
1247         arch = NV_ARCH_30;
1248         break;
1249     case 0x0040:        /* GeForce 6800 */
1250     case 0x00C0:        /* GeForce 6800 */
1251     case 0x0120:        /* GeForce 6800 */
1252     case 0x0140:        /* GeForce 6600 */
1253     case 0x0160:        /* GeForce 6200 */
1254     case 0x01D0:        /* GeForce 7200, 7300, 7400 */
1255     case 0x0090:        /* GeForce 7800 */
1256     case 0x0210:        /* GeForce 6800 */
1257     case 0x0220:        /* GeForce 6200 */
1258     case 0x0240:        /* GeForce 6100 */
1259     case 0x0290:        /* GeForce 7900 */
1260     case 0x0390:        /* GeForce 7600 */
1261     case 0x03D0:
1262         arch = NV_ARCH_40;
1263         break;
1264     case 0x0020:        /* TNT, TNT2 */
1265         arch = NV_ARCH_04;
1266         break;
1267     default:        /* unknown architecture */
1268         break;
1269     }
1270 
1271     return arch;
1272 }
1273 
1274 static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1275 {
1276     struct nvidia_par *par;
1277     struct fb_info *info;
1278     unsigned short cmd;
1279 
1280 
1281     NVTRACE_ENTER();
1282     assert(pd != NULL);
1283 
1284     info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1285 
1286     if (!info)
1287         goto err_out;
1288 
1289     par = info->par;
1290     par->pci_dev = pd;
1291     info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1292 
1293     if (info->pixmap.addr == NULL)
1294         goto err_out_kfree;
1295 
1296     if (pci_enable_device(pd)) {
1297         printk(KERN_ERR PFX "cannot enable PCI device\n");
1298         goto err_out_enable;
1299     }
1300 
1301     if (pci_request_regions(pd, "nvidiafb")) {
1302         printk(KERN_ERR PFX "cannot request PCI regions\n");
1303         goto err_out_enable;
1304     }
1305 
1306     par->FlatPanel = flatpanel;
1307     if (flatpanel == 1)
1308         printk(KERN_INFO PFX "flatpanel support enabled\n");
1309     par->FPDither = fpdither;
1310 
1311     par->CRTCnumber = forceCRTC;
1312     par->FpScale = (!noscale);
1313     par->paneltweak = paneltweak;
1314     par->reverse_i2c = reverse_i2c;
1315 
1316     /* enable IO and mem if not already done */
1317     pci_read_config_word(pd, PCI_COMMAND, &cmd);
1318     cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1319     pci_write_config_word(pd, PCI_COMMAND, cmd);
1320 
1321     nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1322     nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1323     nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1324 
1325     par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1326 
1327     if (!par->REGS) {
1328         printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1329         goto err_out_free_base0;
1330     }
1331 
1332     par->Chipset = nvidia_get_chipset(info);
1333     par->Architecture = nvidia_get_arch(info);
1334 
1335     if (par->Architecture == 0) {
1336         printk(KERN_ERR PFX "unknown NV_ARCH\n");
1337         goto err_out_arch;
1338     }
1339 
1340     sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1341 
1342     if (NVCommonSetup(info))
1343         goto err_out_arch;
1344 
1345     par->FbAddress = nvidiafb_fix.smem_start;
1346     par->FbMapSize = par->RamAmountKBytes * 1024;
1347     if (vram && vram * 1024 * 1024 < par->FbMapSize)
1348         par->FbMapSize = vram * 1024 * 1024;
1349 
1350     /* Limit amount of vram to 64 MB */
1351     if (par->FbMapSize > 64 * 1024 * 1024)
1352         par->FbMapSize = 64 * 1024 * 1024;
1353 
1354     if(par->Architecture >= NV_ARCH_40)
1355             par->FbUsableSize = par->FbMapSize - (560 * 1024);
1356     else
1357         par->FbUsableSize = par->FbMapSize - (128 * 1024);
1358     par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1359         16 * 1024;
1360     par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1361     par->CursorStart = par->FbUsableSize + (32 * 1024);
1362 
1363     info->screen_base = ioremap_wc(nvidiafb_fix.smem_start,
1364                        par->FbMapSize);
1365     info->screen_size = par->FbUsableSize;
1366     nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1367 
1368     if (!info->screen_base) {
1369         printk(KERN_ERR PFX "cannot ioremap FB base\n");
1370         goto err_out_free_base1;
1371     }
1372 
1373     par->FbStart = info->screen_base;
1374 
1375     if (!nomtrr)
1376         par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start,
1377                           par->RamAmountKBytes * 1024);
1378 
1379     info->fbops = &nvidia_fb_ops;
1380     info->fix = nvidiafb_fix;
1381 
1382     if (nvidia_set_fbinfo(info) < 0) {
1383         printk(KERN_ERR PFX "error setting initial video mode\n");
1384         goto err_out_iounmap_fb;
1385     }
1386 
1387     nvidia_save_vga(par, &par->SavedReg);
1388 
1389     pci_set_drvdata(pd, info);
1390 
1391     if (backlight)
1392         nvidia_bl_init(par);
1393 
1394     if (register_framebuffer(info) < 0) {
1395         printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1396         goto err_out_iounmap_fb;
1397     }
1398 
1399 
1400     printk(KERN_INFO PFX
1401            "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1402            info->fix.id,
1403            par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1404 
1405     NVTRACE_LEAVE();
1406     return 0;
1407 
1408 err_out_iounmap_fb:
1409     iounmap(info->screen_base);
1410 err_out_free_base1:
1411     fb_destroy_modedb(info->monspecs.modedb);
1412     nvidia_delete_i2c_busses(par);
1413 err_out_arch:
1414     iounmap(par->REGS);
1415  err_out_free_base0:
1416     pci_release_regions(pd);
1417 err_out_enable:
1418     kfree(info->pixmap.addr);
1419 err_out_kfree:
1420     framebuffer_release(info);
1421 err_out:
1422     return -ENODEV;
1423 }
1424 
1425 static void nvidiafb_remove(struct pci_dev *pd)
1426 {
1427     struct fb_info *info = pci_get_drvdata(pd);
1428     struct nvidia_par *par = info->par;
1429 
1430     NVTRACE_ENTER();
1431 
1432     unregister_framebuffer(info);
1433 
1434     nvidia_bl_exit(par);
1435     arch_phys_wc_del(par->wc_cookie);
1436     iounmap(info->screen_base);
1437     fb_destroy_modedb(info->monspecs.modedb);
1438     nvidia_delete_i2c_busses(par);
1439     iounmap(par->REGS);
1440     pci_release_regions(pd);
1441     kfree(info->pixmap.addr);
1442     framebuffer_release(info);
1443     NVTRACE_LEAVE();
1444 }
1445 
1446 /* ------------------------------------------------------------------------- *
1447  *
1448  * initialization
1449  *
1450  * ------------------------------------------------------------------------- */
1451 
1452 #ifndef MODULE
1453 static int nvidiafb_setup(char *options)
1454 {
1455     char *this_opt;
1456 
1457     NVTRACE_ENTER();
1458     if (!options || !*options)
1459         return 0;
1460 
1461     while ((this_opt = strsep(&options, ",")) != NULL) {
1462         if (!strncmp(this_opt, "forceCRTC", 9)) {
1463             char *p;
1464 
1465             p = this_opt + 9;
1466             if (!*p || !*(++p))
1467                 continue;
1468             forceCRTC = *p - '0';
1469             if (forceCRTC < 0 || forceCRTC > 1)
1470                 forceCRTC = -1;
1471         } else if (!strncmp(this_opt, "flatpanel", 9)) {
1472             flatpanel = 1;
1473         } else if (!strncmp(this_opt, "hwcur", 5)) {
1474             hwcur = 1;
1475         } else if (!strncmp(this_opt, "noaccel", 6)) {
1476             noaccel = 1;
1477         } else if (!strncmp(this_opt, "noscale", 7)) {
1478             noscale = 1;
1479         } else if (!strncmp(this_opt, "reverse_i2c", 11)) {
1480             reverse_i2c = 1;
1481         } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1482             paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1483         } else if (!strncmp(this_opt, "vram:", 5)) {
1484             vram = simple_strtoul(this_opt+5, NULL, 0);
1485         } else if (!strncmp(this_opt, "backlight:", 10)) {
1486             backlight = simple_strtoul(this_opt+10, NULL, 0);
1487         } else if (!strncmp(this_opt, "nomtrr", 6)) {
1488             nomtrr = true;
1489         } else if (!strncmp(this_opt, "fpdither:", 9)) {
1490             fpdither = simple_strtol(this_opt+9, NULL, 0);
1491         } else if (!strncmp(this_opt, "bpp:", 4)) {
1492             bpp = simple_strtoul(this_opt+4, NULL, 0);
1493         } else
1494             mode_option = this_opt;
1495     }
1496     NVTRACE_LEAVE();
1497     return 0;
1498 }
1499 #endif              /* !MODULE */
1500 
1501 static struct pci_driver nvidiafb_driver = {
1502     .name      = "nvidiafb",
1503     .id_table  = nvidiafb_pci_tbl,
1504     .probe     = nvidiafb_probe,
1505     .driver.pm = &nvidiafb_pm_ops,
1506     .remove    = nvidiafb_remove,
1507 };
1508 
1509 /* ------------------------------------------------------------------------- *
1510  *
1511  * modularization
1512  *
1513  * ------------------------------------------------------------------------- */
1514 
1515 static int nvidiafb_init(void)
1516 {
1517 #ifndef MODULE
1518     char *option = NULL;
1519 
1520     if (fb_get_options("nvidiafb", &option))
1521         return -ENODEV;
1522     nvidiafb_setup(option);
1523 #endif
1524     return pci_register_driver(&nvidiafb_driver);
1525 }
1526 
1527 module_init(nvidiafb_init);
1528 
1529 static void __exit nvidiafb_exit(void)
1530 {
1531     pci_unregister_driver(&nvidiafb_driver);
1532 }
1533 
1534 module_exit(nvidiafb_exit);
1535 
1536 module_param(flatpanel, int, 0);
1537 MODULE_PARM_DESC(flatpanel,
1538          "Enables experimental flat panel support for some chipsets. "
1539          "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1540 module_param(fpdither, int, 0);
1541 MODULE_PARM_DESC(fpdither,
1542          "Enables dithering of flat panel for 6 bits panels. "
1543          "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1544 module_param(hwcur, int, 0);
1545 MODULE_PARM_DESC(hwcur,
1546          "Enables hardware cursor implementation. (0 or 1=enabled) "
1547          "(default=0)");
1548 module_param(noaccel, int, 0);
1549 MODULE_PARM_DESC(noaccel,
1550          "Disables hardware acceleration. (0 or 1=disable) "
1551          "(default=0)");
1552 module_param(noscale, int, 0);
1553 MODULE_PARM_DESC(noscale,
1554          "Disables screen scaling. (0 or 1=disable) "
1555          "(default=0, do scaling)");
1556 module_param(paneltweak, int, 0);
1557 MODULE_PARM_DESC(paneltweak,
1558          "Tweak display settings for flatpanels. "
1559          "(default=0, no tweaks)");
1560 module_param(forceCRTC, int, 0);
1561 MODULE_PARM_DESC(forceCRTC,
1562          "Forces usage of a particular CRTC in case autodetection "
1563          "fails. (0 or 1) (default=autodetect)");
1564 module_param(vram, int, 0);
1565 MODULE_PARM_DESC(vram,
1566          "amount of framebuffer memory to remap in MiB"
1567          "(default=0 - remap entire memory)");
1568 module_param(mode_option, charp, 0);
1569 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1570 module_param(bpp, int, 0);
1571 MODULE_PARM_DESC(bpp, "pixel width in bits"
1572          "(default=8)");
1573 module_param(reverse_i2c, int, 0);
1574 MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus");
1575 module_param(nomtrr, bool, false);
1576 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1577          "(default=0)");
1578 
1579 MODULE_AUTHOR("Antonino Daplas");
1580 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1581 MODULE_LICENSE("GPL");
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