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0001  /***************************************************************************\
0002 |*                                                                           *|
0003 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
0004 |*                                                                           *|
0005 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
0006 |*     international laws.  Users and possessors of this source code are     *|
0007 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
0008 |*     use this code in individual and commercial software.                  *|
0009 |*                                                                           *|
0010 |*     Any use of this source code must include,  in the user documenta-     *|
0011 |*     tion and  internal comments to the code,  notices to the end user     *|
0012 |*     as follows:                                                           *|
0013 |*                                                                           *|
0014 |*       Copyright 1993-2003 NVIDIA, Corporation.  All rights reserved.      *|
0015 |*                                                                           *|
0016 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
0017 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
0018 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
0019 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
0020 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
0021 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
0022 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
0023 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
0024 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
0025 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
0026 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
0027 |*                                                                           *|
0028 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
0029 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
0030 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
0031 |*     computer  software  documentation,"  as such  terms  are  used in     *|
0032 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
0033 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
0034 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
0035 |*     all U.S. Government End Users  acquire the source code  with only     *|
0036 |*     those rights set forth herein.                                        *|
0037 |*                                                                           *|
0038  \***************************************************************************/
0039 
0040 /*
0041  * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
0042  * XFree86 'nv' driver, this source code is provided under MIT-style licensing
0043  * where the source code is provided "as is" without warranty of any kind.
0044  * The only usage restriction is for the copyright notices to be retained
0045  * whenever code is used.
0046  *
0047  * Antonino Daplas <adaplas@pol.net> 2005-03-11
0048  */
0049 
0050 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
0051 
0052 #include <linux/pci.h>
0053 #include "nv_type.h"
0054 #include "nv_local.h"
0055 #include "nv_proto.h"
0056 
0057 void NVLockUnlock(struct nvidia_par *par, int Lock)
0058 {
0059     u8 cr11;
0060 
0061     VGA_WR08(par->PCIO, 0x3D4, 0x1F);
0062     VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
0063 
0064     VGA_WR08(par->PCIO, 0x3D4, 0x11);
0065     cr11 = VGA_RD08(par->PCIO, 0x3D5);
0066     if (Lock)
0067         cr11 |= 0x80;
0068     else
0069         cr11 &= ~0x80;
0070     VGA_WR08(par->PCIO, 0x3D5, cr11);
0071 }
0072 
0073 int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
0074 {
0075     int cur = par->CurrentState->cursor1;
0076 
0077     par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
0078         (ShowHide & 0x01);
0079     VGA_WR08(par->PCIO, 0x3D4, 0x31);
0080     VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
0081 
0082     if (par->Architecture == NV_ARCH_40)
0083         NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
0084 
0085     return (cur & 0x01);
0086 }
0087 
0088 /****************************************************************************\
0089 *                                                                            *
0090 * The video arbitration routines calculate some "magic" numbers.  Fixes      *
0091 * the snow seen when accessing the framebuffer without it.                   *
0092 * It just works (I hope).                                                    *
0093 *                                                                            *
0094 \****************************************************************************/
0095 
0096 typedef struct {
0097     int graphics_lwm;
0098     int video_lwm;
0099     int graphics_burst_size;
0100     int video_burst_size;
0101     int valid;
0102 } nv4_fifo_info;
0103 
0104 typedef struct {
0105     int pclk_khz;
0106     int mclk_khz;
0107     int nvclk_khz;
0108     char mem_page_miss;
0109     char mem_latency;
0110     int memory_width;
0111     char enable_video;
0112     char gr_during_vid;
0113     char pix_bpp;
0114     char mem_aligned;
0115     char enable_mp;
0116 } nv4_sim_state;
0117 
0118 typedef struct {
0119     int graphics_lwm;
0120     int video_lwm;
0121     int graphics_burst_size;
0122     int video_burst_size;
0123     int valid;
0124 } nv10_fifo_info;
0125 
0126 typedef struct {
0127     int pclk_khz;
0128     int mclk_khz;
0129     int nvclk_khz;
0130     char mem_page_miss;
0131     char mem_latency;
0132     u32 memory_type;
0133     int memory_width;
0134     char enable_video;
0135     char gr_during_vid;
0136     char pix_bpp;
0137     char mem_aligned;
0138     char enable_mp;
0139 } nv10_sim_state;
0140 
0141 static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
0142             unsigned int *NVClk)
0143 {
0144     unsigned int pll, N, M, MB, NB, P;
0145 
0146     if (par->Architecture >= NV_ARCH_40) {
0147         pll = NV_RD32(par->PMC, 0x4020);
0148         P = (pll >> 16) & 0x07;
0149         pll = NV_RD32(par->PMC, 0x4024);
0150         M = pll & 0xFF;
0151         N = (pll >> 8) & 0xFF;
0152         if (((par->Chipset & 0xfff0) == 0x0290) ||
0153             ((par->Chipset & 0xfff0) == 0x0390)) {
0154             MB = 1;
0155             NB = 1;
0156         } else {
0157             MB = (pll >> 16) & 0xFF;
0158             NB = (pll >> 24) & 0xFF;
0159         }
0160         *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
0161 
0162         pll = NV_RD32(par->PMC, 0x4000);
0163         P = (pll >> 16) & 0x07;
0164         pll = NV_RD32(par->PMC, 0x4004);
0165         M = pll & 0xFF;
0166         N = (pll >> 8) & 0xFF;
0167         MB = (pll >> 16) & 0xFF;
0168         NB = (pll >> 24) & 0xFF;
0169 
0170         *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
0171     } else if (par->twoStagePLL) {
0172         pll = NV_RD32(par->PRAMDAC0, 0x0504);
0173         M = pll & 0xFF;
0174         N = (pll >> 8) & 0xFF;
0175         P = (pll >> 16) & 0x0F;
0176         pll = NV_RD32(par->PRAMDAC0, 0x0574);
0177         if (pll & 0x80000000) {
0178             MB = pll & 0xFF;
0179             NB = (pll >> 8) & 0xFF;
0180         } else {
0181             MB = 1;
0182             NB = 1;
0183         }
0184         *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
0185 
0186         pll = NV_RD32(par->PRAMDAC0, 0x0500);
0187         M = pll & 0xFF;
0188         N = (pll >> 8) & 0xFF;
0189         P = (pll >> 16) & 0x0F;
0190         pll = NV_RD32(par->PRAMDAC0, 0x0570);
0191         if (pll & 0x80000000) {
0192             MB = pll & 0xFF;
0193             NB = (pll >> 8) & 0xFF;
0194         } else {
0195             MB = 1;
0196             NB = 1;
0197         }
0198         *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
0199     } else
0200         if (((par->Chipset & 0x0ff0) == 0x0300) ||
0201         ((par->Chipset & 0x0ff0) == 0x0330)) {
0202         pll = NV_RD32(par->PRAMDAC0, 0x0504);
0203         M = pll & 0x0F;
0204         N = (pll >> 8) & 0xFF;
0205         P = (pll >> 16) & 0x07;
0206         if (pll & 0x00000080) {
0207             MB = (pll >> 4) & 0x07;
0208             NB = (pll >> 19) & 0x1f;
0209         } else {
0210             MB = 1;
0211             NB = 1;
0212         }
0213         *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
0214 
0215         pll = NV_RD32(par->PRAMDAC0, 0x0500);
0216         M = pll & 0x0F;
0217         N = (pll >> 8) & 0xFF;
0218         P = (pll >> 16) & 0x07;
0219         if (pll & 0x00000080) {
0220             MB = (pll >> 4) & 0x07;
0221             NB = (pll >> 19) & 0x1f;
0222         } else {
0223             MB = 1;
0224             NB = 1;
0225         }
0226         *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
0227     } else {
0228         pll = NV_RD32(par->PRAMDAC0, 0x0504);
0229         M = pll & 0xFF;
0230         N = (pll >> 8) & 0xFF;
0231         P = (pll >> 16) & 0x0F;
0232         *MClk = (N * par->CrystalFreqKHz / M) >> P;
0233 
0234         pll = NV_RD32(par->PRAMDAC0, 0x0500);
0235         M = pll & 0xFF;
0236         N = (pll >> 8) & 0xFF;
0237         P = (pll >> 16) & 0x0F;
0238         *NVClk = (N * par->CrystalFreqKHz / M) >> P;
0239     }
0240 }
0241 
0242 static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
0243 {
0244     int data, pagemiss, cas, width, video_enable, bpp;
0245     int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
0246     int found, mclk_extra, mclk_loop, cbs, m1, p1;
0247     int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
0248     int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
0249     int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
0250 
0251     fifo->valid = 1;
0252     pclk_freq = arb->pclk_khz;
0253     mclk_freq = arb->mclk_khz;
0254     nvclk_freq = arb->nvclk_khz;
0255     pagemiss = arb->mem_page_miss;
0256     cas = arb->mem_latency;
0257     width = arb->memory_width >> 6;
0258     video_enable = arb->enable_video;
0259     bpp = arb->pix_bpp;
0260     mp_enable = arb->enable_mp;
0261     clwm = 0;
0262     vlwm = 0;
0263     cbs = 128;
0264     pclks = 2;
0265     nvclks = 2;
0266     nvclks += 2;
0267     nvclks += 1;
0268     mclks = 5;
0269     mclks += 3;
0270     mclks += 1;
0271     mclks += cas;
0272     mclks += 1;
0273     mclks += 1;
0274     mclks += 1;
0275     mclks += 1;
0276     mclk_extra = 3;
0277     nvclks += 2;
0278     nvclks += 1;
0279     nvclks += 1;
0280     nvclks += 1;
0281     if (mp_enable)
0282         mclks += 4;
0283     nvclks += 0;
0284     pclks += 0;
0285     found = 0;
0286     vbs = 0;
0287     while (found != 1) {
0288         fifo->valid = 1;
0289         found = 1;
0290         mclk_loop = mclks + mclk_extra;
0291         us_m = mclk_loop * 1000 * 1000 / mclk_freq;
0292         us_n = nvclks * 1000 * 1000 / nvclk_freq;
0293         us_p = nvclks * 1000 * 1000 / pclk_freq;
0294         if (video_enable) {
0295             video_drain_rate = pclk_freq * 2;
0296             crtc_drain_rate = pclk_freq * bpp / 8;
0297             vpagemiss = 2;
0298             vpagemiss += 1;
0299             crtpagemiss = 2;
0300             vpm_us =
0301                 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
0302             if (nvclk_freq * 2 > mclk_freq * width)
0303                 video_fill_us =
0304                     cbs * 1000 * 1000 / 16 / nvclk_freq;
0305             else
0306                 video_fill_us =
0307                     cbs * 1000 * 1000 / (8 * width) /
0308                     mclk_freq;
0309             us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
0310             vlwm = us_video * video_drain_rate / (1000 * 1000);
0311             vlwm++;
0312             vbs = 128;
0313             if (vlwm > 128)
0314                 vbs = 64;
0315             if (vlwm > (256 - 64))
0316                 vbs = 32;
0317             if (nvclk_freq * 2 > mclk_freq * width)
0318                 video_fill_us =
0319                     vbs * 1000 * 1000 / 16 / nvclk_freq;
0320             else
0321                 video_fill_us =
0322                     vbs * 1000 * 1000 / (8 * width) /
0323                     mclk_freq;
0324             cpm_us =
0325                 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
0326             us_crt =
0327                 us_video + video_fill_us + cpm_us + us_m + us_n +
0328                 us_p;
0329             clwm = us_crt * crtc_drain_rate / (1000 * 1000);
0330             clwm++;
0331         } else {
0332             crtc_drain_rate = pclk_freq * bpp / 8;
0333             crtpagemiss = 2;
0334             crtpagemiss += 1;
0335             cpm_us =
0336                 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
0337             us_crt = cpm_us + us_m + us_n + us_p;
0338             clwm = us_crt * crtc_drain_rate / (1000 * 1000);
0339             clwm++;
0340         }
0341         m1 = clwm + cbs - 512;
0342         p1 = m1 * pclk_freq / mclk_freq;
0343         p1 = p1 * bpp / 8;
0344         if ((p1 < m1) && (m1 > 0)) {
0345             fifo->valid = 0;
0346             found = 0;
0347             if (mclk_extra == 0)
0348                 found = 1;
0349             mclk_extra--;
0350         } else if (video_enable) {
0351             if ((clwm > 511) || (vlwm > 255)) {
0352                 fifo->valid = 0;
0353                 found = 0;
0354                 if (mclk_extra == 0)
0355                     found = 1;
0356                 mclk_extra--;
0357             }
0358         } else {
0359             if (clwm > 519) {
0360                 fifo->valid = 0;
0361                 found = 0;
0362                 if (mclk_extra == 0)
0363                     found = 1;
0364                 mclk_extra--;
0365             }
0366         }
0367         if (clwm < 384)
0368             clwm = 384;
0369         if (vlwm < 128)
0370             vlwm = 128;
0371         data = (int)(clwm);
0372         fifo->graphics_lwm = data;
0373         fifo->graphics_burst_size = 128;
0374         data = (int)((vlwm + 15));
0375         fifo->video_lwm = data;
0376         fifo->video_burst_size = vbs;
0377     }
0378 }
0379 
0380 static void nv4UpdateArbitrationSettings(unsigned VClk,
0381                      unsigned pixelDepth,
0382                      unsigned *burst,
0383                      unsigned *lwm, struct nvidia_par *par)
0384 {
0385     nv4_fifo_info fifo_data;
0386     nv4_sim_state sim_data;
0387     unsigned int MClk, NVClk, cfg1;
0388 
0389     nvGetClocks(par, &MClk, &NVClk);
0390 
0391     cfg1 = NV_RD32(par->PFB, 0x00000204);
0392     sim_data.pix_bpp = (char)pixelDepth;
0393     sim_data.enable_video = 0;
0394     sim_data.enable_mp = 0;
0395     sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
0396         128 : 64;
0397     sim_data.mem_latency = (char)cfg1 & 0x0F;
0398     sim_data.mem_aligned = 1;
0399     sim_data.mem_page_miss =
0400         (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
0401     sim_data.gr_during_vid = 0;
0402     sim_data.pclk_khz = VClk;
0403     sim_data.mclk_khz = MClk;
0404     sim_data.nvclk_khz = NVClk;
0405     nv4CalcArbitration(&fifo_data, &sim_data);
0406     if (fifo_data.valid) {
0407         int b = fifo_data.graphics_burst_size >> 4;
0408         *burst = 0;
0409         while (b >>= 1)
0410             (*burst)++;
0411         *lwm = fifo_data.graphics_lwm >> 3;
0412     }
0413 }
0414 
0415 static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
0416 {
0417     int data, pagemiss, width, video_enable, bpp;
0418     int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
0419     int nvclk_fill;
0420     int found, mclk_extra, mclk_loop, cbs, m1;
0421     int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
0422     int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
0423     int vus_m;
0424     int vpm_us, us_video, cpm_us, us_crt, clwm;
0425     int clwm_rnd_down;
0426     int m2us, us_pipe_min, p1clk, p2;
0427     int min_mclk_extra;
0428     int us_min_mclk_extra;
0429 
0430     fifo->valid = 1;
0431     pclk_freq = arb->pclk_khz;  /* freq in KHz */
0432     mclk_freq = arb->mclk_khz;
0433     nvclk_freq = arb->nvclk_khz;
0434     pagemiss = arb->mem_page_miss;
0435     width = arb->memory_width / 64;
0436     video_enable = arb->enable_video;
0437     bpp = arb->pix_bpp;
0438     mp_enable = arb->enable_mp;
0439     clwm = 0;
0440 
0441     cbs = 512;
0442 
0443     pclks = 4;  /* lwm detect. */
0444 
0445     nvclks = 3; /* lwm -> sync. */
0446     nvclks += 2;    /* fbi bus cycles (1 req + 1 busy) */
0447     /* 2 edge sync.  may be very close to edge so just put one. */
0448     mclks = 1;
0449     mclks += 1; /* arb_hp_req */
0450     mclks += 5; /* ap_hp_req   tiling pipeline */
0451 
0452     mclks += 2; /* tc_req     latency fifo */
0453     mclks += 2; /* fb_cas_n_  memory request to fbio block */
0454     mclks += 7; /* sm_d_rdv   data returned from fbio block */
0455 
0456     /* fb.rd.d.Put_gc   need to accumulate 256 bits for read */
0457     if (arb->memory_type == 0)
0458         if (arb->memory_width == 64)    /* 64 bit bus */
0459             mclks += 4;
0460         else
0461             mclks += 2;
0462     else if (arb->memory_width == 64)   /* 64 bit bus */
0463         mclks += 2;
0464     else
0465         mclks += 1;
0466 
0467     if ((!video_enable) && (arb->memory_width == 128)) {
0468         mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
0469         min_mclk_extra = 17;
0470     } else {
0471         mclk_extra = (bpp == 32) ? 8 : 4;   /* Margin of error */
0472         /* mclk_extra = 4; *//* Margin of error */
0473         min_mclk_extra = 18;
0474     }
0475 
0476     /* 2 edge sync.  may be very close to edge so just put one. */
0477     nvclks += 1;
0478     nvclks += 1;        /* fbi_d_rdv_n */
0479     nvclks += 1;        /* Fbi_d_rdata */
0480     nvclks += 1;        /* crtfifo load */
0481 
0482     if (mp_enable)
0483         mclks += 4; /* Mp can get in with a burst of 8. */
0484     /* Extra clocks determined by heuristics */
0485 
0486     nvclks += 0;
0487     pclks += 0;
0488     found = 0;
0489     while (found != 1) {
0490         fifo->valid = 1;
0491         found = 1;
0492         mclk_loop = mclks + mclk_extra;
0493         /* Mclk latency in us */
0494         us_m = mclk_loop * 1000 * 1000 / mclk_freq;
0495         /* Minimum Mclk latency in us */
0496         us_m_min = mclks * 1000 * 1000 / mclk_freq;
0497         us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
0498         /* nvclk latency in us */
0499         us_n = nvclks * 1000 * 1000 / nvclk_freq;
0500         /* nvclk latency in us */
0501         us_p = pclks * 1000 * 1000 / pclk_freq;
0502         us_pipe_min = us_m_min + us_n + us_p;
0503 
0504         /* Mclk latency in us */
0505         vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
0506 
0507         if (video_enable) {
0508             crtc_drain_rate = pclk_freq * bpp / 8;  /* MB/s */
0509 
0510             vpagemiss = 1;  /* self generating page miss */
0511             vpagemiss += 1; /* One higher priority before */
0512 
0513             crtpagemiss = 2;    /* self generating page miss */
0514             if (mp_enable)
0515                 crtpagemiss += 1;   /* if MA0 conflict */
0516 
0517             vpm_us =
0518                 (vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
0519 
0520             /* Video has separate read return path */
0521             us_video = vpm_us + vus_m;
0522 
0523             cpm_us =
0524                 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
0525             /* Wait for video */
0526             us_crt = us_video
0527                 + cpm_us    /* CRT Page miss */
0528                 + us_m + us_n + us_p    /* other latency */
0529                 ;
0530 
0531             clwm = us_crt * crtc_drain_rate / (1000 * 1000);
0532             /* fixed point <= float_point - 1.  Fixes that */
0533             clwm++;
0534         } else {
0535             /* bpp * pclk/8 */
0536             crtc_drain_rate = pclk_freq * bpp / 8;
0537 
0538             crtpagemiss = 1;    /* self generating page miss */
0539             crtpagemiss += 1;   /* MA0 page miss */
0540             if (mp_enable)
0541                 crtpagemiss += 1;   /* if MA0 conflict */
0542             cpm_us =
0543                 crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
0544             us_crt = cpm_us + us_m + us_n + us_p;
0545             clwm = us_crt * crtc_drain_rate / (1000 * 1000);
0546             /* fixed point <= float_point - 1.  Fixes that */
0547             clwm++;
0548 
0549             /* Finally, a heuristic check when width == 64 bits */
0550             if (width == 1) {
0551                 nvclk_fill = nvclk_freq * 8;
0552                 if (crtc_drain_rate * 100 >= nvclk_fill * 102)
0553                     /*Large number to fail */
0554                     clwm = 0xfff;
0555 
0556                 else if (crtc_drain_rate * 100 >=
0557                      nvclk_fill * 98) {
0558                     clwm = 1024;
0559                     cbs = 512;
0560                 }
0561             }
0562         }
0563 
0564         /*
0565            Overfill check:
0566          */
0567 
0568         clwm_rnd_down = ((int)clwm / 8) * 8;
0569         if (clwm_rnd_down < clwm)
0570             clwm += 8;
0571 
0572         m1 = clwm + cbs - 1024; /* Amount of overfill */
0573         m2us = us_pipe_min + us_min_mclk_extra;
0574 
0575         /* pclk cycles to drain */
0576         p1clk = m2us * pclk_freq / (1000 * 1000);
0577         p2 = p1clk * bpp / 8;   /* bytes drained. */
0578 
0579         if ((p2 < m1) && (m1 > 0)) {
0580             fifo->valid = 0;
0581             found = 0;
0582             if (min_mclk_extra == 0) {
0583                 if (cbs <= 32) {
0584                     /* Can't adjust anymore! */
0585                     found = 1;
0586                 } else {
0587                     /* reduce the burst size */
0588                     cbs = cbs / 2;
0589                 }
0590             } else {
0591                 min_mclk_extra--;
0592             }
0593         } else {
0594             if (clwm > 1023) {  /* Have some margin */
0595                 fifo->valid = 0;
0596                 found = 0;
0597                 if (min_mclk_extra == 0)
0598                     /* Can't adjust anymore! */
0599                     found = 1;
0600                 else
0601                     min_mclk_extra--;
0602             }
0603         }
0604 
0605         if (clwm < (1024 - cbs + 8))
0606             clwm = 1024 - cbs + 8;
0607         data = (int)(clwm);
0608         /*  printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
0609             clwm, data ); */
0610         fifo->graphics_lwm = data;
0611         fifo->graphics_burst_size = cbs;
0612 
0613         fifo->video_lwm = 1024;
0614         fifo->video_burst_size = 512;
0615     }
0616 }
0617 
0618 static void nv10UpdateArbitrationSettings(unsigned VClk,
0619                       unsigned pixelDepth,
0620                       unsigned *burst,
0621                       unsigned *lwm,
0622                       struct nvidia_par *par)
0623 {
0624     nv10_fifo_info fifo_data;
0625     nv10_sim_state sim_data;
0626     unsigned int MClk, NVClk, cfg1;
0627 
0628     nvGetClocks(par, &MClk, &NVClk);
0629 
0630     cfg1 = NV_RD32(par->PFB, 0x0204);
0631     sim_data.pix_bpp = (char)pixelDepth;
0632     sim_data.enable_video = 1;
0633     sim_data.enable_mp = 0;
0634     sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
0635     sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
0636         128 : 64;
0637     sim_data.mem_latency = (char)cfg1 & 0x0F;
0638     sim_data.mem_aligned = 1;
0639     sim_data.mem_page_miss =
0640         (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
0641     sim_data.gr_during_vid = 0;
0642     sim_data.pclk_khz = VClk;
0643     sim_data.mclk_khz = MClk;
0644     sim_data.nvclk_khz = NVClk;
0645     nv10CalcArbitration(&fifo_data, &sim_data);
0646     if (fifo_data.valid) {
0647         int b = fifo_data.graphics_burst_size >> 4;
0648         *burst = 0;
0649         while (b >>= 1)
0650             (*burst)++;
0651         *lwm = fifo_data.graphics_lwm >> 3;
0652     }
0653 }
0654 
0655 static void nv30UpdateArbitrationSettings (
0656     struct nvidia_par *par,
0657     unsigned int      *burst,
0658     unsigned int      *lwm
0659 )
0660 {
0661     unsigned int MClk, NVClk;
0662     unsigned int fifo_size, burst_size, graphics_lwm;
0663 
0664     fifo_size = 2048;
0665     burst_size = 512;
0666     graphics_lwm = fifo_size - burst_size;
0667 
0668     nvGetClocks(par, &MClk, &NVClk);
0669 
0670     *burst = 0;
0671     burst_size >>= 5;
0672     while(burst_size >>= 1) (*burst)++;
0673     *lwm = graphics_lwm >> 3;
0674 }
0675 
0676 static void nForceUpdateArbitrationSettings(unsigned VClk,
0677                         unsigned pixelDepth,
0678                         unsigned *burst,
0679                         unsigned *lwm,
0680                         struct nvidia_par *par)
0681 {
0682     nv10_fifo_info fifo_data;
0683     nv10_sim_state sim_data;
0684     unsigned int M, N, P, pll, MClk, NVClk, memctrl;
0685     struct pci_dev *dev;
0686     int domain = pci_domain_nr(par->pci_dev->bus);
0687 
0688     if ((par->Chipset & 0x0FF0) == 0x01A0) {
0689         unsigned int uMClkPostDiv;
0690         dev = pci_get_domain_bus_and_slot(domain, 0, 3);
0691         pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
0692         uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
0693 
0694         if (!uMClkPostDiv)
0695             uMClkPostDiv = 4;
0696         MClk = 400000 / uMClkPostDiv;
0697     } else {
0698         dev = pci_get_domain_bus_and_slot(domain, 0, 5);
0699         pci_read_config_dword(dev, 0x4c, &MClk);
0700         MClk /= 1000;
0701     }
0702     pci_dev_put(dev);
0703     pll = NV_RD32(par->PRAMDAC0, 0x0500);
0704     M = (pll >> 0) & 0xFF;
0705     N = (pll >> 8) & 0xFF;
0706     P = (pll >> 16) & 0x0F;
0707     NVClk = (N * par->CrystalFreqKHz / M) >> P;
0708     sim_data.pix_bpp = (char)pixelDepth;
0709     sim_data.enable_video = 0;
0710     sim_data.enable_mp = 0;
0711     dev = pci_get_domain_bus_and_slot(domain, 0, 1);
0712     pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
0713     pci_dev_put(dev);
0714     sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
0715     sim_data.memory_width = 64;
0716 
0717     dev = pci_get_domain_bus_and_slot(domain, 0, 3);
0718     pci_read_config_dword(dev, 0, &memctrl);
0719     pci_dev_put(dev);
0720     memctrl >>= 16;
0721 
0722     if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
0723         u32 dimm[3];
0724 
0725         dev = pci_get_domain_bus_and_slot(domain, 0, 2);
0726         pci_read_config_dword(dev, 0x40, &dimm[0]);
0727         dimm[0] = (dimm[0] >> 8) & 0x4f;
0728         pci_read_config_dword(dev, 0x44, &dimm[1]);
0729         dimm[1] = (dimm[1] >> 8) & 0x4f;
0730         pci_read_config_dword(dev, 0x48, &dimm[2]);
0731         dimm[2] = (dimm[2] >> 8) & 0x4f;
0732 
0733         if ((dimm[0] + dimm[1]) != dimm[2]) {
0734             printk("nvidiafb: your nForce DIMMs are not arranged "
0735                    "in optimal banks!\n");
0736         }
0737         pci_dev_put(dev);
0738     }
0739 
0740     sim_data.mem_latency = 3;
0741     sim_data.mem_aligned = 1;
0742     sim_data.mem_page_miss = 10;
0743     sim_data.gr_during_vid = 0;
0744     sim_data.pclk_khz = VClk;
0745     sim_data.mclk_khz = MClk;
0746     sim_data.nvclk_khz = NVClk;
0747     nv10CalcArbitration(&fifo_data, &sim_data);
0748     if (fifo_data.valid) {
0749         int b = fifo_data.graphics_burst_size >> 4;
0750         *burst = 0;
0751         while (b >>= 1)
0752             (*burst)++;
0753         *lwm = fifo_data.graphics_lwm >> 3;
0754     }
0755 }
0756 
0757 /****************************************************************************\
0758 *                                                                            *
0759 *                          RIVA Mode State Routines                          *
0760 *                                                                            *
0761 \****************************************************************************/
0762 
0763 /*
0764  * Calculate the Video Clock parameters for the PLL.
0765  */
0766 static void CalcVClock(int clockIn,
0767                int *clockOut, u32 * pllOut, struct nvidia_par *par)
0768 {
0769     unsigned lowM, highM;
0770     unsigned DeltaNew, DeltaOld;
0771     unsigned VClk, Freq;
0772     unsigned M, N, P;
0773 
0774     DeltaOld = 0xFFFFFFFF;
0775 
0776     VClk = (unsigned)clockIn;
0777 
0778     if (par->CrystalFreqKHz == 13500) {
0779         lowM = 7;
0780         highM = 13;
0781     } else {
0782         lowM = 8;
0783         highM = 14;
0784     }
0785 
0786     for (P = 0; P <= 4; P++) {
0787         Freq = VClk << P;
0788         if ((Freq >= 128000) && (Freq <= 350000)) {
0789             for (M = lowM; M <= highM; M++) {
0790                 N = ((VClk << P) * M) / par->CrystalFreqKHz;
0791                 if (N <= 255) {
0792                     Freq =
0793                         ((par->CrystalFreqKHz * N) /
0794                          M) >> P;
0795                     if (Freq > VClk)
0796                         DeltaNew = Freq - VClk;
0797                     else
0798                         DeltaNew = VClk - Freq;
0799                     if (DeltaNew < DeltaOld) {
0800                         *pllOut =
0801                             (P << 16) | (N << 8) | M;
0802                         *clockOut = Freq;
0803                         DeltaOld = DeltaNew;
0804                     }
0805                 }
0806             }
0807         }
0808     }
0809 }
0810 
0811 static void CalcVClock2Stage(int clockIn,
0812                  int *clockOut,
0813                  u32 * pllOut,
0814                  u32 * pllBOut, struct nvidia_par *par)
0815 {
0816     unsigned DeltaNew, DeltaOld;
0817     unsigned VClk, Freq;
0818     unsigned M, N, P;
0819 
0820     DeltaOld = 0xFFFFFFFF;
0821 
0822     *pllBOut = 0x80000401;  /* fixed at x4 for now */
0823 
0824     VClk = (unsigned)clockIn;
0825 
0826     for (P = 0; P <= 6; P++) {
0827         Freq = VClk << P;
0828         if ((Freq >= 400000) && (Freq <= 1000000)) {
0829             for (M = 1; M <= 13; M++) {
0830                 N = ((VClk << P) * M) /
0831                     (par->CrystalFreqKHz << 2);
0832                 if ((N >= 5) && (N <= 255)) {
0833                     Freq =
0834                         (((par->CrystalFreqKHz << 2) * N) /
0835                          M) >> P;
0836                     if (Freq > VClk)
0837                         DeltaNew = Freq - VClk;
0838                     else
0839                         DeltaNew = VClk - Freq;
0840                     if (DeltaNew < DeltaOld) {
0841                         *pllOut =
0842                             (P << 16) | (N << 8) | M;
0843                         *clockOut = Freq;
0844                         DeltaOld = DeltaNew;
0845                     }
0846                 }
0847             }
0848         }
0849     }
0850 }
0851 
0852 /*
0853  * Calculate extended mode parameters (SVGA) and save in a
0854  * mode state structure.
0855  */
0856 void NVCalcStateExt(struct nvidia_par *par,
0857             RIVA_HW_STATE * state,
0858             int bpp,
0859             int width,
0860             int hDisplaySize, int height, int dotClock, int flags)
0861 {
0862     int pixelDepth, VClk = 0;
0863     /*
0864      * Save mode parameters.
0865      */
0866     state->bpp = bpp;   /* this is not bitsPerPixel, it's 8,15,16,32 */
0867     state->width = width;
0868     state->height = height;
0869     /*
0870      * Extended RIVA registers.
0871      */
0872     pixelDepth = (bpp + 1) / 8;
0873     if (par->twoStagePLL)
0874         CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
0875                  par);
0876     else
0877         CalcVClock(dotClock, &VClk, &state->pll, par);
0878 
0879     switch (par->Architecture) {
0880     case NV_ARCH_04:
0881         nv4UpdateArbitrationSettings(VClk,
0882                          pixelDepth * 8,
0883                          &(state->arbitration0),
0884                          &(state->arbitration1), par);
0885         state->cursor0 = 0x00;
0886         state->cursor1 = 0xbC;
0887         if (flags & FB_VMODE_DOUBLE)
0888             state->cursor1 |= 2;
0889         state->cursor2 = 0x00000000;
0890         state->pllsel = 0x10000700;
0891         state->config = 0x00001114;
0892         state->general = bpp == 16 ? 0x00101100 : 0x00100100;
0893         state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
0894         break;
0895     case NV_ARCH_40:
0896         if (!par->FlatPanel)
0897             state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
0898                 0xeffffeff;
0899         fallthrough;
0900     case NV_ARCH_10:
0901     case NV_ARCH_20:
0902     case NV_ARCH_30:
0903     default:
0904         if ((par->Chipset & 0xfff0) == 0x0240 ||
0905             (par->Chipset & 0xfff0) == 0x03d0) {
0906             state->arbitration0 = 256;
0907             state->arbitration1 = 0x0480;
0908         } else if (((par->Chipset & 0xffff) == 0x01A0) ||
0909             ((par->Chipset & 0xffff) == 0x01f0)) {
0910             nForceUpdateArbitrationSettings(VClk,
0911                             pixelDepth * 8,
0912                             &(state->arbitration0),
0913                             &(state->arbitration1),
0914                             par);
0915         } else if (par->Architecture < NV_ARCH_30) {
0916             nv10UpdateArbitrationSettings(VClk,
0917                               pixelDepth * 8,
0918                               &(state->arbitration0),
0919                               &(state->arbitration1),
0920                               par);
0921         } else {
0922             nv30UpdateArbitrationSettings(par,
0923                               &(state->arbitration0),
0924                               &(state->arbitration1));
0925         }
0926 
0927         state->cursor0 = 0x80 | (par->CursorStart >> 17);
0928         state->cursor1 = (par->CursorStart >> 11) << 2;
0929         state->cursor2 = par->CursorStart >> 24;
0930         if (flags & FB_VMODE_DOUBLE)
0931             state->cursor1 |= 2;
0932         state->pllsel = 0x10000700;
0933         state->config = NV_RD32(par->PFB, 0x00000200);
0934         state->general = bpp == 16 ? 0x00101100 : 0x00100100;
0935         state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
0936         break;
0937     }
0938 
0939     if (bpp != 8)       /* DirectColor */
0940         state->general |= 0x00000030;
0941 
0942     state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
0943     state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
0944 }
0945 
0946 void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
0947 {
0948     int i, j;
0949 
0950     NV_WR32(par->PMC, 0x0140, 0x00000000);
0951     NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
0952     NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
0953 
0954     NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
0955     NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
0956     NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
0957     NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
0958 
0959     if (par->Architecture == NV_ARCH_04) {
0960         if (state)
0961             NV_WR32(par->PFB, 0x0200, state->config);
0962     } else if ((par->Architecture < NV_ARCH_40) ||
0963            (par->Chipset & 0xfff0) == 0x0040) {
0964         for (i = 0; i < 8; i++) {
0965             NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
0966             NV_WR32(par->PFB, 0x0244 + (i * 0x10),
0967                 par->FbMapSize - 1);
0968         }
0969     } else {
0970         int regions = 12;
0971 
0972         if (((par->Chipset & 0xfff0) == 0x0090) ||
0973             ((par->Chipset & 0xfff0) == 0x01D0) ||
0974             ((par->Chipset & 0xfff0) == 0x0290) ||
0975             ((par->Chipset & 0xfff0) == 0x0390) ||
0976             ((par->Chipset & 0xfff0) == 0x03D0))
0977             regions = 15;
0978         for(i = 0; i < regions; i++) {
0979             NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
0980             NV_WR32(par->PFB, 0x0604 + (i * 0x10),
0981                 par->FbMapSize - 1);
0982         }
0983     }
0984 
0985     if (par->Architecture >= NV_ARCH_40) {
0986         NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
0987         NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
0988         NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
0989         NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
0990         NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
0991         NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
0992         NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
0993         NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
0994         NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
0995         NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
0996         NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
0997         NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
0998         NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
0999         NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
1000         NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1001         NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
1002         NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1003         NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1004         NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1005         NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
1006         NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1007         NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
1008         NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
1009         NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
1010         NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
1011         NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
1012         NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1013         NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1014         NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1015         NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
1016         NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1017         NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
1018         NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
1019         NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
1020         NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1021         NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
1022         NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
1023         NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
1024         NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1025         NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
1026         NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1027         NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
1028         NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
1029         NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
1030         NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
1031         NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
1032         NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
1033         NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
1034         NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
1035         NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
1036         NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
1037         NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
1038         NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
1039         NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
1040         NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
1041         NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
1042         NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
1043         NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
1044         NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
1045         NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
1046         NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
1047         NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
1048         NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
1049         NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
1050         NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
1051         NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
1052         NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
1053         NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
1054         NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
1055         NV_WR32(par->PRAMIN, 0x084E * 4,
1056             par->FbUsableSize | 0x00000002);
1057 
1058 #ifdef __BIG_ENDIAN
1059         NV_WR32(par->PRAMIN, 0x080A * 4,
1060             NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
1061         NV_WR32(par->PRAMIN, 0x0812 * 4,
1062             NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
1063         NV_WR32(par->PRAMIN, 0x081A * 4,
1064             NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
1065         NV_WR32(par->PRAMIN, 0x0822 * 4,
1066             NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
1067         NV_WR32(par->PRAMIN, 0x082A * 4,
1068             NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
1069         NV_WR32(par->PRAMIN, 0x0832 * 4,
1070             NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
1071         NV_WR32(par->PRAMIN, 0x083A * 4,
1072             NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
1073         NV_WR32(par->PRAMIN, 0x0842 * 4,
1074             NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
1075         NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
1076         NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
1077 #endif
1078     } else {
1079         NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
1080         NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
1081         NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
1082         NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
1083         NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
1084         NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
1085         NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
1086         NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
1087         NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
1088         NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
1089         NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
1090         NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
1091         NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
1092         NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
1093         NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
1094         NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
1095         NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
1096         NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
1097         NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
1098         NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
1099         if (par->Architecture >= NV_ARCH_10)
1100             NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
1101         else
1102             NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
1103         NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
1104         NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
1105         NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
1106         NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
1107         NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
1108         NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
1109         NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
1110         NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
1111         NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
1112         NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
1113         NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
1114         NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
1115         NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
1116         NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
1117         NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
1118         NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
1119         NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
1120         NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
1121         NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
1122         if (par->WaitVSyncPossible)
1123             NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
1124         else
1125             NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
1126         NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
1127         NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
1128         NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
1129         NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
1130         NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
1131         NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
1132         NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
1133         NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
1134         NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
1135         NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
1136         NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
1137         NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
1138         NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
1139         NV_WR32(par->PRAMIN, 0x0826 * 4,
1140             par->FbUsableSize | 0x00000002);
1141         NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
1142 #ifdef __BIG_ENDIAN
1143         NV_WR32(par->PRAMIN, 0x0804 * 4,
1144             NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
1145         NV_WR32(par->PRAMIN, 0x0808 * 4,
1146             NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
1147         NV_WR32(par->PRAMIN, 0x080C * 4,
1148             NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
1149         NV_WR32(par->PRAMIN, 0x0810 * 4,
1150             NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
1151         NV_WR32(par->PRAMIN, 0x0814 * 4,
1152             NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
1153         NV_WR32(par->PRAMIN, 0x0818 * 4,
1154             NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
1155         NV_WR32(par->PRAMIN, 0x081C * 4,
1156             NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
1157         NV_WR32(par->PRAMIN, 0x0820 * 4,
1158             NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
1159         NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
1160         NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
1161 #endif
1162     }
1163     if (par->Architecture < NV_ARCH_10) {
1164         if ((par->Chipset & 0x0fff) == 0x0020) {
1165             NV_WR32(par->PRAMIN, 0x0824 * 4,
1166                 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
1167             NV_WR32(par->PRAMIN, 0x0826 * 4,
1168                 NV_RD32(par->PRAMIN,
1169                     0x0826 * 4) + par->FbAddress);
1170         }
1171         NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
1172         NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
1173         NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
1174         NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
1175         NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
1176         NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
1177         NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1178         NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1179         NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
1180         NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
1181         NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1182         NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1183         NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1184     } else {
1185         NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
1186         NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
1187 
1188         NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
1189         NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
1190         NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
1191         NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
1192         NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
1193         NV_WR32(par->PGRAPH, 0x0710,
1194             NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
1195         NV_WR32(par->PGRAPH, 0x0710,
1196             NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
1197 
1198         if (par->Architecture == NV_ARCH_10) {
1199             NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1200             NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
1201             NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
1202 
1203             for (i = 0; i < 32; i++)
1204                 NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
1205                     NV_RD32(&par->PFB[(0x0240 / 4) + i],
1206                         0));
1207 
1208             NV_WR32(par->PGRAPH, 0x640, 0);
1209             NV_WR32(par->PGRAPH, 0x644, 0);
1210             NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
1211             NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
1212 
1213             NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
1214             NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
1215         } else {
1216             if (par->Architecture >= NV_ARCH_40) {
1217                 NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
1218                 NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
1219                 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1220                 NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
1221                 NV_WR32(par->PGRAPH, 0x0bc4,
1222                     NV_RD32(par->PGRAPH, 0x0bc4) |
1223                     0x00008000);
1224 
1225                 j = NV_RD32(par->REGS, 0x1540) & 0xff;
1226 
1227                 if (j) {
1228                     for (i = 0; !(j & 1); j >>= 1, i++);
1229                     NV_WR32(par->PGRAPH, 0x5000, i);
1230                 }
1231 
1232                 if ((par->Chipset & 0xfff0) == 0x0040) {
1233                     NV_WR32(par->PGRAPH, 0x09b0,
1234                         0x83280fff);
1235                     NV_WR32(par->PGRAPH, 0x09b4,
1236                         0x000000a0);
1237                 } else {
1238                     NV_WR32(par->PGRAPH, 0x0820,
1239                         0x83280eff);
1240                     NV_WR32(par->PGRAPH, 0x0824,
1241                         0x000000a0);
1242                 }
1243 
1244                 switch (par->Chipset & 0xfff0) {
1245                 case 0x0040:
1246                 case 0x0210:
1247                     NV_WR32(par->PGRAPH, 0x09b8,
1248                         0x0078e366);
1249                     NV_WR32(par->PGRAPH, 0x09bc,
1250                         0x0000014c);
1251                     NV_WR32(par->PFB, 0x033C,
1252                         NV_RD32(par->PFB, 0x33C) &
1253                         0xffff7fff);
1254                     break;
1255                 case 0x00C0:
1256                 case 0x0120:
1257                     NV_WR32(par->PGRAPH, 0x0828,
1258                         0x007596ff);
1259                     NV_WR32(par->PGRAPH, 0x082C,
1260                         0x00000108);
1261                     break;
1262                 case 0x0160:
1263                 case 0x01D0:
1264                 case 0x0240:
1265                 case 0x03D0:
1266                     NV_WR32(par->PMC, 0x1700,
1267                         NV_RD32(par->PFB, 0x020C));
1268                     NV_WR32(par->PMC, 0x1704, 0);
1269                     NV_WR32(par->PMC, 0x1708, 0);
1270                     NV_WR32(par->PMC, 0x170C,
1271                         NV_RD32(par->PFB, 0x020C));
1272                     NV_WR32(par->PGRAPH, 0x0860, 0);
1273                     NV_WR32(par->PGRAPH, 0x0864, 0);
1274                     NV_WR32(par->PRAMDAC, 0x0608,
1275                         NV_RD32(par->PRAMDAC,
1276                             0x0608) | 0x00100000);
1277                     break;
1278                 case 0x0140:
1279                     NV_WR32(par->PGRAPH, 0x0828,
1280                         0x0072cb77);
1281                     NV_WR32(par->PGRAPH, 0x082C,
1282                         0x00000108);
1283                     break;
1284                 case 0x0220:
1285                     NV_WR32(par->PGRAPH, 0x0860, 0);
1286                     NV_WR32(par->PGRAPH, 0x0864, 0);
1287                     NV_WR32(par->PRAMDAC, 0x0608,
1288                         NV_RD32(par->PRAMDAC, 0x0608) |
1289                         0x00100000);
1290                     break;
1291                 case 0x0090:
1292                 case 0x0290:
1293                 case 0x0390:
1294                     NV_WR32(par->PRAMDAC, 0x0608,
1295                         NV_RD32(par->PRAMDAC, 0x0608) |
1296                         0x00100000);
1297                     NV_WR32(par->PGRAPH, 0x0828,
1298                         0x07830610);
1299                     NV_WR32(par->PGRAPH, 0x082C,
1300                         0x0000016A);
1301                     break;
1302                 default:
1303                     break;
1304                 }
1305 
1306                 NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
1307                 NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
1308                 NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
1309                 NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
1310             } else if (par->Architecture == NV_ARCH_30) {
1311                 NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
1312                 NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
1313                 NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
1314                 NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
1315                 NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
1316                 NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
1317                 NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
1318             } else {
1319                 NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
1320                 NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
1321                 NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
1322                 NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
1323 
1324                 if ((par->Chipset & 0x0ff0) >= 0x0250) {
1325                     NV_WR32(par->PGRAPH, 0x0890,
1326                         0x00080000);
1327                     NV_WR32(par->PGRAPH, 0x0610,
1328                         0x304B1FB6);
1329                     NV_WR32(par->PGRAPH, 0x0B80,
1330                         0x18B82880);
1331                     NV_WR32(par->PGRAPH, 0x0B84,
1332                         0x44000000);
1333                     NV_WR32(par->PGRAPH, 0x0098,
1334                         0x40000080);
1335                     NV_WR32(par->PGRAPH, 0x0B88,
1336                         0x000000ff);
1337                 } else {
1338                     NV_WR32(par->PGRAPH, 0x0880,
1339                         0x00080000);
1340                     NV_WR32(par->PGRAPH, 0x0094,
1341                         0x00000005);
1342                     NV_WR32(par->PGRAPH, 0x0B80,
1343                         0x45CAA208);
1344                     NV_WR32(par->PGRAPH, 0x0B84,
1345                         0x24000000);
1346                     NV_WR32(par->PGRAPH, 0x0098,
1347                         0x00000040);
1348                     NV_WR32(par->PGRAPH, 0x0750,
1349                         0x00E00038);
1350                     NV_WR32(par->PGRAPH, 0x0754,
1351                         0x00000030);
1352                     NV_WR32(par->PGRAPH, 0x0750,
1353                         0x00E10038);
1354                     NV_WR32(par->PGRAPH, 0x0754,
1355                         0x00000030);
1356                 }
1357             }
1358 
1359             if ((par->Architecture < NV_ARCH_40) ||
1360                 ((par->Chipset & 0xfff0) == 0x0040)) {
1361                 for (i = 0; i < 32; i++) {
1362                     NV_WR32(par->PGRAPH, 0x0900 + i*4,
1363                         NV_RD32(par->PFB, 0x0240 +i*4));
1364                     NV_WR32(par->PGRAPH, 0x6900 + i*4,
1365                         NV_RD32(par->PFB, 0x0240 +i*4));
1366                 }
1367             } else {
1368                 if (((par->Chipset & 0xfff0) == 0x0090) ||
1369                     ((par->Chipset & 0xfff0) == 0x01D0) ||
1370                     ((par->Chipset & 0xfff0) == 0x0290) ||
1371                     ((par->Chipset & 0xfff0) == 0x0390) ||
1372                     ((par->Chipset & 0xfff0) == 0x03D0)) {
1373                     for (i = 0; i < 60; i++) {
1374                         NV_WR32(par->PGRAPH,
1375                             0x0D00 + i*4,
1376                             NV_RD32(par->PFB,
1377                                 0x0600 + i*4));
1378                         NV_WR32(par->PGRAPH,
1379                             0x6900 + i*4,
1380                             NV_RD32(par->PFB,
1381                                 0x0600 + i*4));
1382                     }
1383                 } else {
1384                     for (i = 0; i < 48; i++) {
1385                         NV_WR32(par->PGRAPH,
1386                             0x0900 + i*4,
1387                             NV_RD32(par->PFB,
1388                                 0x0600 + i*4));
1389                         if(((par->Chipset & 0xfff0)
1390                             != 0x0160) &&
1391                            ((par->Chipset & 0xfff0)
1392                             != 0x0220) &&
1393                            ((par->Chipset & 0xfff0)
1394                             != 0x240))
1395                             NV_WR32(par->PGRAPH,
1396                                 0x6900 + i*4,
1397                                 NV_RD32(par->PFB,
1398                                     0x0600 + i*4));
1399                     }
1400                 }
1401             }
1402 
1403             if (par->Architecture >= NV_ARCH_40) {
1404                 if ((par->Chipset & 0xfff0) == 0x0040) {
1405                     NV_WR32(par->PGRAPH, 0x09A4,
1406                         NV_RD32(par->PFB, 0x0200));
1407                     NV_WR32(par->PGRAPH, 0x09A8,
1408                         NV_RD32(par->PFB, 0x0204));
1409                     NV_WR32(par->PGRAPH, 0x69A4,
1410                         NV_RD32(par->PFB, 0x0200));
1411                     NV_WR32(par->PGRAPH, 0x69A8,
1412                         NV_RD32(par->PFB, 0x0204));
1413 
1414                     NV_WR32(par->PGRAPH, 0x0820, 0);
1415                     NV_WR32(par->PGRAPH, 0x0824, 0);
1416                     NV_WR32(par->PGRAPH, 0x0864,
1417                         par->FbMapSize - 1);
1418                     NV_WR32(par->PGRAPH, 0x0868,
1419                         par->FbMapSize - 1);
1420                 } else {
1421                     if ((par->Chipset & 0xfff0) == 0x0090 ||
1422                         (par->Chipset & 0xfff0) == 0x01D0 ||
1423                         (par->Chipset & 0xfff0) == 0x0290 ||
1424                         (par->Chipset & 0xfff0) == 0x0390) {
1425                         NV_WR32(par->PGRAPH, 0x0DF0,
1426                             NV_RD32(par->PFB, 0x0200));
1427                         NV_WR32(par->PGRAPH, 0x0DF4,
1428                             NV_RD32(par->PFB, 0x0204));
1429                     } else {
1430                         NV_WR32(par->PGRAPH, 0x09F0,
1431                             NV_RD32(par->PFB, 0x0200));
1432                         NV_WR32(par->PGRAPH, 0x09F4,
1433                             NV_RD32(par->PFB, 0x0204));
1434                     }
1435                     NV_WR32(par->PGRAPH, 0x69F0,
1436                         NV_RD32(par->PFB, 0x0200));
1437                     NV_WR32(par->PGRAPH, 0x69F4,
1438                         NV_RD32(par->PFB, 0x0204));
1439 
1440                     NV_WR32(par->PGRAPH, 0x0840, 0);
1441                     NV_WR32(par->PGRAPH, 0x0844, 0);
1442                     NV_WR32(par->PGRAPH, 0x08a0,
1443                         par->FbMapSize - 1);
1444                     NV_WR32(par->PGRAPH, 0x08a4,
1445                         par->FbMapSize - 1);
1446                 }
1447             } else {
1448                 NV_WR32(par->PGRAPH, 0x09A4,
1449                     NV_RD32(par->PFB, 0x0200));
1450                 NV_WR32(par->PGRAPH, 0x09A8,
1451                     NV_RD32(par->PFB, 0x0204));
1452                 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
1453                 NV_WR32(par->PGRAPH, 0x0754,
1454                     NV_RD32(par->PFB, 0x0200));
1455                 NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
1456                 NV_WR32(par->PGRAPH, 0x0754,
1457                     NV_RD32(par->PFB, 0x0204));
1458 
1459                 NV_WR32(par->PGRAPH, 0x0820, 0);
1460                 NV_WR32(par->PGRAPH, 0x0824, 0);
1461                 NV_WR32(par->PGRAPH, 0x0864,
1462                     par->FbMapSize - 1);
1463                 NV_WR32(par->PGRAPH, 0x0868,
1464                     par->FbMapSize - 1);
1465             }
1466             NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
1467             NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
1468         }
1469     }
1470     NV_WR32(par->PGRAPH, 0x053C, 0);
1471     NV_WR32(par->PGRAPH, 0x0540, 0);
1472     NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
1473     NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
1474 
1475     NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
1476     NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
1477     NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
1478     NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
1479     if (par->Architecture >= NV_ARCH_40)
1480         NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
1481     else
1482         NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
1483     NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
1484     NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
1485     if (par->Architecture >= NV_ARCH_40)
1486         NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
1487     else
1488         NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
1489     NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
1490     NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
1491     NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
1492     NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
1493     NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
1494     NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
1495     NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
1496     NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
1497     NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
1498     NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
1499     NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
1500     NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
1501 #ifdef __BIG_ENDIAN
1502     NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
1503 #else
1504     NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
1505 #endif
1506     NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
1507     NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
1508     NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
1509     NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
1510     NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
1511 
1512     if (!state) {
1513         par->CurrentState = NULL;
1514         return;
1515     }
1516 
1517     if (par->Architecture >= NV_ARCH_10) {
1518         if (par->twoHeads) {
1519             NV_WR32(par->PCRTC0, 0x0860, state->head);
1520             NV_WR32(par->PCRTC0, 0x2860, state->head2);
1521         }
1522         NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
1523             (1 << 25));
1524 
1525         NV_WR32(par->PMC, 0x8704, 1);
1526         NV_WR32(par->PMC, 0x8140, 0);
1527         NV_WR32(par->PMC, 0x8920, 0);
1528         NV_WR32(par->PMC, 0x8924, 0);
1529         NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
1530         NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
1531         NV_WR32(par->PMC, 0x1588, 0);
1532 
1533         NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
1534         NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
1535         NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
1536 
1537         if (par->FlatPanel) {
1538             if ((par->Chipset & 0x0ff0) == 0x0110) {
1539                 NV_WR32(par->PRAMDAC, 0x0528, state->dither);
1540             } else if (par->twoHeads) {
1541                 NV_WR32(par->PRAMDAC, 0x083C, state->dither);
1542             }
1543 
1544             VGA_WR08(par->PCIO, 0x03D4, 0x53);
1545             VGA_WR08(par->PCIO, 0x03D5, state->timingH);
1546             VGA_WR08(par->PCIO, 0x03D4, 0x54);
1547             VGA_WR08(par->PCIO, 0x03D5, state->timingV);
1548             VGA_WR08(par->PCIO, 0x03D4, 0x21);
1549             VGA_WR08(par->PCIO, 0x03D5, 0xfa);
1550         }
1551 
1552         VGA_WR08(par->PCIO, 0x03D4, 0x41);
1553         VGA_WR08(par->PCIO, 0x03D5, state->extra);
1554     }
1555 
1556     VGA_WR08(par->PCIO, 0x03D4, 0x19);
1557     VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
1558     VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1559     VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
1560     VGA_WR08(par->PCIO, 0x03D4, 0x25);
1561     VGA_WR08(par->PCIO, 0x03D5, state->screen);
1562     VGA_WR08(par->PCIO, 0x03D4, 0x28);
1563     VGA_WR08(par->PCIO, 0x03D5, state->pixel);
1564     VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1565     VGA_WR08(par->PCIO, 0x03D5, state->horiz);
1566     VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1567     VGA_WR08(par->PCIO, 0x03D5, state->fifo);
1568     VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1569     VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
1570     VGA_WR08(par->PCIO, 0x03D4, 0x20);
1571     VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
1572 
1573     if(par->Architecture >= NV_ARCH_30) {
1574         VGA_WR08(par->PCIO, 0x03D4, 0x47);
1575         VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
1576     }
1577 
1578     VGA_WR08(par->PCIO, 0x03D4, 0x30);
1579     VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
1580     VGA_WR08(par->PCIO, 0x03D4, 0x31);
1581     VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
1582     VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1583     VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
1584     VGA_WR08(par->PCIO, 0x03D4, 0x39);
1585     VGA_WR08(par->PCIO, 0x03D5, state->interlace);
1586 
1587     if (!par->FlatPanel) {
1588         if (par->Architecture >= NV_ARCH_40)
1589             NV_WR32(par->PRAMDAC0, 0x0580, state->control);
1590 
1591         NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
1592         NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
1593         if (par->twoHeads)
1594             NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
1595         if (par->twoStagePLL) {
1596             NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
1597             NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
1598         }
1599     } else {
1600         NV_WR32(par->PRAMDAC, 0x0848, state->scale);
1601         NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
1602             par->PanelTweak);
1603     }
1604 
1605     NV_WR32(par->PRAMDAC, 0x0600, state->general);
1606 
1607     NV_WR32(par->PCRTC, 0x0140, 0);
1608     NV_WR32(par->PCRTC, 0x0100, 1);
1609 
1610     par->CurrentState = state;
1611 }
1612 
1613 void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
1614     VGA_WR08(par->PCIO, 0x03D4, 0x19);
1615     state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
1616     VGA_WR08(par->PCIO, 0x03D4, 0x1A);
1617     state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
1618     VGA_WR08(par->PCIO, 0x03D4, 0x25);
1619     state->screen = VGA_RD08(par->PCIO, 0x03D5);
1620     VGA_WR08(par->PCIO, 0x03D4, 0x28);
1621     state->pixel = VGA_RD08(par->PCIO, 0x03D5);
1622     VGA_WR08(par->PCIO, 0x03D4, 0x2D);
1623     state->horiz = VGA_RD08(par->PCIO, 0x03D5);
1624     VGA_WR08(par->PCIO, 0x03D4, 0x1C);
1625     state->fifo         = VGA_RD08(par->PCIO, 0x03D5);
1626     VGA_WR08(par->PCIO, 0x03D4, 0x1B);
1627     state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
1628     VGA_WR08(par->PCIO, 0x03D4, 0x20);
1629     state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
1630 
1631     if(par->Architecture >= NV_ARCH_30) {
1632         VGA_WR08(par->PCIO, 0x03D4, 0x47);
1633         state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
1634     }
1635 
1636     VGA_WR08(par->PCIO, 0x03D4, 0x30);
1637     state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
1638     VGA_WR08(par->PCIO, 0x03D4, 0x31);
1639     state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
1640     VGA_WR08(par->PCIO, 0x03D4, 0x2F);
1641     state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
1642     VGA_WR08(par->PCIO, 0x03D4, 0x39);
1643     state->interlace = VGA_RD08(par->PCIO, 0x03D5);
1644     state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
1645     if (par->twoHeads)
1646         state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
1647     if (par->twoStagePLL) {
1648         state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
1649         state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
1650     }
1651     state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
1652     state->general = NV_RD32(par->PRAMDAC, 0x0600);
1653     state->scale = NV_RD32(par->PRAMDAC, 0x0848);
1654     state->config = NV_RD32(par->PFB, 0x0200);
1655 
1656     if (par->Architecture >= NV_ARCH_40 && !par->FlatPanel)
1657         state->control  = NV_RD32(par->PRAMDAC0, 0x0580);
1658 
1659     if (par->Architecture >= NV_ARCH_10) {
1660         if (par->twoHeads) {
1661             state->head = NV_RD32(par->PCRTC0, 0x0860);
1662             state->head2 = NV_RD32(par->PCRTC0, 0x2860);
1663             VGA_WR08(par->PCIO, 0x03D4, 0x44);
1664             state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
1665         }
1666         VGA_WR08(par->PCIO, 0x03D4, 0x41);
1667         state->extra = VGA_RD08(par->PCIO, 0x03D5);
1668         state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
1669 
1670         if ((par->Chipset & 0x0ff0) == 0x0110) {
1671             state->dither = NV_RD32(par->PRAMDAC, 0x0528);
1672         } else if (par->twoHeads) {
1673             state->dither = NV_RD32(par->PRAMDAC, 0x083C);
1674         }
1675 
1676         if (par->FlatPanel) {
1677             VGA_WR08(par->PCIO, 0x03D4, 0x53);
1678             state->timingH = VGA_RD08(par->PCIO, 0x03D5);
1679             VGA_WR08(par->PCIO, 0x03D4, 0x54);
1680             state->timingV = VGA_RD08(par->PCIO, 0x03D5);
1681         }
1682     }
1683 }
1684 
1685 void NVSetStartAddress(struct nvidia_par *par, u32 start)
1686 {
1687     NV_WR32(par->PCRTC, 0x800, start);
1688 }
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