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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * drivers/mb862xx/mb862xxfb.c
0004  *
0005  * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
0006  *
0007  * (C) 2008 Anatolij Gustschin <agust@denx.de>
0008  * DENX Software Engineering
0009  */
0010 
0011 #undef DEBUG
0012 
0013 #include <linux/fb.h>
0014 #include <linux/delay.h>
0015 #include <linux/uaccess.h>
0016 #include <linux/module.h>
0017 #include <linux/init.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/pci.h>
0020 #if defined(CONFIG_OF)
0021 #include <linux/of_address.h>
0022 #include <linux/of_irq.h>
0023 #include <linux/of_platform.h>
0024 #endif
0025 #include "mb862xxfb.h"
0026 #include "mb862xx_reg.h"
0027 
0028 #define NR_PALETTE      256
0029 #define MB862XX_MEM_SIZE    0x1000000
0030 #define CORALP_MEM_SIZE     0x2000000
0031 #define CARMINE_MEM_SIZE    0x8000000
0032 #define DRV_NAME        "mb862xxfb"
0033 
0034 #if defined(CONFIG_SOCRATES)
0035 static struct mb862xx_gc_mode socrates_gc_mode = {
0036     /* Mode for Prime View PM070WL4 TFT LCD Panel */
0037     { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
0038     /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
0039     16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
0040 };
0041 #endif
0042 
0043 /* Helpers */
0044 static inline int h_total(struct fb_var_screeninfo *var)
0045 {
0046     return var->xres + var->left_margin +
0047         var->right_margin + var->hsync_len;
0048 }
0049 
0050 static inline int v_total(struct fb_var_screeninfo *var)
0051 {
0052     return var->yres + var->upper_margin +
0053         var->lower_margin + var->vsync_len;
0054 }
0055 
0056 static inline int hsp(struct fb_var_screeninfo *var)
0057 {
0058     return var->xres + var->right_margin - 1;
0059 }
0060 
0061 static inline int vsp(struct fb_var_screeninfo *var)
0062 {
0063     return var->yres + var->lower_margin - 1;
0064 }
0065 
0066 static inline int d_pitch(struct fb_var_screeninfo *var)
0067 {
0068     return var->xres * var->bits_per_pixel / 8;
0069 }
0070 
0071 static inline unsigned int chan_to_field(unsigned int chan,
0072                      struct fb_bitfield *bf)
0073 {
0074     chan &= 0xffff;
0075     chan >>= 16 - bf->length;
0076     return chan << bf->offset;
0077 }
0078 
0079 static int mb862xxfb_setcolreg(unsigned regno,
0080                    unsigned red, unsigned green, unsigned blue,
0081                    unsigned transp, struct fb_info *info)
0082 {
0083     struct mb862xxfb_par *par = info->par;
0084     unsigned int val;
0085 
0086     switch (info->fix.visual) {
0087     case FB_VISUAL_TRUECOLOR:
0088         if (regno < 16) {
0089             val  = chan_to_field(red,   &info->var.red);
0090             val |= chan_to_field(green, &info->var.green);
0091             val |= chan_to_field(blue,  &info->var.blue);
0092             par->pseudo_palette[regno] = val;
0093         }
0094         break;
0095     case FB_VISUAL_PSEUDOCOLOR:
0096         if (regno < 256) {
0097             val = (red >> 8) << 16;
0098             val |= (green >> 8) << 8;
0099             val |= blue >> 8;
0100             outreg(disp, GC_L0PAL0 + (regno * 4), val);
0101         }
0102         break;
0103     default:
0104         return 1;   /* unsupported type */
0105     }
0106     return 0;
0107 }
0108 
0109 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
0110                    struct fb_info *fbi)
0111 {
0112     unsigned long tmp;
0113 
0114     if (fbi->dev)
0115         dev_dbg(fbi->dev, "%s\n", __func__);
0116 
0117     /* check if these values fit into the registers */
0118     if (var->hsync_len > 255 || var->vsync_len > 255)
0119         return -EINVAL;
0120 
0121     if ((var->xres + var->right_margin) >= 4096)
0122         return -EINVAL;
0123 
0124     if ((var->yres + var->lower_margin) > 4096)
0125         return -EINVAL;
0126 
0127     if (h_total(var) > 4096 || v_total(var) > 4096)
0128         return -EINVAL;
0129 
0130     if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
0131         return -EINVAL;
0132 
0133     if (var->bits_per_pixel <= 8)
0134         var->bits_per_pixel = 8;
0135     else if (var->bits_per_pixel <= 16)
0136         var->bits_per_pixel = 16;
0137     else if (var->bits_per_pixel <= 32)
0138         var->bits_per_pixel = 32;
0139 
0140     /*
0141      * can cope with 8,16 or 24/32bpp if resulting
0142      * pitch is divisible by 64 without remainder
0143      */
0144     if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
0145         int r;
0146 
0147         var->bits_per_pixel = 0;
0148         do {
0149             var->bits_per_pixel += 8;
0150             r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
0151         } while (r && var->bits_per_pixel <= 32);
0152 
0153         if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
0154             return -EINVAL;
0155     }
0156 
0157     /* line length is going to be 128 bit aligned */
0158     tmp = (var->xres * var->bits_per_pixel) / 8;
0159     if ((tmp & 15) != 0)
0160         return -EINVAL;
0161 
0162     /* set r/g/b positions and validate bpp */
0163     switch (var->bits_per_pixel) {
0164     case 8:
0165         var->red.length     = var->bits_per_pixel;
0166         var->green.length   = var->bits_per_pixel;
0167         var->blue.length    = var->bits_per_pixel;
0168         var->red.offset     = 0;
0169         var->green.offset   = 0;
0170         var->blue.offset    = 0;
0171         var->transp.length  = 0;
0172         break;
0173     case 16:
0174         var->red.length     = 5;
0175         var->green.length   = 5;
0176         var->blue.length    = 5;
0177         var->red.offset     = 10;
0178         var->green.offset   = 5;
0179         var->blue.offset    = 0;
0180         var->transp.length  = 0;
0181         break;
0182     case 24:
0183     case 32:
0184         var->transp.length  = 8;
0185         var->red.length     = 8;
0186         var->green.length   = 8;
0187         var->blue.length    = 8;
0188         var->transp.offset  = 24;
0189         var->red.offset     = 16;
0190         var->green.offset   = 8;
0191         var->blue.offset    = 0;
0192         break;
0193     default:
0194         return -EINVAL;
0195     }
0196     return 0;
0197 }
0198 
0199 static struct fb_ops mb862xxfb_ops;
0200 
0201 /*
0202  * set display parameters
0203  */
0204 static int mb862xxfb_set_par(struct fb_info *fbi)
0205 {
0206     struct mb862xxfb_par *par = fbi->par;
0207     unsigned long reg, sc;
0208 
0209     dev_dbg(par->dev, "%s\n", __func__);
0210     if (par->type == BT_CORALP)
0211         mb862xxfb_init_accel(fbi, &mb862xxfb_ops, fbi->var.xres);
0212 
0213     if (par->pre_init)
0214         return 0;
0215 
0216     /* disp off */
0217     reg = inreg(disp, GC_DCM1);
0218     reg &= ~GC_DCM01_DEN;
0219     outreg(disp, GC_DCM1, reg);
0220 
0221     /* set display reference clock div. */
0222     sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
0223     reg = inreg(disp, GC_DCM1);
0224     reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
0225     reg |= sc << 8;
0226     outreg(disp, GC_DCM1, reg);
0227     dev_dbg(par->dev, "SC 0x%lx\n", sc);
0228 
0229     /* disp dimension, format */
0230     reg =  pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
0231             (fbi->var.yres - 1));
0232     if (fbi->var.bits_per_pixel == 16)
0233         reg |= GC_L0M_L0C_16;
0234     outreg(disp, GC_L0M, reg);
0235 
0236     if (fbi->var.bits_per_pixel == 32) {
0237         reg = inreg(disp, GC_L0EM);
0238         outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
0239     }
0240     outreg(disp, GC_WY_WX, 0);
0241     reg = pack(fbi->var.yres - 1, fbi->var.xres);
0242     outreg(disp, GC_WH_WW, reg);
0243     outreg(disp, GC_L0OA0, 0);
0244     outreg(disp, GC_L0DA0, 0);
0245     outreg(disp, GC_L0DY_L0DX, 0);
0246     outreg(disp, GC_L0WY_L0WX, 0);
0247     outreg(disp, GC_L0WH_L0WW, reg);
0248 
0249     /* both HW-cursors off */
0250     reg = inreg(disp, GC_CPM_CUTC);
0251     reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
0252     outreg(disp, GC_CPM_CUTC, reg);
0253 
0254     /* timings */
0255     reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
0256     outreg(disp, GC_HDB_HDP, reg);
0257     reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
0258     outreg(disp, GC_VDP_VSP, reg);
0259     reg = ((fbi->var.vsync_len - 1) << 24) |
0260           pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
0261     outreg(disp, GC_VSW_HSW_HSP, reg);
0262     outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
0263     outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
0264 
0265     /* display on */
0266     reg = inreg(disp, GC_DCM1);
0267     reg |= GC_DCM01_DEN | GC_DCM01_L0E;
0268     reg &= ~GC_DCM01_ESY;
0269     outreg(disp, GC_DCM1, reg);
0270     return 0;
0271 }
0272 
0273 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
0274              struct fb_info *info)
0275 {
0276     struct mb862xxfb_par *par = info->par;
0277     unsigned long reg;
0278 
0279     reg = pack(var->yoffset, var->xoffset);
0280     outreg(disp, GC_L0WY_L0WX, reg);
0281 
0282     reg = pack(info->var.yres_virtual, info->var.xres_virtual);
0283     outreg(disp, GC_L0WH_L0WW, reg);
0284     return 0;
0285 }
0286 
0287 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
0288 {
0289     struct mb862xxfb_par  *par = fbi->par;
0290     unsigned long reg;
0291 
0292     dev_dbg(fbi->dev, "blank mode=%d\n", mode);
0293 
0294     switch (mode) {
0295     case FB_BLANK_POWERDOWN:
0296         reg = inreg(disp, GC_DCM1);
0297         reg &= ~GC_DCM01_DEN;
0298         outreg(disp, GC_DCM1, reg);
0299         break;
0300     case FB_BLANK_UNBLANK:
0301         reg = inreg(disp, GC_DCM1);
0302         reg |= GC_DCM01_DEN;
0303         outreg(disp, GC_DCM1, reg);
0304         break;
0305     case FB_BLANK_NORMAL:
0306     case FB_BLANK_VSYNC_SUSPEND:
0307     case FB_BLANK_HSYNC_SUSPEND:
0308     default:
0309         return 1;
0310     }
0311     return 0;
0312 }
0313 
0314 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
0315                unsigned long arg)
0316 {
0317     struct mb862xxfb_par *par = fbi->par;
0318     struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
0319     void __user *argp = (void __user *)arg;
0320     int *enable;
0321     u32 l1em = 0;
0322 
0323     switch (cmd) {
0324     case MB862XX_L1_GET_CFG:
0325         if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
0326             return -EFAULT;
0327         break;
0328     case MB862XX_L1_SET_CFG:
0329         if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
0330             return -EFAULT;
0331         if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
0332             return -EINVAL;
0333         if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
0334             /* downscaling */
0335             outreg(cap, GC_CAP_CSC,
0336                 pack((l1_cfg->sh << 11) / l1_cfg->dh,
0337                      (l1_cfg->sw << 11) / l1_cfg->dw));
0338             l1em = inreg(disp, GC_L1EM);
0339             l1em &= ~GC_L1EM_DM;
0340         } else if ((l1_cfg->sw <= l1_cfg->dw) &&
0341                (l1_cfg->sh <= l1_cfg->dh)) {
0342             /* upscaling */
0343             outreg(cap, GC_CAP_CSC,
0344                 pack((l1_cfg->sh << 11) / l1_cfg->dh,
0345                      (l1_cfg->sw << 11) / l1_cfg->dw));
0346             outreg(cap, GC_CAP_CMSS,
0347                 pack(l1_cfg->sw >> 1, l1_cfg->sh));
0348             outreg(cap, GC_CAP_CMDS,
0349                 pack(l1_cfg->dw >> 1, l1_cfg->dh));
0350             l1em = inreg(disp, GC_L1EM);
0351             l1em |= GC_L1EM_DM;
0352         }
0353 
0354         if (l1_cfg->mirror) {
0355             outreg(cap, GC_CAP_CBM,
0356                 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
0357             l1em |= l1_cfg->dw * 2 - 8;
0358         } else {
0359             outreg(cap, GC_CAP_CBM,
0360                 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
0361             l1em &= 0xffff0000;
0362         }
0363         outreg(disp, GC_L1EM, l1em);
0364         break;
0365     case MB862XX_L1_ENABLE:
0366         enable = (int *)arg;
0367         if (*enable) {
0368             outreg(disp, GC_L1DA, par->cap_buf);
0369             outreg(cap, GC_CAP_IMG_START,
0370                 pack(l1_cfg->sy >> 1, l1_cfg->sx));
0371             outreg(cap, GC_CAP_IMG_END,
0372                 pack(l1_cfg->sh, l1_cfg->sw));
0373             outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
0374                          (par->l1_stride << 16));
0375             outreg(disp, GC_L1WY_L1WX,
0376                 pack(l1_cfg->dy, l1_cfg->dx));
0377             outreg(disp, GC_L1WH_L1WW,
0378                 pack(l1_cfg->dh - 1, l1_cfg->dw));
0379             outreg(disp, GC_DLS, 1);
0380             outreg(cap, GC_CAP_VCM,
0381                 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
0382             outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
0383                           GC_DCM1_DEN | GC_DCM1_L1E);
0384         } else {
0385             outreg(cap, GC_CAP_VCM,
0386                 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
0387             outreg(disp, GC_DCM1,
0388                 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
0389         }
0390         break;
0391     case MB862XX_L1_CAP_CTL:
0392         enable = (int *)arg;
0393         if (*enable) {
0394             outreg(cap, GC_CAP_VCM,
0395                 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
0396         } else {
0397             outreg(cap, GC_CAP_VCM,
0398                 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
0399         }
0400         break;
0401     default:
0402         return -EINVAL;
0403     }
0404     return 0;
0405 }
0406 
0407 /* framebuffer ops */
0408 static struct fb_ops mb862xxfb_ops = {
0409     .owner      = THIS_MODULE,
0410     .fb_check_var   = mb862xxfb_check_var,
0411     .fb_set_par = mb862xxfb_set_par,
0412     .fb_setcolreg   = mb862xxfb_setcolreg,
0413     .fb_blank   = mb862xxfb_blank,
0414     .fb_pan_display = mb862xxfb_pan,
0415     .fb_fillrect    = cfb_fillrect,
0416     .fb_copyarea    = cfb_copyarea,
0417     .fb_imageblit   = cfb_imageblit,
0418     .fb_ioctl   = mb862xxfb_ioctl,
0419 };
0420 
0421 /* initialize fb_info data */
0422 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
0423 {
0424     struct mb862xxfb_par *par = fbi->par;
0425     struct mb862xx_gc_mode *mode = par->gc_mode;
0426     unsigned long reg;
0427     int stride;
0428 
0429     fbi->fbops = &mb862xxfb_ops;
0430     fbi->pseudo_palette = par->pseudo_palette;
0431     fbi->screen_base = par->fb_base;
0432     fbi->screen_size = par->mapped_vram;
0433 
0434     strcpy(fbi->fix.id, DRV_NAME);
0435     fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
0436     fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
0437     fbi->fix.mmio_len = par->mmio_len;
0438     fbi->fix.accel = FB_ACCEL_NONE;
0439     fbi->fix.type = FB_TYPE_PACKED_PIXELS;
0440     fbi->fix.type_aux = 0;
0441     fbi->fix.xpanstep = 1;
0442     fbi->fix.ypanstep = 1;
0443     fbi->fix.ywrapstep = 0;
0444 
0445     reg = inreg(disp, GC_DCM1);
0446     if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
0447         /* get the disp mode from active display cfg */
0448         unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
0449         unsigned long hsp, vsp, ht, vt;
0450 
0451         dev_dbg(par->dev, "using bootloader's disp. mode\n");
0452         fbi->var.pixclock = (sc * 1000000) / par->refclk;
0453         fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
0454         reg = inreg(disp, GC_VDP_VSP);
0455         fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
0456         vsp = (reg & 0x0fff) + 1;
0457         fbi->var.xres_virtual = fbi->var.xres;
0458         fbi->var.yres_virtual = fbi->var.yres;
0459         reg = inreg(disp, GC_L0EM);
0460         if (reg & GC_L0EM_L0EC_24) {
0461             fbi->var.bits_per_pixel = 32;
0462         } else {
0463             reg = inreg(disp, GC_L0M);
0464             if (reg & GC_L0M_L0C_16)
0465                 fbi->var.bits_per_pixel = 16;
0466             else
0467                 fbi->var.bits_per_pixel = 8;
0468         }
0469         reg = inreg(disp, GC_VSW_HSW_HSP);
0470         fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
0471         fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
0472         hsp = (reg & 0xffff) + 1;
0473         ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
0474         fbi->var.right_margin = hsp - fbi->var.xres;
0475         fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
0476         vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
0477         fbi->var.lower_margin = vsp - fbi->var.yres;
0478         fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
0479     } else if (mode) {
0480         dev_dbg(par->dev, "using supplied mode\n");
0481         fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
0482         fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
0483     } else {
0484         int ret;
0485 
0486         ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
0487                    NULL, 0, NULL, 16);
0488         if (ret == 0 || ret == 4) {
0489             dev_err(par->dev,
0490                 "failed to get initial mode\n");
0491             return -EINVAL;
0492         }
0493     }
0494 
0495     fbi->var.xoffset = 0;
0496     fbi->var.yoffset = 0;
0497     fbi->var.grayscale = 0;
0498     fbi->var.nonstd = 0;
0499     fbi->var.height = -1;
0500     fbi->var.width = -1;
0501     fbi->var.accel_flags = 0;
0502     fbi->var.vmode = FB_VMODE_NONINTERLACED;
0503     fbi->var.activate = FB_ACTIVATE_NOW;
0504     fbi->flags = FBINFO_DEFAULT |
0505 #ifdef __BIG_ENDIAN
0506              FBINFO_FOREIGN_ENDIAN |
0507 #endif
0508              FBINFO_HWACCEL_XPAN |
0509              FBINFO_HWACCEL_YPAN;
0510 
0511     /* check and possibly fix bpp */
0512     if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
0513         dev_err(par->dev, "check_var() failed on initial setup?\n");
0514 
0515     fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
0516              FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
0517     fbi->fix.line_length = (fbi->var.xres_virtual *
0518                 fbi->var.bits_per_pixel) / 8;
0519     fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
0520 
0521     /*
0522      * reserve space for capture buffers and two cursors
0523      * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
0524      */
0525     par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
0526     par->cap_len = 0x1bd800;
0527     par->l1_cfg.sx = 0;
0528     par->l1_cfg.sy = 0;
0529     par->l1_cfg.sw = 720;
0530     par->l1_cfg.sh = 576;
0531     par->l1_cfg.dx = 0;
0532     par->l1_cfg.dy = 0;
0533     par->l1_cfg.dw = 720;
0534     par->l1_cfg.dh = 576;
0535     stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
0536     par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
0537     outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
0538                 (par->l1_stride << 16));
0539     outreg(cap, GC_CAP_CBOA, par->cap_buf);
0540     outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
0541     return 0;
0542 }
0543 
0544 /*
0545  * show some display controller and cursor registers
0546  */
0547 static ssize_t dispregs_show(struct device *dev,
0548                  struct device_attribute *attr, char *buf)
0549 {
0550     struct fb_info *fbi = dev_get_drvdata(dev);
0551     struct mb862xxfb_par *par = fbi->par;
0552     char *ptr = buf;
0553     unsigned int reg;
0554 
0555     for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
0556         ptr += sprintf(ptr, "%08x = %08x\n",
0557                    reg, inreg(disp, reg));
0558 
0559     for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
0560         ptr += sprintf(ptr, "%08x = %08x\n",
0561                    reg, inreg(disp, reg));
0562 
0563     for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
0564         ptr += sprintf(ptr, "%08x = %08x\n",
0565                    reg, inreg(disp, reg));
0566 
0567     for (reg = 0x400; reg <= 0x410; reg += 4)
0568         ptr += sprintf(ptr, "geo %08x = %08x\n",
0569                    reg, inreg(geo, reg));
0570 
0571     for (reg = 0x400; reg <= 0x410; reg += 4)
0572         ptr += sprintf(ptr, "draw %08x = %08x\n",
0573                    reg, inreg(draw, reg));
0574 
0575     for (reg = 0x440; reg <= 0x450; reg += 4)
0576         ptr += sprintf(ptr, "draw %08x = %08x\n",
0577                    reg, inreg(draw, reg));
0578 
0579     return ptr - buf;
0580 }
0581 
0582 static DEVICE_ATTR_RO(dispregs);
0583 
0584 static irqreturn_t mb862xx_intr(int irq, void *dev_id)
0585 {
0586     struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
0587     unsigned long reg_ist, mask;
0588 
0589     if (!par)
0590         return IRQ_NONE;
0591 
0592     if (par->type == BT_CARMINE) {
0593         /* Get Interrupt Status */
0594         reg_ist = inreg(ctrl, GC_CTRL_STATUS);
0595         mask = inreg(ctrl, GC_CTRL_INT_MASK);
0596         if (reg_ist == 0)
0597             return IRQ_HANDLED;
0598 
0599         reg_ist &= mask;
0600         if (reg_ist == 0)
0601             return IRQ_HANDLED;
0602 
0603         /* Clear interrupt status */
0604         outreg(ctrl, 0x0, reg_ist);
0605     } else {
0606         /* Get status */
0607         reg_ist = inreg(host, GC_IST);
0608         mask = inreg(host, GC_IMASK);
0609 
0610         reg_ist &= mask;
0611         if (reg_ist == 0)
0612             return IRQ_HANDLED;
0613 
0614         /* Clear status */
0615         outreg(host, GC_IST, ~reg_ist);
0616     }
0617     return IRQ_HANDLED;
0618 }
0619 
0620 #if defined(CONFIG_FB_MB862XX_LIME)
0621 /*
0622  * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
0623  */
0624 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
0625 {
0626     unsigned long ccf, mmr;
0627     unsigned long ver, rev;
0628 
0629     if (!par)
0630         return -ENODEV;
0631 
0632 #if defined(CONFIG_FB_PRE_INIT_FB)
0633     par->pre_init = 1;
0634 #endif
0635     par->host = par->mmio_base;
0636     par->i2c = par->mmio_base + MB862XX_I2C_BASE;
0637     par->disp = par->mmio_base + MB862XX_DISP_BASE;
0638     par->cap = par->mmio_base + MB862XX_CAP_BASE;
0639     par->draw = par->mmio_base + MB862XX_DRAW_BASE;
0640     par->geo = par->mmio_base + MB862XX_GEO_BASE;
0641     par->pio = par->mmio_base + MB862XX_PIO_BASE;
0642 
0643     par->refclk = GC_DISP_REFCLK_400;
0644 
0645     ver = inreg(host, GC_CID);
0646     rev = inreg(pio, GC_REVISION);
0647     if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
0648         dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
0649              (int)rev & 0xff);
0650         par->type = BT_LIME;
0651         ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
0652         mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
0653     } else {
0654         dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
0655         return -ENODEV;
0656     }
0657 
0658     if (!par->pre_init) {
0659         outreg(host, GC_CCF, ccf);
0660         udelay(200);
0661         outreg(host, GC_MMR, mmr);
0662         udelay(10);
0663     }
0664 
0665     /* interrupt status */
0666     outreg(host, GC_IST, 0);
0667     outreg(host, GC_IMASK, GC_INT_EN);
0668     return 0;
0669 }
0670 
0671 static int of_platform_mb862xx_probe(struct platform_device *ofdev)
0672 {
0673     struct device_node *np = ofdev->dev.of_node;
0674     struct device *dev = &ofdev->dev;
0675     struct mb862xxfb_par *par;
0676     struct fb_info *info;
0677     struct resource res;
0678     resource_size_t res_size;
0679     unsigned long ret = -ENODEV;
0680 
0681     if (of_address_to_resource(np, 0, &res)) {
0682         dev_err(dev, "Invalid address\n");
0683         return -ENXIO;
0684     }
0685 
0686     info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
0687     if (!info)
0688         return -ENOMEM;
0689 
0690     par = info->par;
0691     par->info = info;
0692     par->dev = dev;
0693 
0694     par->irq = irq_of_parse_and_map(np, 0);
0695     if (par->irq == NO_IRQ) {
0696         dev_err(dev, "failed to map irq\n");
0697         ret = -ENODEV;
0698         goto fbrel;
0699     }
0700 
0701     res_size = resource_size(&res);
0702     par->res = request_mem_region(res.start, res_size, DRV_NAME);
0703     if (par->res == NULL) {
0704         dev_err(dev, "Cannot claim framebuffer/mmio\n");
0705         ret = -ENXIO;
0706         goto irqdisp;
0707     }
0708 
0709 #if defined(CONFIG_SOCRATES)
0710     par->gc_mode = &socrates_gc_mode;
0711 #endif
0712 
0713     par->fb_base_phys = res.start;
0714     par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
0715     par->mmio_len = MB862XX_MMIO_SIZE;
0716     if (par->gc_mode)
0717         par->mapped_vram = par->gc_mode->max_vram;
0718     else
0719         par->mapped_vram = MB862XX_MEM_SIZE;
0720 
0721     par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
0722     if (par->fb_base == NULL) {
0723         dev_err(dev, "Cannot map framebuffer\n");
0724         goto rel_reg;
0725     }
0726 
0727     par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
0728     if (par->mmio_base == NULL) {
0729         dev_err(dev, "Cannot map registers\n");
0730         goto fb_unmap;
0731     }
0732 
0733     dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
0734         (u64)par->fb_base_phys, (ulong)par->mapped_vram);
0735     dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
0736         (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
0737 
0738     if (mb862xx_gdc_init(par))
0739         goto io_unmap;
0740 
0741     if (request_irq(par->irq, mb862xx_intr, 0,
0742             DRV_NAME, (void *)par)) {
0743         dev_err(dev, "Cannot request irq\n");
0744         goto io_unmap;
0745     }
0746 
0747     mb862xxfb_init_fbinfo(info);
0748 
0749     if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
0750         dev_err(dev, "Could not allocate cmap for fb_info.\n");
0751         goto free_irq;
0752     }
0753 
0754     if ((info->fbops->fb_set_par)(info))
0755         dev_err(dev, "set_var() failed on initial setup?\n");
0756 
0757     if (register_framebuffer(info)) {
0758         dev_err(dev, "failed to register framebuffer\n");
0759         goto rel_cmap;
0760     }
0761 
0762     dev_set_drvdata(dev, info);
0763 
0764     if (device_create_file(dev, &dev_attr_dispregs))
0765         dev_err(dev, "Can't create sysfs regdump file\n");
0766     return 0;
0767 
0768 rel_cmap:
0769     fb_dealloc_cmap(&info->cmap);
0770 free_irq:
0771     outreg(host, GC_IMASK, 0);
0772     free_irq(par->irq, (void *)par);
0773 io_unmap:
0774     iounmap(par->mmio_base);
0775 fb_unmap:
0776     iounmap(par->fb_base);
0777 rel_reg:
0778     release_mem_region(res.start, res_size);
0779 irqdisp:
0780     irq_dispose_mapping(par->irq);
0781 fbrel:
0782     framebuffer_release(info);
0783     return ret;
0784 }
0785 
0786 static int of_platform_mb862xx_remove(struct platform_device *ofdev)
0787 {
0788     struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
0789     struct mb862xxfb_par *par = fbi->par;
0790     resource_size_t res_size = resource_size(par->res);
0791     unsigned long reg;
0792 
0793     dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
0794 
0795     /* display off */
0796     reg = inreg(disp, GC_DCM1);
0797     reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
0798     outreg(disp, GC_DCM1, reg);
0799 
0800     /* disable interrupts */
0801     outreg(host, GC_IMASK, 0);
0802 
0803     free_irq(par->irq, (void *)par);
0804     irq_dispose_mapping(par->irq);
0805 
0806     device_remove_file(&ofdev->dev, &dev_attr_dispregs);
0807 
0808     unregister_framebuffer(fbi);
0809     fb_dealloc_cmap(&fbi->cmap);
0810 
0811     iounmap(par->mmio_base);
0812     iounmap(par->fb_base);
0813 
0814     release_mem_region(par->res->start, res_size);
0815     framebuffer_release(fbi);
0816     return 0;
0817 }
0818 
0819 /*
0820  * common types
0821  */
0822 static struct of_device_id of_platform_mb862xx_tbl[] = {
0823     { .compatible = "fujitsu,MB86276", },
0824     { .compatible = "fujitsu,lime", },
0825     { .compatible = "fujitsu,MB86277", },
0826     { .compatible = "fujitsu,mint", },
0827     { .compatible = "fujitsu,MB86293", },
0828     { .compatible = "fujitsu,MB86294", },
0829     { .compatible = "fujitsu,coral", },
0830     { /* end */ }
0831 };
0832 MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl);
0833 
0834 static struct platform_driver of_platform_mb862xxfb_driver = {
0835     .driver = {
0836         .name = DRV_NAME,
0837         .of_match_table = of_platform_mb862xx_tbl,
0838     },
0839     .probe      = of_platform_mb862xx_probe,
0840     .remove     = of_platform_mb862xx_remove,
0841 };
0842 #endif
0843 
0844 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
0845 static int coralp_init(struct mb862xxfb_par *par)
0846 {
0847     int cn, ver;
0848 
0849     par->host = par->mmio_base;
0850     par->i2c = par->mmio_base + MB862XX_I2C_BASE;
0851     par->disp = par->mmio_base + MB862XX_DISP_BASE;
0852     par->cap = par->mmio_base + MB862XX_CAP_BASE;
0853     par->draw = par->mmio_base + MB862XX_DRAW_BASE;
0854     par->geo = par->mmio_base + MB862XX_GEO_BASE;
0855     par->pio = par->mmio_base + MB862XX_PIO_BASE;
0856 
0857     par->refclk = GC_DISP_REFCLK_400;
0858 
0859     if (par->mapped_vram >= 0x2000000) {
0860         /* relocate gdc registers space */
0861         writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
0862         udelay(1); /* wait at least 20 bus cycles */
0863     }
0864 
0865     ver = inreg(host, GC_CID);
0866     cn = (ver & GC_CID_CNAME_MSK) >> 8;
0867     ver = ver & GC_CID_VERSION_MSK;
0868     if (cn == 3) {
0869         unsigned long reg;
0870 
0871         dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
0872              (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
0873              par->pdev->revision);
0874         reg = inreg(disp, GC_DCM1);
0875         if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
0876             par->pre_init = 1;
0877 
0878         if (!par->pre_init) {
0879             outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
0880             udelay(200);
0881             outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
0882             udelay(10);
0883         }
0884         /* Clear interrupt status */
0885         outreg(host, GC_IST, 0);
0886     } else {
0887         return -ENODEV;
0888     }
0889 
0890     mb862xx_i2c_init(par);
0891     return 0;
0892 }
0893 
0894 static int init_dram_ctrl(struct mb862xxfb_par *par)
0895 {
0896     unsigned long i = 0;
0897 
0898     /*
0899      * Set io mode first! Spec. says IC may be destroyed
0900      * if not set to SSTL2/LVCMOS before init.
0901      */
0902     outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
0903 
0904     /* DRAM init */
0905     outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
0906     outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
0907     outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
0908            GC_EVB_DCTL_REFRESH_SETTIME2);
0909     outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
0910     outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
0911     outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
0912 
0913     /* DLL reset done? */
0914     while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
0915         udelay(GC_DCTL_INIT_WAIT_INTERVAL);
0916         if (i++ > GC_DCTL_INIT_WAIT_CNT) {
0917             dev_err(par->dev, "VRAM init failed.\n");
0918             return -EINVAL;
0919         }
0920     }
0921     outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
0922     outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
0923     return 0;
0924 }
0925 
0926 static int carmine_init(struct mb862xxfb_par *par)
0927 {
0928     unsigned long reg;
0929 
0930     par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
0931     par->i2c = par->mmio_base + MB86297_I2C_BASE;
0932     par->disp = par->mmio_base + MB86297_DISP0_BASE;
0933     par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
0934     par->cap = par->mmio_base + MB86297_CAP0_BASE;
0935     par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
0936     par->draw = par->mmio_base + MB86297_DRAW_BASE;
0937     par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
0938     par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
0939 
0940     par->refclk = GC_DISP_REFCLK_533;
0941 
0942     /* warm up */
0943     reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
0944     outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
0945 
0946     /* check for engine module revision */
0947     if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
0948         dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
0949              par->pdev->revision);
0950     else
0951         goto err_init;
0952 
0953     reg &= ~GC_CTRL_CLK_EN_2D3D;
0954     outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
0955 
0956     /* set up vram */
0957     if (init_dram_ctrl(par) < 0)
0958         goto err_init;
0959 
0960     outreg(ctrl, GC_CTRL_INT_MASK, 0);
0961     return 0;
0962 
0963 err_init:
0964     outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
0965     return -EINVAL;
0966 }
0967 
0968 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
0969 {
0970     switch (par->type) {
0971     case BT_CORALP:
0972         return coralp_init(par);
0973     case BT_CARMINE:
0974         return carmine_init(par);
0975     default:
0976         return -ENODEV;
0977     }
0978 }
0979 
0980 #define CHIP_ID(id) \
0981     { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
0982 
0983 static const struct pci_device_id mb862xx_pci_tbl[] = {
0984     /* MB86295/MB86296 */
0985     CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
0986     CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
0987     /* MB86297 */
0988     CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
0989     { 0, }
0990 };
0991 
0992 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
0993 
0994 static int mb862xx_pci_probe(struct pci_dev *pdev,
0995                  const struct pci_device_id *ent)
0996 {
0997     struct mb862xxfb_par *par;
0998     struct fb_info *info;
0999     struct device *dev = &pdev->dev;
1000     int ret;
1001 
1002     ret = pci_enable_device(pdev);
1003     if (ret < 0) {
1004         dev_err(dev, "Cannot enable PCI device\n");
1005         goto out;
1006     }
1007 
1008     info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1009     if (!info) {
1010         ret = -ENOMEM;
1011         goto dis_dev;
1012     }
1013 
1014     par = info->par;
1015     par->info = info;
1016     par->dev = dev;
1017     par->pdev = pdev;
1018     par->irq = pdev->irq;
1019 
1020     ret = pci_request_regions(pdev, DRV_NAME);
1021     if (ret < 0) {
1022         dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1023         goto rel_fb;
1024     }
1025 
1026     switch (pdev->device) {
1027     case PCI_DEVICE_ID_FUJITSU_CORALP:
1028     case PCI_DEVICE_ID_FUJITSU_CORALPA:
1029         par->fb_base_phys = pci_resource_start(par->pdev, 0);
1030         par->mapped_vram = CORALP_MEM_SIZE;
1031         if (par->mapped_vram >= 0x2000000) {
1032             par->mmio_base_phys = par->fb_base_phys +
1033                           MB862XX_MMIO_HIGH_BASE;
1034         } else {
1035             par->mmio_base_phys = par->fb_base_phys +
1036                           MB862XX_MMIO_BASE;
1037         }
1038         par->mmio_len = MB862XX_MMIO_SIZE;
1039         par->type = BT_CORALP;
1040         break;
1041     case PCI_DEVICE_ID_FUJITSU_CARMINE:
1042         par->fb_base_phys = pci_resource_start(par->pdev, 2);
1043         par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1044         par->mmio_len = pci_resource_len(par->pdev, 3);
1045         par->mapped_vram = CARMINE_MEM_SIZE;
1046         par->type = BT_CARMINE;
1047         break;
1048     default:
1049         /* should never occur */
1050         ret = -EIO;
1051         goto rel_reg;
1052     }
1053 
1054     par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1055     if (par->fb_base == NULL) {
1056         dev_err(dev, "Cannot map framebuffer\n");
1057         ret = -EIO;
1058         goto rel_reg;
1059     }
1060 
1061     par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1062     if (par->mmio_base == NULL) {
1063         dev_err(dev, "Cannot map registers\n");
1064         ret = -EIO;
1065         goto fb_unmap;
1066     }
1067 
1068     dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1069         (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1070     dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1071         (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1072 
1073     ret = mb862xx_pci_gdc_init(par);
1074     if (ret)
1075         goto io_unmap;
1076 
1077     ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1078               DRV_NAME, (void *)par);
1079     if (ret) {
1080         dev_err(dev, "Cannot request irq\n");
1081         goto io_unmap;
1082     }
1083 
1084     mb862xxfb_init_fbinfo(info);
1085 
1086     if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1087         dev_err(dev, "Could not allocate cmap for fb_info.\n");
1088         ret = -ENOMEM;
1089         goto free_irq;
1090     }
1091 
1092     if ((info->fbops->fb_set_par)(info))
1093         dev_err(dev, "set_var() failed on initial setup?\n");
1094 
1095     ret = register_framebuffer(info);
1096     if (ret < 0) {
1097         dev_err(dev, "failed to register framebuffer\n");
1098         goto rel_cmap;
1099     }
1100 
1101     pci_set_drvdata(pdev, info);
1102 
1103     if (device_create_file(dev, &dev_attr_dispregs))
1104         dev_err(dev, "Can't create sysfs regdump file\n");
1105 
1106     if (par->type == BT_CARMINE)
1107         outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1108     else
1109         outreg(host, GC_IMASK, GC_INT_EN);
1110 
1111     return 0;
1112 
1113 rel_cmap:
1114     fb_dealloc_cmap(&info->cmap);
1115 free_irq:
1116     free_irq(par->irq, (void *)par);
1117 io_unmap:
1118     iounmap(par->mmio_base);
1119 fb_unmap:
1120     iounmap(par->fb_base);
1121 rel_reg:
1122     pci_release_regions(pdev);
1123 rel_fb:
1124     framebuffer_release(info);
1125 dis_dev:
1126     pci_disable_device(pdev);
1127 out:
1128     return ret;
1129 }
1130 
1131 static void mb862xx_pci_remove(struct pci_dev *pdev)
1132 {
1133     struct fb_info *fbi = pci_get_drvdata(pdev);
1134     struct mb862xxfb_par *par = fbi->par;
1135     unsigned long reg;
1136 
1137     dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1138 
1139     /* display off */
1140     reg = inreg(disp, GC_DCM1);
1141     reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1142     outreg(disp, GC_DCM1, reg);
1143 
1144     if (par->type == BT_CARMINE) {
1145         outreg(ctrl, GC_CTRL_INT_MASK, 0);
1146         outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1147     } else {
1148         outreg(host, GC_IMASK, 0);
1149     }
1150 
1151     mb862xx_i2c_exit(par);
1152 
1153     device_remove_file(&pdev->dev, &dev_attr_dispregs);
1154 
1155     unregister_framebuffer(fbi);
1156     fb_dealloc_cmap(&fbi->cmap);
1157 
1158     free_irq(par->irq, (void *)par);
1159     iounmap(par->mmio_base);
1160     iounmap(par->fb_base);
1161 
1162     pci_release_regions(pdev);
1163     framebuffer_release(fbi);
1164     pci_disable_device(pdev);
1165 }
1166 
1167 static struct pci_driver mb862xxfb_pci_driver = {
1168     .name       = DRV_NAME,
1169     .id_table   = mb862xx_pci_tbl,
1170     .probe      = mb862xx_pci_probe,
1171     .remove     = mb862xx_pci_remove,
1172 };
1173 #endif
1174 
1175 static int mb862xxfb_init(void)
1176 {
1177     int ret = -ENODEV;
1178 
1179 #if defined(CONFIG_FB_MB862XX_LIME)
1180     ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1181 #endif
1182 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1183     ret = pci_register_driver(&mb862xxfb_pci_driver);
1184 #endif
1185     return ret;
1186 }
1187 
1188 static void __exit mb862xxfb_exit(void)
1189 {
1190 #if defined(CONFIG_FB_MB862XX_LIME)
1191     platform_driver_unregister(&of_platform_mb862xxfb_driver);
1192 #endif
1193 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1194     pci_unregister_driver(&mb862xxfb_pci_driver);
1195 #endif
1196 }
1197 
1198 module_init(mb862xxfb_init);
1199 module_exit(mb862xxfb_exit);
1200 
1201 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1202 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1203 MODULE_LICENSE("GPL v2");
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