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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *
0004  * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
0005  *
0006  * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
0007  *
0008  */
0009 #ifndef __MATROXFB_H__
0010 #define __MATROXFB_H__
0011 
0012 /* general, but fairly heavy, debugging */
0013 #undef MATROXFB_DEBUG
0014 
0015 /* heavy debugging: */
0016 /* -- logs putc[s], so every time a char is displayed, it's logged */
0017 #undef MATROXFB_DEBUG_HEAVY
0018 
0019 /* This one _could_ cause infinite loops */
0020 /* It _does_ cause lots and lots of messages during idle loops */
0021 #undef MATROXFB_DEBUG_LOOP
0022 
0023 /* Debug register calls, too? */
0024 #undef MATROXFB_DEBUG_REG
0025 
0026 /* Guard accelerator accesses with spin_lock_irqsave... */
0027 #undef MATROXFB_USE_SPINLOCKS
0028 
0029 #include <linux/module.h>
0030 #include <linux/kernel.h>
0031 #include <linux/errno.h>
0032 #include <linux/string.h>
0033 #include <linux/mm.h>
0034 #include <linux/slab.h>
0035 #include <linux/delay.h>
0036 #include <linux/fb.h>
0037 #include <linux/console.h>
0038 #include <linux/selection.h>
0039 #include <linux/ioport.h>
0040 #include <linux/init.h>
0041 #include <linux/timer.h>
0042 #include <linux/pci.h>
0043 #include <linux/spinlock.h>
0044 #include <linux/kd.h>
0045 
0046 #include <asm/io.h>
0047 #include <asm/unaligned.h>
0048 
0049 #if defined(CONFIG_PPC_PMAC)
0050 #include "../macmodes.h"
0051 #endif
0052 
0053 #ifdef MATROXFB_DEBUG
0054 
0055 #define DEBUG
0056 #define DBG(x)      printk(KERN_DEBUG "matroxfb: %s\n", (x));
0057 
0058 #ifdef MATROXFB_DEBUG_HEAVY
0059 #define DBG_HEAVY(x)    DBG(x)
0060 #else /* MATROXFB_DEBUG_HEAVY */
0061 #define DBG_HEAVY(x)    /* DBG_HEAVY */
0062 #endif /* MATROXFB_DEBUG_HEAVY */
0063 
0064 #ifdef MATROXFB_DEBUG_LOOP
0065 #define DBG_LOOP(x) DBG(x)
0066 #else /* MATROXFB_DEBUG_LOOP */
0067 #define DBG_LOOP(x) /* DBG_LOOP */
0068 #endif /* MATROXFB_DEBUG_LOOP */
0069 
0070 #ifdef MATROXFB_DEBUG_REG
0071 #define DBG_REG(x)  DBG(x)
0072 #else /* MATROXFB_DEBUG_REG */
0073 #define DBG_REG(x)  /* DBG_REG */
0074 #endif /* MATROXFB_DEBUG_REG */
0075 
0076 #else /* MATROXFB_DEBUG */
0077 
0078 #define DBG(x)      /* DBG */
0079 #define DBG_HEAVY(x)    /* DBG_HEAVY */
0080 #define DBG_REG(x)  /* DBG_REG */
0081 #define DBG_LOOP(x) /* DBG_LOOP */
0082 
0083 #endif /* MATROXFB_DEBUG */
0084 
0085 #ifdef DEBUG
0086 #define dprintk(X...)   printk(X)
0087 #else
0088 #define dprintk(X...)   no_printk(X)
0089 #endif
0090 
0091 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
0092 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF    0x110A
0093 #endif
0094 #ifndef PCI_SS_VENDOR_ID_MATROX
0095 #define PCI_SS_VENDOR_ID_MATROX     PCI_VENDOR_ID_MATROX
0096 #endif
0097 
0098 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
0099 #define PCI_SS_ID_MATROX_GENERIC        0xFF00
0100 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP    0xFF01
0101 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP  0xFF02
0102 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
0103 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP    0xFF04
0104 #define PCI_SS_ID_MATROX_MGA_G100_PCI       0xFF05
0105 #define PCI_SS_ID_MATROX_MGA_G100_AGP       0x1001
0106 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP    0x2179
0107 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP      0x001E /* 30 */
0108 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP      0x0032 /* 50 */
0109 #endif
0110 
0111 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
0112 #define MX_VISUAL_DIRECTCOLOR   FB_VISUAL_TRUECOLOR
0113 #define MX_VISUAL_PSEUDOCOLOR   FB_VISUAL_PSEUDOCOLOR
0114 
0115 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
0116 
0117 /* G-series and Mystique have (almost) same DAC */
0118 #undef NEED_DAC1064
0119 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
0120 #define NEED_DAC1064 1
0121 #endif
0122 
0123 typedef struct {
0124     void __iomem*   vaddr;
0125 } vaddr_t;
0126 
0127 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) {
0128     return readb(va.vaddr + offs);
0129 }
0130 
0131 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) {
0132     writeb(value, va.vaddr + offs);
0133 }
0134 
0135 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) {
0136     writew(value, va.vaddr + offs);
0137 }
0138 
0139 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) {
0140     return readl(va.vaddr + offs);
0141 }
0142 
0143 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) {
0144     writel(value, va.vaddr + offs);
0145 }
0146 
0147 static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) {
0148 #if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
0149     /*
0150      * iowrite32_rep works for us if:
0151      *  (1) Copies data as 32bit quantities, not byte after byte,
0152      *  (2) Performs LE ordered stores, and
0153      *  (3) It copes with unaligned source (destination is guaranteed to be page
0154      *      aligned and length is guaranteed to be multiple of 4).
0155      */
0156     iowrite32_rep(va.vaddr, src, len >> 2);
0157 #else
0158         u_int32_t __iomem* addr = va.vaddr;
0159 
0160     if ((unsigned long)src & 3) {
0161         while (len >= 4) {
0162             fb_writel(get_unaligned((u32 *)src), addr);
0163             addr++;
0164             len -= 4;
0165             src += 4;
0166         }
0167     } else {
0168         while (len >= 4) {
0169             fb_writel(*(u32 *)src, addr);
0170             addr++;
0171             len -= 4;
0172             src += 4;
0173         }
0174     }
0175 #endif
0176 }
0177 
0178 static inline void vaddr_add(vaddr_t* va, unsigned long offs) {
0179     va->vaddr += offs;
0180 }
0181 
0182 static inline void __iomem* vaddr_va(vaddr_t va) {
0183     return va.vaddr;
0184 }
0185 
0186 struct my_timming {
0187     unsigned int pixclock;
0188     int mnp;
0189     unsigned int crtc;
0190     unsigned int HDisplay;
0191     unsigned int HSyncStart;
0192     unsigned int HSyncEnd;
0193     unsigned int HTotal;
0194     unsigned int VDisplay;
0195     unsigned int VSyncStart;
0196     unsigned int VSyncEnd;
0197     unsigned int VTotal;
0198     unsigned int sync;
0199     int      dblscan;
0200     int      interlaced;
0201     unsigned int delay; /* CRTC delay */
0202 };
0203 
0204 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL };
0205 
0206 struct matrox_pll_cache {
0207     unsigned int    valid;
0208     struct {
0209         unsigned int    mnp_key;
0210         unsigned int    mnp_value;
0211               } data[4];
0212 };
0213 
0214 struct matrox_pll_limits {
0215     unsigned int    vcomin;
0216     unsigned int    vcomax;
0217 };
0218 
0219 struct matrox_pll_features {
0220     unsigned int    vco_freq_min;
0221     unsigned int    ref_freq;
0222     unsigned int    feed_div_min;
0223     unsigned int    feed_div_max;
0224     unsigned int    in_div_min;
0225     unsigned int    in_div_max;
0226     unsigned int    post_shift_max;
0227 };
0228 
0229 struct matroxfb_par
0230 {
0231     unsigned int    final_bppShift;
0232     unsigned int    cmap_len;
0233     struct {
0234         unsigned int bytes;
0235         unsigned int pixels;
0236         unsigned int chunks;
0237               } ydstorg;
0238 };
0239 
0240 struct matrox_fb_info;
0241 
0242 struct matrox_DAC1064_features {
0243     u_int8_t    xvrefctrl;
0244     u_int8_t    xmiscctrl;
0245 };
0246 
0247 /* current hardware status */
0248 struct mavenregs {
0249     u_int8_t regs[256];
0250     int  mode;
0251     int  vlines;
0252     int  xtal;
0253     int  fv;
0254 
0255     u_int16_t htotal;
0256     u_int16_t hcorr;
0257 };
0258 
0259 struct matrox_crtc2 {
0260     u_int32_t ctl;
0261 };
0262 
0263 struct matrox_hw_state {
0264     u_int32_t   MXoptionReg;
0265     unsigned char   DACclk[6];
0266     unsigned char   DACreg[80];
0267     unsigned char   MiscOutReg;
0268     unsigned char   DACpal[768];
0269     unsigned char   CRTC[25];
0270     unsigned char   CRTCEXT[9];
0271     unsigned char   SEQ[5];
0272     /* unused for MGA mode, but who knows... */
0273     unsigned char   GCTL[9];
0274     /* unused for MGA mode, but who knows... */
0275     unsigned char   ATTR[21];
0276 
0277     /* TVOut only */
0278     struct mavenregs    maven;
0279 
0280     struct matrox_crtc2 crtc2;
0281 };
0282 
0283 struct matrox_accel_data {
0284 #ifdef CONFIG_FB_MATROX_MILLENIUM
0285     unsigned char   ramdac_rev;
0286 #endif
0287     u_int32_t   m_dwg_rect;
0288     u_int32_t   m_opmode;
0289     u_int32_t   m_access;
0290     u_int32_t   m_pitch;
0291 };
0292 
0293 struct v4l2_queryctrl;
0294 struct v4l2_control;
0295 
0296 struct matrox_altout {
0297     const char  *name;
0298     int     (*compute)(void* altout_dev, struct my_timming* input);
0299     int     (*program)(void* altout_dev);
0300     int     (*start)(void* altout_dev);
0301     int     (*verifymode)(void* altout_dev, u_int32_t mode);
0302     int     (*getqueryctrl)(void* altout_dev,
0303                     struct v4l2_queryctrl* ctrl);
0304     int     (*getctrl)(void* altout_dev, 
0305                    struct v4l2_control* ctrl);
0306     int     (*setctrl)(void* altout_dev, 
0307                    struct v4l2_control* ctrl);
0308 };
0309 
0310 #define MATROXFB_SRC_NONE   0
0311 #define MATROXFB_SRC_CRTC1  1
0312 #define MATROXFB_SRC_CRTC2  2
0313 
0314 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 };
0315 
0316 struct matrox_bios {
0317     unsigned int    bios_valid : 1;
0318     unsigned int    pins_len;
0319     unsigned char   pins[128];
0320     struct {
0321         unsigned char vMaj, vMin, vRev;
0322               } version;
0323     struct {
0324         unsigned char state, tvout;
0325               } output;
0326 };
0327 
0328 struct matrox_switch;
0329 struct matroxfb_driver;
0330 struct matroxfb_dh_fb_info;
0331 
0332 struct matrox_vsync {
0333     wait_queue_head_t   wait;
0334     unsigned int        cnt;
0335 };
0336 
0337 struct matrox_fb_info {
0338     struct fb_info      fbcon;
0339 
0340     struct list_head    next_fb;
0341 
0342     int         dead;
0343     int                     initialized;
0344     unsigned int        usecount;
0345 
0346     unsigned int        userusecount;
0347     unsigned long       irq_flags;
0348 
0349     struct matroxfb_par curr;
0350     struct matrox_hw_state  hw;
0351 
0352     struct matrox_accel_data accel;
0353 
0354     struct pci_dev*     pcidev;
0355 
0356     struct {
0357         struct matrox_vsync vsync;
0358         unsigned int    pixclock;
0359         int     mnp;
0360         int     panpos;
0361                   } crtc1;
0362     struct {
0363         struct matrox_vsync vsync;
0364         unsigned int    pixclock;
0365         int     mnp;
0366     struct matroxfb_dh_fb_info* info;
0367     struct rw_semaphore lock;
0368                   } crtc2;
0369     struct {
0370     struct rw_semaphore lock;
0371     struct {
0372         int brightness, contrast, saturation, hue, gamma;
0373         int testout, deflicker;
0374                 } tvo_params;
0375                   } altout;
0376 #define MATROXFB_MAX_OUTPUTS        3
0377     struct {
0378     unsigned int        src;
0379     struct matrox_altout*   output;
0380     void*           data;
0381     unsigned int        mode;
0382     unsigned int        default_src;
0383                   } outputs[MATROXFB_MAX_OUTPUTS];
0384 
0385 #define MATROXFB_MAX_FB_DRIVERS     5
0386     struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]);
0387     void*           (drivers_data[MATROXFB_MAX_FB_DRIVERS]);
0388     unsigned int        drivers_count;
0389 
0390     struct {
0391     unsigned long   base;   /* physical */
0392     vaddr_t     vbase;  /* CPU view */
0393     unsigned int    len;
0394     unsigned int    len_usable;
0395     unsigned int    len_maximum;
0396               } video;
0397 
0398     struct {
0399     unsigned long   base;   /* physical */
0400     vaddr_t     vbase;  /* CPU view */
0401     unsigned int    len;
0402               } mmio;
0403 
0404     unsigned int    max_pixel_clock;
0405     unsigned int    max_pixel_clock_panellink;
0406 
0407     struct matrox_switch*   hw_switch;
0408 
0409     struct {
0410         struct matrox_pll_features pll;
0411         struct matrox_DAC1064_features DAC1064;
0412                   } features;
0413     struct {
0414         spinlock_t  DAC;
0415         spinlock_t  accel;
0416                   } lock;
0417 
0418     enum mga_chip       chip;
0419 
0420     int         interleave;
0421     int         millenium;
0422     int         milleniumII;
0423     struct {
0424         int     cfb4;
0425         const int*  vxres;
0426         int     cross4MB;
0427         int     text;
0428         int     plnwt;
0429         int     srcorg;
0430                   } capable;
0431     int         wc_cookie;
0432     struct {
0433         int     precise_width;
0434         int     mga_24bpp_fix;
0435         int     novga;
0436         int     nobios;
0437         int     nopciretry;
0438         int     noinit;
0439         int     sgram;
0440         int     support32MB;
0441 
0442         int     accelerator;
0443         int     text_type_aux;
0444         int     video64bits;
0445         int     crtc2;
0446         int     maven_capable;
0447         unsigned int    vgastep;
0448         unsigned int    textmode;
0449         unsigned int    textstep;
0450         unsigned int    textvram;   /* character cells */
0451         unsigned int    ydstorg;    /* offset in bytes from video start to usable memory */
0452                         /* 0 except for 6MB Millenium */
0453         int     memtype;
0454         int     g450dac;
0455         int     dfp_type;
0456         int     panellink;  /* G400 DFP possible (not G450/G550) */
0457         int     dualhead;
0458         unsigned int    fbResource;
0459                   } devflags;
0460     struct fb_ops       fbops;
0461     struct matrox_bios  bios;
0462     struct {
0463         struct matrox_pll_limits    pixel;
0464         struct matrox_pll_limits    system;
0465         struct matrox_pll_limits    video;
0466                   } limits;
0467     struct {
0468         struct matrox_pll_cache pixel;
0469         struct matrox_pll_cache system;
0470         struct matrox_pll_cache video;
0471                       } cache;
0472     struct {
0473         struct {
0474             unsigned int    video;
0475             unsigned int    system;
0476                       } pll;
0477         struct {
0478             u_int32_t   opt;
0479             u_int32_t   opt2;
0480             u_int32_t   opt3;
0481             u_int32_t   mctlwtst;
0482             u_int32_t   mctlwtst_core;
0483             u_int32_t   memmisc;
0484             u_int32_t   memrdbk;
0485             u_int32_t   maccess;
0486                       } reg;
0487         struct {
0488             unsigned int    ddr:1,
0489                             emrswen:1,
0490                     dll:1;
0491                       } memory;
0492                   } values;
0493     u_int32_t cmap[16];
0494 };
0495 
0496 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
0497 
0498 struct matrox_switch {
0499     int (*preinit)(struct matrox_fb_info *minfo);
0500     void    (*reset)(struct matrox_fb_info *minfo);
0501     int (*init)(struct matrox_fb_info *minfo, struct my_timming*);
0502     void    (*restore)(struct matrox_fb_info *minfo);
0503 };
0504 
0505 struct matroxfb_driver {
0506     struct list_head    node;
0507     char*           name;
0508     void*           (*probe)(struct matrox_fb_info* info);
0509     void            (*remove)(struct matrox_fb_info* info, void* data);
0510 };
0511 
0512 int matroxfb_register_driver(struct matroxfb_driver* drv);
0513 void matroxfb_unregister_driver(struct matroxfb_driver* drv);
0514 
0515 #define PCI_OPTION_REG  0x40
0516 #define   PCI_OPTION_ENABLE_ROM     0x40000000
0517 
0518 #define PCI_MGA_INDEX   0x44
0519 #define PCI_MGA_DATA    0x48
0520 #define PCI_OPTION2_REG 0x50
0521 #define PCI_OPTION3_REG 0x54
0522 #define PCI_MEMMISC_REG 0x58
0523 
0524 #define M_DWGCTL    0x1C00
0525 #define M_MACCESS   0x1C04
0526 #define M_CTLWTST   0x1C08
0527 
0528 #define M_PLNWT     0x1C1C
0529 
0530 #define M_BCOL      0x1C20
0531 #define M_FCOL      0x1C24
0532 
0533 #define M_SGN       0x1C58
0534 #define M_LEN       0x1C5C
0535 #define M_AR0       0x1C60
0536 #define M_AR1       0x1C64
0537 #define M_AR2       0x1C68
0538 #define M_AR3       0x1C6C
0539 #define M_AR4       0x1C70
0540 #define M_AR5       0x1C74
0541 #define M_AR6       0x1C78
0542 
0543 #define M_CXBNDRY   0x1C80
0544 #define M_FXBNDRY   0x1C84
0545 #define M_YDSTLEN   0x1C88
0546 #define M_PITCH     0x1C8C
0547 #define M_YDST      0x1C90
0548 #define M_YDSTORG   0x1C94
0549 #define M_YTOP      0x1C98
0550 #define M_YBOT      0x1C9C
0551 
0552 /* mystique only */
0553 #define M_CACHEFLUSH    0x1FFF
0554 
0555 #define M_EXEC      0x0100
0556 
0557 #define M_DWG_TRAP  0x04
0558 #define M_DWG_BITBLT    0x08
0559 #define M_DWG_ILOAD 0x09
0560 
0561 #define M_DWG_LINEAR    0x0080
0562 #define M_DWG_SOLID 0x0800
0563 #define M_DWG_ARZERO    0x1000
0564 #define M_DWG_SGNZERO   0x2000
0565 #define M_DWG_SHIFTZERO 0x4000
0566 
0567 #define M_DWG_REPLACE   0x000C0000
0568 #define M_DWG_REPLACE2  (M_DWG_REPLACE | 0x40)
0569 #define M_DWG_XOR   0x00060010
0570 
0571 #define M_DWG_BFCOL 0x04000000
0572 #define M_DWG_BMONOWF   0x08000000
0573 
0574 #define M_DWG_TRANSC    0x40000000
0575 
0576 #define M_FIFOSTATUS    0x1E10
0577 #define M_STATUS    0x1E14
0578 #define M_ICLEAR    0x1E18
0579 #define M_IEN       0x1E1C
0580 
0581 #define M_VCOUNT    0x1E20
0582 
0583 #define M_RESET     0x1E40
0584 #define M_MEMRDBK   0x1E44
0585 
0586 #define M_AGP2PLL   0x1E4C
0587 
0588 #define M_OPMODE    0x1E54
0589 #define     M_OPMODE_DMA_GEN_WRITE  0x00
0590 #define     M_OPMODE_DMA_BLIT       0x04
0591 #define     M_OPMODE_DMA_VECTOR_WRITE   0x08
0592 #define     M_OPMODE_DMA_LE     0x0000      /* little endian - no transformation */
0593 #define     M_OPMODE_DMA_BE_8BPP    0x0000
0594 #define     M_OPMODE_DMA_BE_16BPP   0x0100
0595 #define     M_OPMODE_DMA_BE_32BPP   0x0200
0596 #define     M_OPMODE_DIR_LE     0x000000    /* little endian - no transformation */
0597 #define     M_OPMODE_DIR_BE_8BPP    0x000000
0598 #define     M_OPMODE_DIR_BE_16BPP   0x010000
0599 #define     M_OPMODE_DIR_BE_32BPP   0x020000
0600 
0601 #define M_ATTR_INDEX    0x1FC0
0602 #define M_ATTR_DATA 0x1FC1
0603 
0604 #define M_MISC_REG  0x1FC2
0605 #define M_3C2_RD    0x1FC2
0606 
0607 #define M_SEQ_INDEX 0x1FC4
0608 #define M_SEQ_DATA  0x1FC5
0609 #define     M_SEQ1      0x01
0610 #define        M_SEQ1_SCROFF        0x20
0611 
0612 #define M_MISC_REG_READ 0x1FCC
0613 
0614 #define M_GRAPHICS_INDEX 0x1FCE
0615 #define M_GRAPHICS_DATA 0x1FCF
0616 
0617 #define M_CRTC_INDEX    0x1FD4
0618 
0619 #define M_ATTR_RESET    0x1FDA
0620 #define M_3DA_WR    0x1FDA
0621 #define M_INSTS1    0x1FDA
0622 
0623 #define M_EXTVGA_INDEX  0x1FDE
0624 #define M_EXTVGA_DATA   0x1FDF
0625 
0626 /* G200 only */
0627 #define M_SRCORG    0x2CB4
0628 #define M_DSTORG    0x2CB8
0629 
0630 #define M_RAMDAC_BASE   0x3C00
0631 
0632 /* fortunately, same on TVP3026 and MGA1064 */
0633 #define M_DAC_REG   (M_RAMDAC_BASE+0)
0634 #define M_DAC_VAL   (M_RAMDAC_BASE+1)
0635 #define M_PALETTE_MASK  (M_RAMDAC_BASE+2)
0636 
0637 #define M_X_INDEX   0x00
0638 #define M_X_DATAREG 0x0A
0639 
0640 #define DAC_XGENIOCTRL      0x2A
0641 #define DAC_XGENIODATA      0x2B
0642 
0643 #define M_C2CTL     0x3C10
0644 
0645 #define MX_OPTION_BSWAP         0x00000000
0646 
0647 #ifdef __LITTLE_ENDIAN
0648 #define M_OPMODE_4BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
0649 #define M_OPMODE_8BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
0650 #define M_OPMODE_16BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
0651 #define M_OPMODE_24BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
0652 #define M_OPMODE_32BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
0653 #else
0654 #ifdef __BIG_ENDIAN
0655 #define M_OPMODE_4BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE       | M_OPMODE_DMA_BLIT)   /* TODO */
0656 #define M_OPMODE_8BPP   (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP  | M_OPMODE_DMA_BLIT)
0657 #define M_OPMODE_16BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
0658 #define M_OPMODE_24BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP  | M_OPMODE_DMA_BLIT)   /* TODO, ?32 */
0659 #define M_OPMODE_32BPP  (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
0660 #else
0661 #error "Byte ordering have to be defined. Cannot continue."
0662 #endif
0663 #endif
0664 
0665 #define mga_inb(addr)       mga_readb(minfo->mmio.vbase, (addr))
0666 #define mga_inl(addr)       mga_readl(minfo->mmio.vbase, (addr))
0667 #define mga_outb(addr,val)  mga_writeb(minfo->mmio.vbase, (addr), (val))
0668 #define mga_outw(addr,val)  mga_writew(minfo->mmio.vbase, (addr), (val))
0669 #define mga_outl(addr,val)  mga_writel(minfo->mmio.vbase, (addr), (val))
0670 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
0671 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
0672 
0673 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
0674 
0675 #define WaitTillIdle()  do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0)
0676 
0677 /* code speedup */
0678 #ifdef CONFIG_FB_MATROX_MILLENIUM
0679 #define isInterleave(x)  (x->interleave)
0680 #define isMillenium(x)   (x->millenium)
0681 #define isMilleniumII(x) (x->milleniumII)
0682 #else
0683 #define isInterleave(x)  (0)
0684 #define isMillenium(x)   (0)
0685 #define isMilleniumII(x) (0)
0686 #endif
0687 
0688 #define matroxfb_DAC_lock()                   spin_lock(&minfo->lock.DAC)
0689 #define matroxfb_DAC_unlock()                 spin_unlock(&minfo->lock.DAC)
0690 #define matroxfb_DAC_lock_irqsave(flags)      spin_lock_irqsave(&minfo->lock.DAC, flags)
0691 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags)
0692 extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg,
0693                  int val);
0694 extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg);
0695 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
0696 extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc);
0697 extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable);
0698 
0699 #ifdef MATROXFB_USE_SPINLOCKS
0700 #define CRITBEGIN  spin_lock_irqsave(&minfo->lock.accel, critflags);
0701 #define CRITEND    spin_unlock_irqrestore(&minfo->lock.accel, critflags);
0702 #define CRITFLAGS  unsigned long critflags;
0703 #else
0704 #define CRITBEGIN
0705 #define CRITEND
0706 #define CRITFLAGS
0707 #endif
0708 
0709 #endif  /* __MATROXFB_H__ */
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