fbdev/kyro/STG4000VTG.c

0001 /*
0002  *  linux/drivers/video/kyro/STG4000VTG.c
0003  *
0004  *  Copyright (C) 2002 STMicroelectronics
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file COPYING in the main directory of this archive
0008  * for more details.
0009  */
0010
0011 #include <linux/types.h>
0012 #include <video/kyro.h>
0013
0014 #include "STG4000Reg.h"
0015 #include "STG4000Interface.h"
0016
0017 void DisableVGA(volatile STG4000REG __iomem *pSTGReg)
0018 {
0019     u32 tmp;
0020     volatile u32 count = 0, i;
0021
0022     /* Reset the VGA registers */
0023     tmp = STG_READ_REG(SoftwareReset);
0024     CLEAR_BIT(8);
0025     STG_WRITE_REG(SoftwareReset, tmp);
0026
0027     /* Just for Delay */
0028     for (i = 0; i < 1000; i++) {
0029         count++;
0030     }
0031
0032     /* Pull-out the VGA registers from reset */
0033     tmp = STG_READ_REG(SoftwareReset);
0034     tmp |= SET_BIT(8);
0035     STG_WRITE_REG(SoftwareReset, tmp);
0036 }
0037
0038 void StopVTG(volatile STG4000REG __iomem *pSTGReg)
0039 {
0040     u32 tmp = 0;
0041
0042     /* Stop Ver and Hor Sync Generator */
0043     tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
0044     CLEAR_BIT(31);
0045     STG_WRITE_REG(DACSyncCtrl, tmp);
0046 }
0047
0048 void StartVTG(volatile STG4000REG __iomem *pSTGReg)
0049 {
0050     u32 tmp = 0;
0051
0052     /* Start Ver and Hor Sync Generator */
0053     tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31));
0054     CLEAR_BIT(0);
0055     CLEAR_BIT(2);
0056     STG_WRITE_REG(DACSyncCtrl, tmp);
0057 }
0058
0059 void SetupVTG(volatile STG4000REG __iomem *pSTGReg,
0060           const struct kyrofb_info * pTiming)
0061 {
0062     u32 tmp = 0;
0063     u32 margins = 0;
0064     u32 ulBorder;
0065     u32 xRes = pTiming->XRES;
0066     u32 yRes = pTiming->YRES;
0067
0068     /* Horizontal */
0069     u32 HAddrTime, HRightBorder, HLeftBorder;
0070     u32 HBackPorcStrt, HFrontPorchStrt, HTotal,
0071         HLeftBorderStrt, HRightBorderStrt, HDisplayStrt;
0072
0073     /* Vertical */
0074     u32 VDisplayStrt, VBottomBorder, VTopBorder;
0075     u32 VBackPorchStrt, VTotal, VTopBorderStrt,
0076         VFrontPorchStrt, VBottomBorderStrt, VAddrTime;
0077
0078     /* Need to calculate the right border */
0079     if ((xRes == 640) && (yRes == 480)) {
0080         if ((pTiming->VFREQ == 60) || (pTiming->VFREQ == 72)) {
0081             margins = 8;
0082         }
0083     }
0084
0085     /* Work out the Border */
0086     ulBorder =
0087         (pTiming->HTot -
0088          (pTiming->HST + (pTiming->HBP - margins) + xRes +
0089           (pTiming->HFP - margins))) >> 1;
0090
0091     /* Border the same for Vertical and Horizontal */
0092     VBottomBorder = HLeftBorder = VTopBorder = HRightBorder = ulBorder;
0093
0094     /************ Get Timing values for Horizontal ******************/
0095     HAddrTime = xRes;
0096     HBackPorcStrt = pTiming->HST;
0097     HTotal = pTiming->HTot;
0098     HDisplayStrt =
0099         pTiming->HST + (pTiming->HBP - margins) + HLeftBorder;
0100     HLeftBorderStrt = HDisplayStrt - HLeftBorder;
0101     HFrontPorchStrt =
0102         pTiming->HST + (pTiming->HBP - margins) + HLeftBorder +
0103         HAddrTime + HRightBorder;
0104     HRightBorderStrt = HFrontPorchStrt - HRightBorder;
0105
0106     /************ Get Timing values for Vertical ******************/
0107     VAddrTime = yRes;
0108     VBackPorchStrt = pTiming->VST;
0109     VTotal = pTiming->VTot;
0110     VDisplayStrt =
0111         pTiming->VST + (pTiming->VBP - margins) + VTopBorder;
0112     VTopBorderStrt = VDisplayStrt - VTopBorder;
0113     VFrontPorchStrt =
0114         pTiming->VST + (pTiming->VBP - margins) + VTopBorder +
0115         VAddrTime + VBottomBorder;
0116     VBottomBorderStrt = VFrontPorchStrt - VBottomBorder;
0117
0118     /* Set Hor Timing 1, 2, 3 */
0119     tmp = STG_READ_REG(DACHorTim1);
0120     CLEAR_BITS_FRM_TO(0, 11);
0121     CLEAR_BITS_FRM_TO(16, 27);
0122     tmp |= (HTotal) | (HBackPorcStrt << 16);
0123     STG_WRITE_REG(DACHorTim1, tmp);
0124
0125     tmp = STG_READ_REG(DACHorTim2);
0126     CLEAR_BITS_FRM_TO(0, 11);
0127     CLEAR_BITS_FRM_TO(16, 27);
0128     tmp |= (HDisplayStrt << 16) | HLeftBorderStrt;
0129     STG_WRITE_REG(DACHorTim2, tmp);
0130
0131     tmp = STG_READ_REG(DACHorTim3);
0132     CLEAR_BITS_FRM_TO(0, 11);
0133     CLEAR_BITS_FRM_TO(16, 27);
0134     tmp |= (HFrontPorchStrt << 16) | HRightBorderStrt;
0135     STG_WRITE_REG(DACHorTim3, tmp);
0136
0137     /* Set Ver Timing 1, 2, 3 */
0138     tmp = STG_READ_REG(DACVerTim1);
0139     CLEAR_BITS_FRM_TO(0, 11);
0140     CLEAR_BITS_FRM_TO(16, 27);
0141     tmp |= (VBackPorchStrt << 16) | (VTotal);
0142     STG_WRITE_REG(DACVerTim1, tmp);
0143
0144     tmp = STG_READ_REG(DACVerTim2);
0145     CLEAR_BITS_FRM_TO(0, 11);
0146     CLEAR_BITS_FRM_TO(16, 27);
0147     tmp |= (VDisplayStrt << 16) | VTopBorderStrt;
0148     STG_WRITE_REG(DACVerTim2, tmp);
0149
0150     tmp = STG_READ_REG(DACVerTim3);
0151     CLEAR_BITS_FRM_TO(0, 11);
0152     CLEAR_BITS_FRM_TO(16, 27);
0153     tmp |= (VFrontPorchStrt << 16) | VBottomBorderStrt;
0154     STG_WRITE_REG(DACVerTim3, tmp);
0155
0156     /* Set Verical and Horizontal Polarity */
0157     tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1);
0158
0159     if ((pTiming->HSP > 0) && (pTiming->VSP < 0)) { /* +hsync -vsync */
0160         tmp &= ~0x8;
0161     } else if ((pTiming->HSP < 0) && (pTiming->VSP > 0)) {  /* -hsync +vsync */
0162         tmp &= ~0x2;
0163     } else if ((pTiming->HSP < 0) && (pTiming->VSP < 0)) {  /* -hsync -vsync */
0164         tmp &= ~0xA;
0165     } else if ((pTiming->HSP > 0) && (pTiming->VSP > 0)) {  /* +hsync -vsync */
0166         tmp &= ~0x0;
0167     }
0168
0169     STG_WRITE_REG(DACSyncCtrl, tmp);
0170 }