fbdev/kyro/STG4000Reg.h

0001 /*
0002  *  linux/drivers/video/kyro/STG4000Reg.h
0003  *
0004  *  Copyright (C) 2002 STMicroelectronics
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file COPYING in the main directory of this archive
0008  * for more details.
0009  */
0010
0011 #ifndef _STG4000REG_H
0012 #define _STG4000REG_H
0013
0014 #define DWFILL unsigned long :32
0015 #define WFILL unsigned short :16
0016
0017 /*
0018  * Macros that access memory mapped card registers in PCI space
0019  * Add an appropriate section for your OS or processor architecture.
0020  */
0021 #if defined(__KERNEL__)
0022 #include <asm/page.h>
0023 #include <asm/io.h>
0024 #define STG_WRITE_REG(reg,data) (writel(data,&pSTGReg->reg))
0025 #define STG_READ_REG(reg)      (readl(&pSTGReg->reg))
0026 #else
0027 #define STG_WRITE_REG(reg,data) (pSTGReg->reg = data)
0028 #define STG_READ_REG(reg)      (pSTGReg->reg)
0029 #endif /* __KERNEL__ */
0030
0031 #define SET_BIT(n) (1<<(n))
0032 #define CLEAR_BIT(n) (tmp &= ~(1<<n))
0033 #define CLEAR_BITS_FRM_TO(frm, to) \
0034 {\
0035 int i; \
0036     for(i = frm; i<= to; i++) \
0037     { \
0038         tmp &= ~(1<<i); \
0039     } \
0040 }
0041
0042 #define CLEAR_BIT_2(n) (usTemp &= ~(1<<n))
0043 #define CLEAR_BITS_FRM_TO_2(frm, to) \
0044 {\
0045 int i; \
0046     for(i = frm; i<= to; i++) \
0047     { \
0048         usTemp &= ~(1<<i); \
0049     } \
0050 }
0051
0052 /* LUT select */
0053 typedef enum _LUT_USES {
0054     NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
0055 } LUT_USES;
0056
0057 /* Primary surface pixel format select */
0058 typedef enum _PIXEL_FORMAT {
0059     _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
0060 } PIXEL_FORMAT;
0061
0062 /* Overlay blending mode select */
0063 typedef enum _BLEND_MODE {
0064     GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
0065     CK_PIXEL_ALPHA, CK_GLOBAL_ALPHA
0066 } OVRL_BLEND_MODE;
0067
0068 /* Overlay Pixel format select */
0069 typedef enum _OVRL_PIX_FORMAT {
0070     UYVY, VYUY, YUYV, YVYU
0071 } OVRL_PIX_FORMAT;
0072
0073 /* Register Table */
0074 typedef struct {
0075     /* 0h  */
0076     volatile u32 Thread0Enable; /* 0x0000 */
0077     volatile u32 Thread1Enable; /* 0x0004 */
0078     volatile u32 Thread0Recover;    /* 0x0008 */
0079     volatile u32 Thread1Recover;    /* 0x000C */
0080     volatile u32 Thread0Step;   /* 0x0010 */
0081     volatile u32 Thread1Step;   /* 0x0014 */
0082     volatile u32 VideoInStatus; /* 0x0018 */
0083     volatile u32 Core2InSignStart;  /* 0x001C */
0084     volatile u32 Core1ResetVector;  /* 0x0020 */
0085     volatile u32 Core1ROMOffset;    /* 0x0024 */
0086     volatile u32 Core1ArbiterPriority;  /* 0x0028 */
0087     volatile u32 VideoInControl;    /* 0x002C */
0088     volatile u32 VideoInReg0CtrlA;  /* 0x0030 */
0089     volatile u32 VideoInReg0CtrlB;  /* 0x0034 */
0090     volatile u32 VideoInReg1CtrlA;  /* 0x0038 */
0091     volatile u32 VideoInReg1CtrlB;  /* 0x003C */
0092     volatile u32 Thread0Kicker; /* 0x0040 */
0093     volatile u32 Core2InputSign;    /* 0x0044 */
0094     volatile u32 Thread0ProgCtr;    /* 0x0048 */
0095     volatile u32 Thread1ProgCtr;    /* 0x004C */
0096     volatile u32 Thread1Kicker; /* 0x0050 */
0097     volatile u32 GPRegister1;   /* 0x0054 */
0098     volatile u32 GPRegister2;   /* 0x0058 */
0099     volatile u32 GPRegister3;   /* 0x005C */
0100     volatile u32 GPRegister4;   /* 0x0060 */
0101     volatile u32 SerialIntA;    /* 0x0064 */
0102
0103     volatile u32 Fill0[6];  /* GAP 0x0068 - 0x007C */
0104
0105     volatile u32 SoftwareReset; /* 0x0080 */
0106     volatile u32 SerialIntB;    /* 0x0084 */
0107
0108     volatile u32 Fill1[37]; /* GAP 0x0088 - 0x011C */
0109
0110     volatile u32 ROMELQV;   /* 0x011C */
0111     volatile u32 WLWH;  /* 0x0120 */
0112     volatile u32 ROMELWL;   /* 0x0124 */
0113
0114     volatile u32 dwFill_1;  /* GAP 0x0128 */
0115
0116     volatile u32 IntStatus; /* 0x012C */
0117     volatile u32 IntMask;   /* 0x0130 */
0118     volatile u32 IntClear;  /* 0x0134 */
0119
0120     volatile u32 Fill2[6];  /* GAP 0x0138 - 0x014C */
0121
0122     volatile u32 ROMGPIOA;  /* 0x0150 */
0123     volatile u32 ROMGPIOB;  /* 0x0154 */
0124     volatile u32 ROMGPIOC;  /* 0x0158 */
0125     volatile u32 ROMGPIOD;  /* 0x015C */
0126
0127     volatile u32 Fill3[2];  /* GAP 0x0160 - 0x0168 */
0128
0129     volatile u32 AGPIntID;  /* 0x0168 */
0130     volatile u32 AGPIntClassCode;   /* 0x016C */
0131     volatile u32 AGPIntBIST;    /* 0x0170 */
0132     volatile u32 AGPIntSSID;    /* 0x0174 */
0133     volatile u32 AGPIntPMCSR;   /* 0x0178 */
0134     volatile u32 VGAFrameBufBase;   /* 0x017C */
0135     volatile u32 VGANotify; /* 0x0180 */
0136     volatile u32 DACPLLMode;    /* 0x0184 */
0137     volatile u32 Core1VideoClockDiv;    /* 0x0188 */
0138     volatile u32 AGPIntStat;    /* 0x018C */
0139
0140     /*
0141        volatile u32 Fill4[0x0400/4 - 0x0190/4]; //GAP 0x0190 - 0x0400
0142        volatile u32 Fill5[0x05FC/4 - 0x0400/4]; //GAP 0x0400 - 0x05FC Fog Table
0143        volatile u32 Fill6[0x0604/4 - 0x0600/4]; //GAP 0x0600 - 0x0604
0144        volatile u32 Fill7[0x0680/4 - 0x0608/4]; //GAP 0x0608 - 0x0680
0145        volatile u32 Fill8[0x07FC/4 - 0x0684/4]; //GAP 0x0684 - 0x07FC
0146      */
0147     volatile u32 Fill4[412];    /* 0x0190 - 0x07FC */
0148
0149     volatile u32 TACtrlStreamBase;  /* 0x0800 */
0150     volatile u32 TAObjDataBase; /* 0x0804 */
0151     volatile u32 TAPtrDataBase; /* 0x0808 */
0152     volatile u32 TARegionDataBase;  /* 0x080C */
0153     volatile u32 TATailPtrBase; /* 0x0810 */
0154     volatile u32 TAPtrRegionSize;   /* 0x0814 */
0155     volatile u32 TAConfiguration;   /* 0x0818 */
0156     volatile u32 TAObjDataStartAddr;    /* 0x081C */
0157     volatile u32 TAObjDataEndAddr;  /* 0x0820 */
0158     volatile u32 TAXScreenClip; /* 0x0824 */
0159     volatile u32 TAYScreenClip; /* 0x0828 */
0160     volatile u32 TARHWClamp;    /* 0x082C */
0161     volatile u32 TARHWCompare;  /* 0x0830 */
0162     volatile u32 TAStart;   /* 0x0834 */
0163     volatile u32 TAObjReStart;  /* 0x0838 */
0164     volatile u32 TAPtrReStart;  /* 0x083C */
0165     volatile u32 TAStatus1; /* 0x0840 */
0166     volatile u32 TAStatus2; /* 0x0844 */
0167     volatile u32 TAIntStatus;   /* 0x0848 */
0168     volatile u32 TAIntMask; /* 0x084C */
0169
0170     volatile u32 Fill5[235];    /* GAP 0x0850 - 0x0BF8 */
0171
0172     volatile u32 TextureAddrThresh; /* 0x0BFC */
0173     volatile u32 Core1Translation;  /* 0x0C00 */
0174     volatile u32 TextureAddrReMap;  /* 0x0C04 */
0175     volatile u32 RenderOutAGPRemap; /* 0x0C08 */
0176     volatile u32 _3DRegionReadTrans;    /* 0x0C0C */
0177     volatile u32 _3DPtrReadTrans;   /* 0x0C10 */
0178     volatile u32 _3DParamReadTrans; /* 0x0C14 */
0179     volatile u32 _3DRegionReadThresh;   /* 0x0C18 */
0180     volatile u32 _3DPtrReadThresh;  /* 0x0C1C */
0181     volatile u32 _3DParamReadThresh;    /* 0x0C20 */
0182     volatile u32 _3DRegionReadAGPRemap; /* 0x0C24 */
0183     volatile u32 _3DPtrReadAGPRemap;    /* 0x0C28 */
0184     volatile u32 _3DParamReadAGPRemap;  /* 0x0C2C */
0185     volatile u32 ZBufferAGPRemap;   /* 0x0C30 */
0186     volatile u32 TAIndexAGPRemap;   /* 0x0C34 */
0187     volatile u32 TAVertexAGPRemap;  /* 0x0C38 */
0188     volatile u32 TAUVAddrTrans; /* 0x0C3C */
0189     volatile u32 TATailPtrCacheTrans;   /* 0x0C40 */
0190     volatile u32 TAParamWriteTrans; /* 0x0C44 */
0191     volatile u32 TAPtrWriteTrans;   /* 0x0C48 */
0192     volatile u32 TAParamWriteThresh;    /* 0x0C4C */
0193     volatile u32 TAPtrWriteThresh;  /* 0x0C50 */
0194     volatile u32 TATailPtrCacheAGPRe;   /* 0x0C54 */
0195     volatile u32 TAParamWriteAGPRe; /* 0x0C58 */
0196     volatile u32 TAPtrWriteAGPRe;   /* 0x0C5C */
0197     volatile u32 SDRAMArbiterConf;  /* 0x0C60 */
0198     volatile u32 SDRAMConf0;    /* 0x0C64 */
0199     volatile u32 SDRAMConf1;    /* 0x0C68 */
0200     volatile u32 SDRAMConf2;    /* 0x0C6C */
0201     volatile u32 SDRAMRefresh;  /* 0x0C70 */
0202     volatile u32 SDRAMPowerStat;    /* 0x0C74 */
0203
0204     volatile u32 Fill6[2];  /* GAP 0x0C78 - 0x0C7C */
0205
0206     volatile u32 RAMBistData;   /* 0x0C80 */
0207     volatile u32 RAMBistCtrl;   /* 0x0C84 */
0208     volatile u32 FIFOBistKey;   /* 0x0C88 */
0209     volatile u32 RAMBistResult; /* 0x0C8C */
0210     volatile u32 FIFOBistResult;    /* 0x0C90 */
0211
0212     /*
0213        volatile u32 Fill11[0x0CBC/4 - 0x0C94/4]; //GAP 0x0C94 - 0x0CBC
0214        volatile u32 Fill12[0x0CD0/4 - 0x0CC0/4]; //GAP 0x0CC0 - 0x0CD0 3DRegisters
0215      */
0216
0217     volatile u32 Fill7[16]; /* 0x0c94 - 0x0cd0 */
0218
0219     volatile u32 SDRAMAddrSign; /* 0x0CD4 */
0220     volatile u32 SDRAMDataSign; /* 0x0CD8 */
0221     volatile u32 SDRAMSignConf; /* 0x0CDC */
0222
0223     /* DWFILL; //GAP 0x0CE0 */
0224     volatile u32 dwFill_2;
0225
0226     volatile u32 ISPSignature;  /* 0x0CE4 */
0227
0228     volatile u32 Fill8[454];    /*GAP 0x0CE8 - 0x13FC */
0229
0230     volatile u32 DACPrimAddress;    /* 0x1400 */
0231     volatile u32 DACPrimSize;   /* 0x1404 */
0232     volatile u32 DACCursorAddr; /* 0x1408 */
0233     volatile u32 DACCursorCtrl; /* 0x140C */
0234     volatile u32 DACOverlayAddr;    /* 0x1410 */
0235     volatile u32 DACOverlayUAddr;   /* 0x1414 */
0236     volatile u32 DACOverlayVAddr;   /* 0x1418 */
0237     volatile u32 DACOverlaySize;    /* 0x141C */
0238     volatile u32 DACOverlayVtDec;   /* 0x1420 */
0239
0240     volatile u32 Fill9[9];  /* GAP 0x1424 - 0x1444 */
0241
0242     volatile u32 DACVerticalScal;   /* 0x1448 */
0243     volatile u32 DACPixelFormat;    /* 0x144C */
0244     volatile u32 DACHorizontalScal; /* 0x1450 */
0245     volatile u32 DACVidWinStart;    /* 0x1454 */
0246     volatile u32 DACVidWinEnd;  /* 0x1458 */
0247     volatile u32 DACBlendCtrl;  /* 0x145C */
0248     volatile u32 DACHorTim1;    /* 0x1460 */
0249     volatile u32 DACHorTim2;    /* 0x1464 */
0250     volatile u32 DACHorTim3;    /* 0x1468 */
0251     volatile u32 DACVerTim1;    /* 0x146C */
0252     volatile u32 DACVerTim2;    /* 0x1470 */
0253     volatile u32 DACVerTim3;    /* 0x1474 */
0254     volatile u32 DACBorderColor;    /* 0x1478 */
0255     volatile u32 DACSyncCtrl;   /* 0x147C */
0256     volatile u32 DACStreamCtrl; /* 0x1480 */
0257     volatile u32 DACLUTAddress; /* 0x1484 */
0258     volatile u32 DACLUTData;    /* 0x1488 */
0259     volatile u32 DACBurstCtrl;  /* 0x148C */
0260     volatile u32 DACCrcTrigger; /* 0x1490 */
0261     volatile u32 DACCrcDone;    /* 0x1494 */
0262     volatile u32 DACCrcResult1; /* 0x1498 */
0263     volatile u32 DACCrcResult2; /* 0x149C */
0264     volatile u32 DACLinecount;  /* 0x14A0 */
0265
0266     volatile u32 Fill10[151];   /*GAP 0x14A4 - 0x16FC */
0267
0268     volatile u32 DigVidPortCtrl;    /* 0x1700 */
0269     volatile u32 DigVidPortStat;    /* 0x1704 */
0270
0271     /*
0272        volatile u32 Fill11[0x1FFC/4 - 0x1708/4]; //GAP 0x1708 - 0x1FFC
0273        volatile u32 Fill17[0x3000/4 - 0x2FFC/4]; //GAP 0x2000 - 0x2FFC ALUT
0274      */
0275
0276     volatile u32 Fill11[1598];
0277
0278     /* DWFILL; //GAP 0x3000          ALUT 256MB offset */
0279     volatile u32 Fill_3;
0280
0281 } STG4000REG;
0282
0283 #endif /* _STG4000REG_H */