fbdev/kyro/STG4000Ramdac.c

0001 /*
0002  *  linux/drivers/video/kyro/STG4000Ramdac.c
0003  *
0004  *  Copyright (C) 2002 STMicroelectronics
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file COPYING in the main directory of this archive
0008  * for more details.
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/errno.h>
0013 #include <linux/types.h>
0014 #include <video/kyro.h>
0015
0016 #include "STG4000Reg.h"
0017 #include "STG4000Interface.h"
0018
0019 static u32 STG_PIXEL_BUS_WIDTH = 128;   /* 128 bit bus width      */
0020 static u32 REF_CLOCK = 14318;
0021
0022 int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
0023              u32 displayDepth,
0024              u32 displayWidth,
0025              u32 displayHeight,
0026              s32 HSyncPolarity,
0027              s32 VSyncPolarity, u32 * pixelClock)
0028 {
0029     u32 tmp = 0;
0030     u32 F = 0, R = 0, P = 0;
0031     u32 stride = 0;
0032     u32 ulPdiv = 0;
0033     u32 physicalPixelDepth = 0;
0034     /* Make sure DAC is in Reset */
0035     tmp = STG_READ_REG(SoftwareReset);
0036
0037     if (tmp & 0x1) {
0038         CLEAR_BIT(1);
0039         STG_WRITE_REG(SoftwareReset, tmp);
0040     }
0041
0042     /* Set Pixel Format */
0043     tmp = STG_READ_REG(DACPixelFormat);
0044     CLEAR_BITS_FRM_TO(0, 2);
0045
0046     /* Set LUT not used from 16bpp to 32 bpp ??? */
0047     CLEAR_BITS_FRM_TO(8, 9);
0048
0049     switch (displayDepth) {
0050     case 16:
0051         {
0052             physicalPixelDepth = 16;
0053             tmp |= _16BPP;
0054             break;
0055         }
0056     case 32:
0057         {
0058             /* Set for 32 bits per pixel */
0059             physicalPixelDepth = 32;
0060             tmp |= _32BPP;
0061             break;
0062         }
0063     default:
0064         return -EINVAL;
0065     }
0066
0067     STG_WRITE_REG(DACPixelFormat, tmp);
0068
0069     /* Workout Bus transfer bandwidth according to pixel format */
0070     ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;
0071
0072     /* Get Screen Stride in pixels */
0073     stride = displayWidth;
0074
0075     /* Set Primary size info */
0076     tmp = STG_READ_REG(DACPrimSize);
0077     CLEAR_BITS_FRM_TO(0, 10);
0078     CLEAR_BITS_FRM_TO(12, 31);
0079     tmp |=
0080         ((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
0081                           1) << 23))
0082          | (stride / ulPdiv));
0083     STG_WRITE_REG(DACPrimSize, tmp);
0084
0085
0086     /* Set Pixel Clock */
0087     *pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);
0088
0089     /* Set DAC PLL Mode */
0090     tmp = STG_READ_REG(DACPLLMode);
0091     CLEAR_BITS_FRM_TO(0, 15);
0092     /* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */
0093     tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
0094     STG_WRITE_REG(DACPLLMode, tmp);
0095
0096     /* Set Prim Address */
0097     tmp = STG_READ_REG(DACPrimAddress);
0098     CLEAR_BITS_FRM_TO(0, 20);
0099     CLEAR_BITS_FRM_TO(20, 31);
0100     STG_WRITE_REG(DACPrimAddress, tmp);
0101
0102     /* Set Cursor details with HW Cursor disabled */
0103     tmp = STG_READ_REG(DACCursorCtrl);
0104     tmp &= ~SET_BIT(31);
0105     STG_WRITE_REG(DACCursorCtrl, tmp);
0106
0107     tmp = STG_READ_REG(DACCursorAddr);
0108     CLEAR_BITS_FRM_TO(0, 20);
0109     STG_WRITE_REG(DACCursorAddr, tmp);
0110
0111     /* Set Video Window */
0112     tmp = STG_READ_REG(DACVidWinStart);
0113     CLEAR_BITS_FRM_TO(0, 10);
0114     CLEAR_BITS_FRM_TO(16, 26);
0115     STG_WRITE_REG(DACVidWinStart, tmp);
0116
0117     tmp = STG_READ_REG(DACVidWinEnd);
0118     CLEAR_BITS_FRM_TO(0, 10);
0119     CLEAR_BITS_FRM_TO(16, 26);
0120     STG_WRITE_REG(DACVidWinEnd, tmp);
0121
0122     /* Set DAC Border Color to default */
0123     tmp = STG_READ_REG(DACBorderColor);
0124     CLEAR_BITS_FRM_TO(0, 23);
0125     STG_WRITE_REG(DACBorderColor, tmp);
0126
0127     /* Set Graphics and Overlay Burst Control */
0128     STG_WRITE_REG(DACBurstCtrl, 0x0404);
0129
0130     /* Set CRC Trigger to default */
0131     tmp = STG_READ_REG(DACCrcTrigger);
0132     CLEAR_BIT(0);
0133     STG_WRITE_REG(DACCrcTrigger, tmp);
0134
0135     /* Set Video Port Control to default */
0136     tmp = STG_READ_REG(DigVidPortCtrl);
0137     CLEAR_BIT(8);
0138     CLEAR_BITS_FRM_TO(16, 27);
0139     CLEAR_BITS_FRM_TO(1, 3);
0140     CLEAR_BITS_FRM_TO(10, 11);
0141     STG_WRITE_REG(DigVidPortCtrl, tmp);
0142
0143     return 0;
0144 }
0145
0146 /* Ramdac control, turning output to the screen on and off */
0147 void DisableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
0148 {
0149     u32 tmp;
0150
0151     /* Disable DAC for Graphics Stream Control */
0152     tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
0153     STG_WRITE_REG(DACStreamCtrl, tmp);
0154 }
0155
0156 void EnableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
0157 {
0158     u32 tmp;
0159
0160     /* Enable DAC for Graphics Stream Control */
0161     tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
0162     STG_WRITE_REG(DACStreamCtrl, tmp);
0163 }