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0001 /*
0002  * intelfb
0003  *
0004  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
0005  *
0006  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
0007  *                   2004 Sylvain Meyer
0008  *
0009  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
0010  * the basic fbdev interfaces, is derived in part from the radeonfb and
0011  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
0012  * provides the code to program the hardware.  Most of it is derived from
0013  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
0014  * under a dual license (GPL and MIT/XFree86 license).
0015  *
0016  * Author: David Dawes
0017  *
0018  */
0019 
0020 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
0021 
0022 #include <linux/module.h>
0023 #include <linux/kernel.h>
0024 #include <linux/errno.h>
0025 #include <linux/string.h>
0026 #include <linux/mm.h>
0027 #include <linux/delay.h>
0028 #include <linux/fb.h>
0029 #include <linux/ioport.h>
0030 #include <linux/init.h>
0031 #include <linux/pci.h>
0032 #include <linux/vmalloc.h>
0033 #include <linux/pagemap.h>
0034 #include <linux/interrupt.h>
0035 
0036 #include <asm/io.h>
0037 
0038 #include "intelfb.h"
0039 #include "intelfbhw.h"
0040 
0041 struct pll_min_max {
0042     int min_m, max_m, min_m1, max_m1;
0043     int min_m2, max_m2, min_n, max_n;
0044     int min_p, max_p, min_p1, max_p1;
0045     int min_vco, max_vco, p_transition_clk, ref_clk;
0046     int p_inc_lo, p_inc_hi;
0047 };
0048 
0049 #define PLLS_I8xx 0
0050 #define PLLS_I9xx 1
0051 #define PLLS_MAX 2
0052 
0053 static struct pll_min_max plls[PLLS_MAX] = {
0054     { 108, 140, 18, 26,
0055       6, 16, 3, 16,
0056       4, 128, 0, 31,
0057       930000, 1400000, 165000, 48000,
0058       4, 2 },       /* I8xx */
0059 
0060     { 75, 120, 10, 20,
0061       5, 9, 4, 7,
0062       5, 80, 1, 8,
0063       1400000, 2800000, 200000, 96000,
0064       10, 5 }       /* I9xx */
0065 };
0066 
0067 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
0068 {
0069     u32 tmp;
0070     if (!pdev || !dinfo)
0071         return 1;
0072 
0073     switch (pdev->device) {
0074     case PCI_DEVICE_ID_INTEL_830M:
0075         dinfo->name = "Intel(R) 830M";
0076         dinfo->chipset = INTEL_830M;
0077         dinfo->mobile = 1;
0078         dinfo->pll_index = PLLS_I8xx;
0079         return 0;
0080     case PCI_DEVICE_ID_INTEL_845G:
0081         dinfo->name = "Intel(R) 845G";
0082         dinfo->chipset = INTEL_845G;
0083         dinfo->mobile = 0;
0084         dinfo->pll_index = PLLS_I8xx;
0085         return 0;
0086     case PCI_DEVICE_ID_INTEL_854:
0087         dinfo->mobile = 1;
0088         dinfo->name = "Intel(R) 854";
0089         dinfo->chipset = INTEL_854;
0090         return 0;
0091     case PCI_DEVICE_ID_INTEL_85XGM:
0092         tmp = 0;
0093         dinfo->mobile = 1;
0094         dinfo->pll_index = PLLS_I8xx;
0095         pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
0096         switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
0097             INTEL_85X_VARIANT_MASK) {
0098         case INTEL_VAR_855GME:
0099             dinfo->name = "Intel(R) 855GME";
0100             dinfo->chipset = INTEL_855GME;
0101             return 0;
0102         case INTEL_VAR_855GM:
0103             dinfo->name = "Intel(R) 855GM";
0104             dinfo->chipset = INTEL_855GM;
0105             return 0;
0106         case INTEL_VAR_852GME:
0107             dinfo->name = "Intel(R) 852GME";
0108             dinfo->chipset = INTEL_852GME;
0109             return 0;
0110         case INTEL_VAR_852GM:
0111             dinfo->name = "Intel(R) 852GM";
0112             dinfo->chipset = INTEL_852GM;
0113             return 0;
0114         default:
0115             dinfo->name = "Intel(R) 852GM/855GM";
0116             dinfo->chipset = INTEL_85XGM;
0117             return 0;
0118         }
0119         break;
0120     case PCI_DEVICE_ID_INTEL_865G:
0121         dinfo->name = "Intel(R) 865G";
0122         dinfo->chipset = INTEL_865G;
0123         dinfo->mobile = 0;
0124         dinfo->pll_index = PLLS_I8xx;
0125         return 0;
0126     case PCI_DEVICE_ID_INTEL_915G:
0127         dinfo->name = "Intel(R) 915G";
0128         dinfo->chipset = INTEL_915G;
0129         dinfo->mobile = 0;
0130         dinfo->pll_index = PLLS_I9xx;
0131         return 0;
0132     case PCI_DEVICE_ID_INTEL_915GM:
0133         dinfo->name = "Intel(R) 915GM";
0134         dinfo->chipset = INTEL_915GM;
0135         dinfo->mobile = 1;
0136         dinfo->pll_index = PLLS_I9xx;
0137         return 0;
0138     case PCI_DEVICE_ID_INTEL_945G:
0139         dinfo->name = "Intel(R) 945G";
0140         dinfo->chipset = INTEL_945G;
0141         dinfo->mobile = 0;
0142         dinfo->pll_index = PLLS_I9xx;
0143         return 0;
0144     case PCI_DEVICE_ID_INTEL_945GM:
0145         dinfo->name = "Intel(R) 945GM";
0146         dinfo->chipset = INTEL_945GM;
0147         dinfo->mobile = 1;
0148         dinfo->pll_index = PLLS_I9xx;
0149         return 0;
0150     case PCI_DEVICE_ID_INTEL_945GME:
0151         dinfo->name = "Intel(R) 945GME";
0152         dinfo->chipset = INTEL_945GME;
0153         dinfo->mobile = 1;
0154         dinfo->pll_index = PLLS_I9xx;
0155         return 0;
0156     case PCI_DEVICE_ID_INTEL_965G:
0157         dinfo->name = "Intel(R) 965G";
0158         dinfo->chipset = INTEL_965G;
0159         dinfo->mobile = 0;
0160         dinfo->pll_index = PLLS_I9xx;
0161         return 0;
0162     case PCI_DEVICE_ID_INTEL_965GM:
0163         dinfo->name = "Intel(R) 965GM";
0164         dinfo->chipset = INTEL_965GM;
0165         dinfo->mobile = 1;
0166         dinfo->pll_index = PLLS_I9xx;
0167         return 0;
0168     default:
0169         return 1;
0170     }
0171 }
0172 
0173 int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
0174              int *stolen_size)
0175 {
0176     struct pci_dev *bridge_dev;
0177     u16 tmp;
0178     int stolen_overhead;
0179 
0180     if (!pdev || !aperture_size || !stolen_size)
0181         return 1;
0182 
0183     /* Find the bridge device.  It is always 0:0.0 */
0184     bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0,
0185                          PCI_DEVFN(0, 0));
0186     if (!bridge_dev) {
0187         ERR_MSG("cannot find bridge device\n");
0188         return 1;
0189     }
0190 
0191     /* Get the fb aperture size and "stolen" memory amount. */
0192     tmp = 0;
0193     pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
0194     pci_dev_put(bridge_dev);
0195 
0196     switch (pdev->device) {
0197     case PCI_DEVICE_ID_INTEL_915G:
0198     case PCI_DEVICE_ID_INTEL_915GM:
0199     case PCI_DEVICE_ID_INTEL_945G:
0200     case PCI_DEVICE_ID_INTEL_945GM:
0201     case PCI_DEVICE_ID_INTEL_945GME:
0202     case PCI_DEVICE_ID_INTEL_965G:
0203     case PCI_DEVICE_ID_INTEL_965GM:
0204         /*
0205          * 915, 945 and 965 chipsets support 64MB, 128MB or 256MB
0206          * aperture. Determine size from PCI resource length.
0207          */
0208         *aperture_size = pci_resource_len(pdev, 2);
0209         break;
0210     default:
0211         if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
0212             *aperture_size = MB(64);
0213         else
0214             *aperture_size = MB(128);
0215         break;
0216     }
0217 
0218     /* Stolen memory size is reduced by the GTT and the popup.
0219        GTT is 1K per MB of aperture size, and popup is 4K. */
0220     stolen_overhead = (*aperture_size / MB(1)) + 4;
0221     switch(pdev->device) {
0222     case PCI_DEVICE_ID_INTEL_830M:
0223     case PCI_DEVICE_ID_INTEL_845G:
0224         switch (tmp & INTEL_830_GMCH_GMS_MASK) {
0225         case INTEL_830_GMCH_GMS_STOLEN_512:
0226             *stolen_size = KB(512) - KB(stolen_overhead);
0227             return 0;
0228         case INTEL_830_GMCH_GMS_STOLEN_1024:
0229             *stolen_size = MB(1) - KB(stolen_overhead);
0230             return 0;
0231         case INTEL_830_GMCH_GMS_STOLEN_8192:
0232             *stolen_size = MB(8) - KB(stolen_overhead);
0233             return 0;
0234         case INTEL_830_GMCH_GMS_LOCAL:
0235             ERR_MSG("only local memory found\n");
0236             return 1;
0237         case INTEL_830_GMCH_GMS_DISABLED:
0238             ERR_MSG("video memory is disabled\n");
0239             return 1;
0240         default:
0241             ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
0242                 tmp & INTEL_830_GMCH_GMS_MASK);
0243             return 1;
0244         }
0245         break;
0246     default:
0247         switch (tmp & INTEL_855_GMCH_GMS_MASK) {
0248         case INTEL_855_GMCH_GMS_STOLEN_1M:
0249             *stolen_size = MB(1) - KB(stolen_overhead);
0250             return 0;
0251         case INTEL_855_GMCH_GMS_STOLEN_4M:
0252             *stolen_size = MB(4) - KB(stolen_overhead);
0253             return 0;
0254         case INTEL_855_GMCH_GMS_STOLEN_8M:
0255             *stolen_size = MB(8) - KB(stolen_overhead);
0256             return 0;
0257         case INTEL_855_GMCH_GMS_STOLEN_16M:
0258             *stolen_size = MB(16) - KB(stolen_overhead);
0259             return 0;
0260         case INTEL_855_GMCH_GMS_STOLEN_32M:
0261             *stolen_size = MB(32) - KB(stolen_overhead);
0262             return 0;
0263         case INTEL_915G_GMCH_GMS_STOLEN_48M:
0264             *stolen_size = MB(48) - KB(stolen_overhead);
0265             return 0;
0266         case INTEL_915G_GMCH_GMS_STOLEN_64M:
0267             *stolen_size = MB(64) - KB(stolen_overhead);
0268             return 0;
0269         case INTEL_855_GMCH_GMS_DISABLED:
0270             ERR_MSG("video memory is disabled\n");
0271             return 0;
0272         default:
0273             ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
0274                 tmp & INTEL_855_GMCH_GMS_MASK);
0275             return 1;
0276         }
0277     }
0278 }
0279 
0280 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
0281 {
0282     int dvo = 0;
0283 
0284     if (INREG(LVDS) & PORT_ENABLE)
0285         dvo |= LVDS_PORT;
0286     if (INREG(DVOA) & PORT_ENABLE)
0287         dvo |= DVOA_PORT;
0288     if (INREG(DVOB) & PORT_ENABLE)
0289         dvo |= DVOB_PORT;
0290     if (INREG(DVOC) & PORT_ENABLE)
0291         dvo |= DVOC_PORT;
0292 
0293     return dvo;
0294 }
0295 
0296 const char * intelfbhw_dvo_to_string(int dvo)
0297 {
0298     if (dvo & DVOA_PORT)
0299         return "DVO port A";
0300     else if (dvo & DVOB_PORT)
0301         return "DVO port B";
0302     else if (dvo & DVOC_PORT)
0303         return "DVO port C";
0304     else if (dvo & LVDS_PORT)
0305         return "LVDS port";
0306     else
0307         return NULL;
0308 }
0309 
0310 
0311 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
0312                 struct fb_var_screeninfo *var)
0313 {
0314     int bytes_per_pixel;
0315     int tmp;
0316 
0317 #if VERBOSE > 0
0318     DBG_MSG("intelfbhw_validate_mode\n");
0319 #endif
0320 
0321     bytes_per_pixel = var->bits_per_pixel / 8;
0322     if (bytes_per_pixel == 3)
0323         bytes_per_pixel = 4;
0324 
0325     /* Check if enough video memory. */
0326     tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
0327     if (tmp > dinfo->fb.size) {
0328         WRN_MSG("Not enough video ram for mode "
0329             "(%d KByte vs %d KByte).\n",
0330             BtoKB(tmp), BtoKB(dinfo->fb.size));
0331         return 1;
0332     }
0333 
0334     /* Check if x/y limits are OK. */
0335     if (var->xres - 1 > HACTIVE_MASK) {
0336         WRN_MSG("X resolution too large (%d vs %d).\n",
0337             var->xres, HACTIVE_MASK + 1);
0338         return 1;
0339     }
0340     if (var->yres - 1 > VACTIVE_MASK) {
0341         WRN_MSG("Y resolution too large (%d vs %d).\n",
0342             var->yres, VACTIVE_MASK + 1);
0343         return 1;
0344     }
0345     if (var->xres < 4) {
0346         WRN_MSG("X resolution too small (%d vs 4).\n", var->xres);
0347         return 1;
0348     }
0349     if (var->yres < 4) {
0350         WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres);
0351         return 1;
0352     }
0353 
0354     /* Check for doublescan modes. */
0355     if (var->vmode & FB_VMODE_DOUBLE) {
0356         WRN_MSG("Mode is double-scan.\n");
0357         return 1;
0358     }
0359 
0360     if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) {
0361         WRN_MSG("Odd number of lines in interlaced mode\n");
0362         return 1;
0363     }
0364 
0365     /* Check if clock is OK. */
0366     tmp = 1000000000 / var->pixclock;
0367     if (tmp < MIN_CLOCK) {
0368         WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
0369             (tmp + 500) / 1000, MIN_CLOCK / 1000);
0370         return 1;
0371     }
0372     if (tmp > MAX_CLOCK) {
0373         WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
0374             (tmp + 500) / 1000, MAX_CLOCK / 1000);
0375         return 1;
0376     }
0377 
0378     return 0;
0379 }
0380 
0381 int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
0382 {
0383     struct intelfb_info *dinfo = GET_DINFO(info);
0384     u32 offset, xoffset, yoffset;
0385 
0386 #if VERBOSE > 0
0387     DBG_MSG("intelfbhw_pan_display\n");
0388 #endif
0389 
0390     xoffset = ROUND_DOWN_TO(var->xoffset, 8);
0391     yoffset = var->yoffset;
0392 
0393     if ((xoffset + info->var.xres > info->var.xres_virtual) ||
0394         (yoffset + info->var.yres > info->var.yres_virtual))
0395         return -EINVAL;
0396 
0397     offset = (yoffset * dinfo->pitch) +
0398          (xoffset * info->var.bits_per_pixel) / 8;
0399 
0400     offset += dinfo->fb.offset << 12;
0401 
0402     dinfo->vsync.pan_offset = offset;
0403     if ((var->activate & FB_ACTIVATE_VBL) &&
0404         !intelfbhw_enable_irq(dinfo))
0405         dinfo->vsync.pan_display = 1;
0406     else {
0407         dinfo->vsync.pan_display = 0;
0408         OUTREG(DSPABASE, offset);
0409     }
0410 
0411     return 0;
0412 }
0413 
0414 /* Blank the screen. */
0415 void intelfbhw_do_blank(int blank, struct fb_info *info)
0416 {
0417     struct intelfb_info *dinfo = GET_DINFO(info);
0418     u32 tmp;
0419 
0420 #if VERBOSE > 0
0421     DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
0422 #endif
0423 
0424     /* Turn plane A on or off */
0425     tmp = INREG(DSPACNTR);
0426     if (blank)
0427         tmp &= ~DISPPLANE_PLANE_ENABLE;
0428     else
0429         tmp |= DISPPLANE_PLANE_ENABLE;
0430     OUTREG(DSPACNTR, tmp);
0431     /* Flush */
0432     tmp = INREG(DSPABASE);
0433     OUTREG(DSPABASE, tmp);
0434 
0435     /* Turn off/on the HW cursor */
0436 #if VERBOSE > 0
0437     DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
0438 #endif
0439     if (dinfo->cursor_on) {
0440         if (blank)
0441             intelfbhw_cursor_hide(dinfo);
0442         else
0443             intelfbhw_cursor_show(dinfo);
0444         dinfo->cursor_on = 1;
0445     }
0446     dinfo->cursor_blanked = blank;
0447 
0448     /* Set DPMS level */
0449     tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
0450     switch (blank) {
0451     case FB_BLANK_UNBLANK:
0452     case FB_BLANK_NORMAL:
0453         tmp |= ADPA_DPMS_D0;
0454         break;
0455     case FB_BLANK_VSYNC_SUSPEND:
0456         tmp |= ADPA_DPMS_D1;
0457         break;
0458     case FB_BLANK_HSYNC_SUSPEND:
0459         tmp |= ADPA_DPMS_D2;
0460         break;
0461     case FB_BLANK_POWERDOWN:
0462         tmp |= ADPA_DPMS_D3;
0463         break;
0464     }
0465     OUTREG(ADPA, tmp);
0466 
0467     return;
0468 }
0469 
0470 
0471 /* Check which pipe is connected to an active display plane. */
0472 int intelfbhw_active_pipe(const struct intelfb_hwstate *hw)
0473 {
0474     int pipe = -1;
0475 
0476     /* keep old default behaviour - prefer PIPE_A */
0477     if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) {
0478         pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
0479         pipe &= PIPE_MASK;
0480         if (unlikely(pipe == PIPE_A))
0481             return PIPE_A;
0482     }
0483     if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) {
0484         pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT);
0485         pipe &= PIPE_MASK;
0486         if (likely(pipe == PIPE_A))
0487             return PIPE_A;
0488     }
0489     /* Impossible that no pipe is selected - return PIPE_A */
0490     WARN_ON(pipe == -1);
0491     if (unlikely(pipe == -1))
0492         pipe = PIPE_A;
0493 
0494     return pipe;
0495 }
0496 
0497 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
0498              unsigned red, unsigned green, unsigned blue,
0499              unsigned transp)
0500 {
0501     u32 palette_reg = (dinfo->pipe == PIPE_A) ?
0502               PALETTE_A : PALETTE_B;
0503 
0504 #if VERBOSE > 0
0505     DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
0506         regno, red, green, blue);
0507 #endif
0508 
0509     OUTREG(palette_reg + (regno << 2),
0510            (red << PALETTE_8_RED_SHIFT) |
0511            (green << PALETTE_8_GREEN_SHIFT) |
0512            (blue << PALETTE_8_BLUE_SHIFT));
0513 }
0514 
0515 
0516 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
0517                 struct intelfb_hwstate *hw, int flag)
0518 {
0519     int i;
0520 
0521 #if VERBOSE > 0
0522     DBG_MSG("intelfbhw_read_hw_state\n");
0523 #endif
0524 
0525     if (!hw || !dinfo)
0526         return -1;
0527 
0528     /* Read in as much of the HW state as possible. */
0529     hw->vga0_divisor = INREG(VGA0_DIVISOR);
0530     hw->vga1_divisor = INREG(VGA1_DIVISOR);
0531     hw->vga_pd = INREG(VGAPD);
0532     hw->dpll_a = INREG(DPLL_A);
0533     hw->dpll_b = INREG(DPLL_B);
0534     hw->fpa0 = INREG(FPA0);
0535     hw->fpa1 = INREG(FPA1);
0536     hw->fpb0 = INREG(FPB0);
0537     hw->fpb1 = INREG(FPB1);
0538 
0539     if (flag == 1)
0540         return flag;
0541 
0542 #if 0
0543     /* This seems to be a problem with the 852GM/855GM */
0544     for (i = 0; i < PALETTE_8_ENTRIES; i++) {
0545         hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
0546         hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
0547     }
0548 #endif
0549 
0550     if (flag == 2)
0551         return flag;
0552 
0553     hw->htotal_a = INREG(HTOTAL_A);
0554     hw->hblank_a = INREG(HBLANK_A);
0555     hw->hsync_a = INREG(HSYNC_A);
0556     hw->vtotal_a = INREG(VTOTAL_A);
0557     hw->vblank_a = INREG(VBLANK_A);
0558     hw->vsync_a = INREG(VSYNC_A);
0559     hw->src_size_a = INREG(SRC_SIZE_A);
0560     hw->bclrpat_a = INREG(BCLRPAT_A);
0561     hw->htotal_b = INREG(HTOTAL_B);
0562     hw->hblank_b = INREG(HBLANK_B);
0563     hw->hsync_b = INREG(HSYNC_B);
0564     hw->vtotal_b = INREG(VTOTAL_B);
0565     hw->vblank_b = INREG(VBLANK_B);
0566     hw->vsync_b = INREG(VSYNC_B);
0567     hw->src_size_b = INREG(SRC_SIZE_B);
0568     hw->bclrpat_b = INREG(BCLRPAT_B);
0569 
0570     if (flag == 3)
0571         return flag;
0572 
0573     hw->adpa = INREG(ADPA);
0574     hw->dvoa = INREG(DVOA);
0575     hw->dvob = INREG(DVOB);
0576     hw->dvoc = INREG(DVOC);
0577     hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
0578     hw->dvob_srcdim = INREG(DVOB_SRCDIM);
0579     hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
0580     hw->lvds = INREG(LVDS);
0581 
0582     if (flag == 4)
0583         return flag;
0584 
0585     hw->pipe_a_conf = INREG(PIPEACONF);
0586     hw->pipe_b_conf = INREG(PIPEBCONF);
0587     hw->disp_arb = INREG(DISPARB);
0588 
0589     if (flag == 5)
0590         return flag;
0591 
0592     hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
0593     hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
0594     hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
0595     hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
0596 
0597     if (flag == 6)
0598         return flag;
0599 
0600     for (i = 0; i < 4; i++) {
0601         hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
0602         hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
0603     }
0604 
0605     if (flag == 7)
0606         return flag;
0607 
0608     hw->cursor_size = INREG(CURSOR_SIZE);
0609 
0610     if (flag == 8)
0611         return flag;
0612 
0613     hw->disp_a_ctrl = INREG(DSPACNTR);
0614     hw->disp_b_ctrl = INREG(DSPBCNTR);
0615     hw->disp_a_base = INREG(DSPABASE);
0616     hw->disp_b_base = INREG(DSPBBASE);
0617     hw->disp_a_stride = INREG(DSPASTRIDE);
0618     hw->disp_b_stride = INREG(DSPBSTRIDE);
0619 
0620     if (flag == 9)
0621         return flag;
0622 
0623     hw->vgacntrl = INREG(VGACNTRL);
0624 
0625     if (flag == 10)
0626         return flag;
0627 
0628     hw->add_id = INREG(ADD_ID);
0629 
0630     if (flag == 11)
0631         return flag;
0632 
0633     for (i = 0; i < 7; i++) {
0634         hw->swf0x[i] = INREG(SWF00 + (i << 2));
0635         hw->swf1x[i] = INREG(SWF10 + (i << 2));
0636         if (i < 3)
0637             hw->swf3x[i] = INREG(SWF30 + (i << 2));
0638     }
0639 
0640     for (i = 0; i < 8; i++)
0641         hw->fence[i] = INREG(FENCE + (i << 2));
0642 
0643     hw->instpm = INREG(INSTPM);
0644     hw->mem_mode = INREG(MEM_MODE);
0645     hw->fw_blc_0 = INREG(FW_BLC_0);
0646     hw->fw_blc_1 = INREG(FW_BLC_1);
0647 
0648     hw->hwstam = INREG16(HWSTAM);
0649     hw->ier = INREG16(IER);
0650     hw->iir = INREG16(IIR);
0651     hw->imr = INREG16(IMR);
0652 
0653     return 0;
0654 }
0655 
0656 
0657 static int calc_vclock3(int index, int m, int n, int p)
0658 {
0659     if (p == 0 || n == 0)
0660         return 0;
0661     return plls[index].ref_clk * m / n / p;
0662 }
0663 
0664 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
0665                int lvds)
0666 {
0667     struct pll_min_max *pll = &plls[index];
0668     u32 m, vco, p;
0669 
0670     m = (5 * (m1 + 2)) + (m2 + 2);
0671     n += 2;
0672     vco = pll->ref_clk * m / n;
0673 
0674     if (index == PLLS_I8xx)
0675         p = ((p1 + 2) * (1 << (p2 + 1)));
0676     else
0677         p = ((p1) * (p2 ? 5 : 10));
0678     return vco / p;
0679 }
0680 
0681 #if REGDUMP
0682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
0683                    int *o_p1, int *o_p2)
0684 {
0685     int p1, p2;
0686 
0687     if (IS_I9XX(dinfo)) {
0688         if (dpll & DPLL_P1_FORCE_DIV2)
0689             p1 = 1;
0690         else
0691             p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
0692 
0693         p1 = ffs(p1);
0694 
0695         p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
0696     } else {
0697         if (dpll & DPLL_P1_FORCE_DIV2)
0698             p1 = 0;
0699         else
0700             p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
0701         p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
0702     }
0703 
0704     *o_p1 = p1;
0705     *o_p2 = p2;
0706 }
0707 #endif
0708 
0709 
0710 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
0711                   struct intelfb_hwstate *hw)
0712 {
0713 #if REGDUMP
0714     int i, m1, m2, n, p1, p2;
0715     int index = dinfo->pll_index;
0716     DBG_MSG("intelfbhw_print_hw_state\n");
0717 
0718     if (!hw)
0719         return;
0720     /* Read in as much of the HW state as possible. */
0721     printk("hw state dump start\n");
0722     printk("    VGA0_DIVISOR:       0x%08x\n", hw->vga0_divisor);
0723     printk("    VGA1_DIVISOR:       0x%08x\n", hw->vga1_divisor);
0724     printk("    VGAPD:          0x%08x\n", hw->vga_pd);
0725     n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0726     m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0727     m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0728 
0729     intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
0730 
0731     printk("    VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
0732            m1, m2, n, p1, p2);
0733     printk("    VGA0: clock is %d\n",
0734            calc_vclock(index, m1, m2, n, p1, p2, 0));
0735 
0736     n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0737     m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0738     m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0739 
0740     intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
0741     printk("    VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
0742            m1, m2, n, p1, p2);
0743     printk("    VGA1: clock is %d\n",
0744            calc_vclock(index, m1, m2, n, p1, p2, 0));
0745 
0746     printk("    DPLL_A:         0x%08x\n", hw->dpll_a);
0747     printk("    DPLL_B:         0x%08x\n", hw->dpll_b);
0748     printk("    FPA0:           0x%08x\n", hw->fpa0);
0749     printk("    FPA1:           0x%08x\n", hw->fpa1);
0750     printk("    FPB0:           0x%08x\n", hw->fpb0);
0751     printk("    FPB1:           0x%08x\n", hw->fpb1);
0752 
0753     n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0754     m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0755     m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0756 
0757     intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
0758 
0759     printk("    PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
0760            m1, m2, n, p1, p2);
0761     printk("    PLLA0: clock is %d\n",
0762            calc_vclock(index, m1, m2, n, p1, p2, 0));
0763 
0764     n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0765     m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0766     m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
0767 
0768     intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
0769 
0770     printk("    PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
0771            m1, m2, n, p1, p2);
0772     printk("    PLLA1: clock is %d\n",
0773            calc_vclock(index, m1, m2, n, p1, p2, 0));
0774 
0775 #if 0
0776     printk("    PALETTE_A:\n");
0777     for (i = 0; i < PALETTE_8_ENTRIES)
0778         printk("    %3d:    0x%08x\n", i, hw->palette_a[i]);
0779     printk("    PALETTE_B:\n");
0780     for (i = 0; i < PALETTE_8_ENTRIES)
0781         printk("    %3d:    0x%08x\n", i, hw->palette_b[i]);
0782 #endif
0783 
0784     printk("    HTOTAL_A:       0x%08x\n", hw->htotal_a);
0785     printk("    HBLANK_A:       0x%08x\n", hw->hblank_a);
0786     printk("    HSYNC_A:        0x%08x\n", hw->hsync_a);
0787     printk("    VTOTAL_A:       0x%08x\n", hw->vtotal_a);
0788     printk("    VBLANK_A:       0x%08x\n", hw->vblank_a);
0789     printk("    VSYNC_A:        0x%08x\n", hw->vsync_a);
0790     printk("    SRC_SIZE_A:     0x%08x\n", hw->src_size_a);
0791     printk("    BCLRPAT_A:      0x%08x\n", hw->bclrpat_a);
0792     printk("    HTOTAL_B:       0x%08x\n", hw->htotal_b);
0793     printk("    HBLANK_B:       0x%08x\n", hw->hblank_b);
0794     printk("    HSYNC_B:        0x%08x\n", hw->hsync_b);
0795     printk("    VTOTAL_B:       0x%08x\n", hw->vtotal_b);
0796     printk("    VBLANK_B:       0x%08x\n", hw->vblank_b);
0797     printk("    VSYNC_B:        0x%08x\n", hw->vsync_b);
0798     printk("    SRC_SIZE_B:     0x%08x\n", hw->src_size_b);
0799     printk("    BCLRPAT_B:      0x%08x\n", hw->bclrpat_b);
0800 
0801     printk("    ADPA:           0x%08x\n", hw->adpa);
0802     printk("    DVOA:           0x%08x\n", hw->dvoa);
0803     printk("    DVOB:           0x%08x\n", hw->dvob);
0804     printk("    DVOC:           0x%08x\n", hw->dvoc);
0805     printk("    DVOA_SRCDIM:        0x%08x\n", hw->dvoa_srcdim);
0806     printk("    DVOB_SRCDIM:        0x%08x\n", hw->dvob_srcdim);
0807     printk("    DVOC_SRCDIM:        0x%08x\n", hw->dvoc_srcdim);
0808     printk("    LVDS:           0x%08x\n", hw->lvds);
0809 
0810     printk("    PIPEACONF:      0x%08x\n", hw->pipe_a_conf);
0811     printk("    PIPEBCONF:      0x%08x\n", hw->pipe_b_conf);
0812     printk("    DISPARB:        0x%08x\n", hw->disp_arb);
0813 
0814     printk("    CURSOR_A_CONTROL:   0x%08x\n", hw->cursor_a_control);
0815     printk("    CURSOR_B_CONTROL:   0x%08x\n", hw->cursor_b_control);
0816     printk("    CURSOR_A_BASEADDR:  0x%08x\n", hw->cursor_a_base);
0817     printk("    CURSOR_B_BASEADDR:  0x%08x\n", hw->cursor_b_base);
0818 
0819     printk("    CURSOR_A_PALETTE:   ");
0820     for (i = 0; i < 4; i++) {
0821         printk("0x%08x", hw->cursor_a_palette[i]);
0822         if (i < 3)
0823             printk(", ");
0824     }
0825     printk("\n");
0826     printk("    CURSOR_B_PALETTE:   ");
0827     for (i = 0; i < 4; i++) {
0828         printk("0x%08x", hw->cursor_b_palette[i]);
0829         if (i < 3)
0830             printk(", ");
0831     }
0832     printk("\n");
0833 
0834     printk("    CURSOR_SIZE:        0x%08x\n", hw->cursor_size);
0835 
0836     printk("    DSPACNTR:       0x%08x\n", hw->disp_a_ctrl);
0837     printk("    DSPBCNTR:       0x%08x\n", hw->disp_b_ctrl);
0838     printk("    DSPABASE:       0x%08x\n", hw->disp_a_base);
0839     printk("    DSPBBASE:       0x%08x\n", hw->disp_b_base);
0840     printk("    DSPASTRIDE:     0x%08x\n", hw->disp_a_stride);
0841     printk("    DSPBSTRIDE:     0x%08x\n", hw->disp_b_stride);
0842 
0843     printk("    VGACNTRL:       0x%08x\n", hw->vgacntrl);
0844     printk("    ADD_ID:         0x%08x\n", hw->add_id);
0845 
0846     for (i = 0; i < 7; i++) {
0847         printk("    SWF0%d          0x%08x\n", i,
0848             hw->swf0x[i]);
0849     }
0850     for (i = 0; i < 7; i++) {
0851         printk("    SWF1%d          0x%08x\n", i,
0852             hw->swf1x[i]);
0853     }
0854     for (i = 0; i < 3; i++) {
0855         printk("    SWF3%d          0x%08x\n", i,
0856                hw->swf3x[i]);
0857     }
0858     for (i = 0; i < 8; i++)
0859         printk("    FENCE%d         0x%08x\n", i,
0860                hw->fence[i]);
0861 
0862     printk("    INSTPM          0x%08x\n", hw->instpm);
0863     printk("    MEM_MODE        0x%08x\n", hw->mem_mode);
0864     printk("    FW_BLC_0        0x%08x\n", hw->fw_blc_0);
0865     printk("    FW_BLC_1        0x%08x\n", hw->fw_blc_1);
0866 
0867     printk("    HWSTAM          0x%04x\n", hw->hwstam);
0868     printk("    IER         0x%04x\n", hw->ier);
0869     printk("    IIR         0x%04x\n", hw->iir);
0870     printk("    IMR         0x%04x\n", hw->imr);
0871     printk("hw state dump end\n");
0872 #endif
0873 }
0874 
0875 
0876 
0877 /* Split the M parameter into M1 and M2. */
0878 static int splitm(int index, unsigned int m, unsigned int *retm1,
0879           unsigned int *retm2)
0880 {
0881     int m1, m2;
0882     int testm;
0883     struct pll_min_max *pll = &plls[index];
0884 
0885     /* no point optimising too much - brute force m */
0886     for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
0887         for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
0888             testm = (5 * (m1 + 2)) + (m2 + 2);
0889             if (testm == m) {
0890                 *retm1 = (unsigned int)m1;
0891                 *retm2 = (unsigned int)m2;
0892                 return 0;
0893             }
0894         }
0895     }
0896     return 1;
0897 }
0898 
0899 /* Split the P parameter into P1 and P2. */
0900 static int splitp(int index, unsigned int p, unsigned int *retp1,
0901           unsigned int *retp2)
0902 {
0903     int p1, p2;
0904     struct pll_min_max *pll = &plls[index];
0905 
0906     if (index == PLLS_I9xx) {
0907         p2 = (p % 10) ? 1 : 0;
0908 
0909         p1 = p / (p2 ? 5 : 10);
0910 
0911         *retp1 = (unsigned int)p1;
0912         *retp2 = (unsigned int)p2;
0913         return 0;
0914     }
0915 
0916     if (p % 4 == 0)
0917         p2 = 1;
0918     else
0919         p2 = 0;
0920     p1 = (p / (1 << (p2 + 1))) - 2;
0921     if (p % 4 == 0 && p1 < pll->min_p1) {
0922         p2 = 0;
0923         p1 = (p / (1 << (p2 + 1))) - 2;
0924     }
0925     if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
0926         (p1 + 2) * (1 << (p2 + 1)) != p) {
0927         return 1;
0928     } else {
0929         *retp1 = (unsigned int)p1;
0930         *retp2 = (unsigned int)p2;
0931         return 0;
0932     }
0933 }
0934 
0935 static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
0936                u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
0937 {
0938     u32 m1, m2, n, p1, p2, n1, testm;
0939     u32 f_vco, p, p_best = 0, m, f_out = 0;
0940     u32 err_best = 10000000;
0941     u32 n_best = 0, m_best = 0, f_err;
0942     u32 p_min, p_max, p_inc, div_max;
0943     struct pll_min_max *pll = &plls[index];
0944 
0945     DBG_MSG("Clock is %d\n", clock);
0946 
0947     div_max = pll->max_vco / clock;
0948 
0949     p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
0950     p_min = p_inc;
0951     p_max = ROUND_DOWN_TO(div_max, p_inc);
0952     if (p_min < pll->min_p)
0953         p_min = pll->min_p;
0954     if (p_max > pll->max_p)
0955         p_max = pll->max_p;
0956 
0957     DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
0958 
0959     p = p_min;
0960     do {
0961         if (splitp(index, p, &p1, &p2)) {
0962             WRN_MSG("cannot split p = %d\n", p);
0963             p += p_inc;
0964             continue;
0965         }
0966         n = pll->min_n;
0967         f_vco = clock * p;
0968 
0969         do {
0970             m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
0971             if (m < pll->min_m)
0972                 m = pll->min_m + 1;
0973             if (m > pll->max_m)
0974                 m = pll->max_m - 1;
0975             for (testm = m - 1; testm <= m; testm++) {
0976                 f_out = calc_vclock3(index, testm, n, p);
0977                 if (splitm(index, testm, &m1, &m2)) {
0978                     WRN_MSG("cannot split m = %d\n",
0979                         testm);
0980                     continue;
0981                 }
0982                 if (clock > f_out)
0983                     f_err = clock - f_out;
0984                 else/* slightly bias the error for bigger clocks */
0985                     f_err = f_out - clock + 1;
0986 
0987                 if (f_err < err_best) {
0988                     m_best = testm;
0989                     n_best = n;
0990                     p_best = p;
0991                     err_best = f_err;
0992                 }
0993             }
0994             n++;
0995         } while ((n <= pll->max_n) && (f_out >= clock));
0996         p += p_inc;
0997     } while ((p <= p_max));
0998 
0999     if (!m_best) {
1000         WRN_MSG("cannot find parameters for clock %d\n", clock);
1001         return 1;
1002     }
1003     m = m_best;
1004     n = n_best;
1005     p = p_best;
1006     splitm(index, m, &m1, &m2);
1007     splitp(index, p, &p1, &p2);
1008     n1 = n - 2;
1009 
1010     DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
1011         "f: %d (%d), VCO: %d\n",
1012         m, m1, m2, n, n1, p, p1, p2,
1013         calc_vclock3(index, m, n, p),
1014         calc_vclock(index, m1, m2, n1, p1, p2, 0),
1015         calc_vclock3(index, m, n, p) * p);
1016     *retm1 = m1;
1017     *retm2 = m2;
1018     *retn = n1;
1019     *retp1 = p1;
1020     *retp2 = p2;
1021     *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1022 
1023     return 0;
1024 }
1025 
1026 static __inline__ int check_overflow(u32 value, u32 limit,
1027                      const char *description)
1028 {
1029     if (value > limit) {
1030         WRN_MSG("%s value %d exceeds limit %d\n",
1031             description, value, limit);
1032         return 1;
1033     }
1034     return 0;
1035 }
1036 
1037 /* It is assumed that hw is filled in with the initial state information. */
1038 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
1039              struct intelfb_hwstate *hw,
1040              struct fb_var_screeninfo *var)
1041 {
1042     int pipe = intelfbhw_active_pipe(hw);
1043     u32 *dpll, *fp0, *fp1;
1044     u32 m1, m2, n, p1, p2, clock_target, clock;
1045     u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1046     u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1047     u32 vsync_pol, hsync_pol;
1048     u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1049     u32 stride_alignment;
1050 
1051     DBG_MSG("intelfbhw_mode_to_hw\n");
1052 
1053     /* Disable VGA */
1054     hw->vgacntrl |= VGA_DISABLE;
1055 
1056     /* Set which pipe's registers will be set. */
1057     if (pipe == PIPE_B) {
1058         dpll = &hw->dpll_b;
1059         fp0 = &hw->fpb0;
1060         fp1 = &hw->fpb1;
1061         hs = &hw->hsync_b;
1062         hb = &hw->hblank_b;
1063         ht = &hw->htotal_b;
1064         vs = &hw->vsync_b;
1065         vb = &hw->vblank_b;
1066         vt = &hw->vtotal_b;
1067         ss = &hw->src_size_b;
1068         pipe_conf = &hw->pipe_b_conf;
1069     } else {
1070         dpll = &hw->dpll_a;
1071         fp0 = &hw->fpa0;
1072         fp1 = &hw->fpa1;
1073         hs = &hw->hsync_a;
1074         hb = &hw->hblank_a;
1075         ht = &hw->htotal_a;
1076         vs = &hw->vsync_a;
1077         vb = &hw->vblank_a;
1078         vt = &hw->vtotal_a;
1079         ss = &hw->src_size_a;
1080         pipe_conf = &hw->pipe_a_conf;
1081     }
1082 
1083     /* Use ADPA register for sync control. */
1084     hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1085 
1086     /* sync polarity */
1087     hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1088             ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1089     vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1090             ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1091     hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1092               (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1093     hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1094             (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1095 
1096     /* Connect correct pipe to the analog port DAC */
1097     hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1098     hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1099 
1100     /* Set DPMS state to D0 (on) */
1101     hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1102     hw->adpa |= ADPA_DPMS_D0;
1103 
1104     hw->adpa |= ADPA_DAC_ENABLE;
1105 
1106     *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1107     *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1108     *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1109 
1110     /* Desired clock in kHz */
1111     clock_target = 1000000000 / var->pixclock;
1112 
1113     if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1114                 &n, &p1, &p2, &clock)) {
1115         WRN_MSG("calc_pll_params failed\n");
1116         return 1;
1117     }
1118 
1119     /* Check for overflow. */
1120     if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1121         return 1;
1122     if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1123         return 1;
1124     if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1125         return 1;
1126     if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1127         return 1;
1128     if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1129         return 1;
1130 
1131     *dpll &= ~DPLL_P1_FORCE_DIV2;
1132     *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1133            (DPLL_P1_MASK << DPLL_P1_SHIFT));
1134 
1135     if (IS_I9XX(dinfo)) {
1136         *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1137         *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1138     } else
1139         *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1140 
1141     *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1142            (m1 << FP_M1_DIVISOR_SHIFT) |
1143            (m2 << FP_M2_DIVISOR_SHIFT);
1144     *fp1 = *fp0;
1145 
1146     hw->dvob &= ~PORT_ENABLE;
1147     hw->dvoc &= ~PORT_ENABLE;
1148 
1149     /* Use display plane A. */
1150     hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1151     hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1152     hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1153     switch (intelfb_var_to_depth(var)) {
1154     case 8:
1155         hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1156         break;
1157     case 15:
1158         hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1159         break;
1160     case 16:
1161         hw->disp_a_ctrl |= DISPPLANE_16BPP;
1162         break;
1163     case 24:
1164         hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1165         break;
1166     }
1167     hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1168     hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1169 
1170     /* Set CRTC registers. */
1171     hactive = var->xres;
1172     hsync_start = hactive + var->right_margin;
1173     hsync_end = hsync_start + var->hsync_len;
1174     htotal = hsync_end + var->left_margin;
1175     hblank_start = hactive;
1176     hblank_end = htotal;
1177 
1178     DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1179         hactive, hsync_start, hsync_end, htotal, hblank_start,
1180         hblank_end);
1181 
1182     vactive = var->yres;
1183     if (var->vmode & FB_VMODE_INTERLACED)
1184         vactive--; /* the chip adds 2 halflines automatically */
1185     vsync_start = vactive + var->lower_margin;
1186     vsync_end = vsync_start + var->vsync_len;
1187     vtotal = vsync_end + var->upper_margin;
1188     vblank_start = vactive;
1189     vblank_end = vsync_end + 1;
1190 
1191     DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1192         vactive, vsync_start, vsync_end, vtotal, vblank_start,
1193         vblank_end);
1194 
1195     /* Adjust for register values, and check for overflow. */
1196     hactive--;
1197     if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1198         return 1;
1199     hsync_start--;
1200     if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1201         return 1;
1202     hsync_end--;
1203     if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1204         return 1;
1205     htotal--;
1206     if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1207         return 1;
1208     hblank_start--;
1209     if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1210         return 1;
1211     hblank_end--;
1212     if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1213         return 1;
1214 
1215     vactive--;
1216     if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1217         return 1;
1218     vsync_start--;
1219     if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1220         return 1;
1221     vsync_end--;
1222     if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1223         return 1;
1224     vtotal--;
1225     if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1226         return 1;
1227     vblank_start--;
1228     if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1229         return 1;
1230     vblank_end--;
1231     if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1232         return 1;
1233 
1234     *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1235     *hb = (hblank_start << HBLANKSTART_SHIFT) |
1236           (hblank_end << HSYNCEND_SHIFT);
1237     *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1238 
1239     *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1240     *vb = (vblank_start << VBLANKSTART_SHIFT) |
1241           (vblank_end << VSYNCEND_SHIFT);
1242     *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1243     *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1244           (vactive << SRC_SIZE_VERT_SHIFT);
1245 
1246     hw->disp_a_stride = dinfo->pitch;
1247     DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1248 
1249     hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1250               var->xoffset * var->bits_per_pixel / 8;
1251 
1252     hw->disp_a_base += dinfo->fb.offset << 12;
1253 
1254     /* Check stride alignment. */
1255     stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1256                         STRIDE_ALIGNMENT;
1257     if (hw->disp_a_stride % stride_alignment != 0) {
1258         WRN_MSG("display stride %d has bad alignment %d\n",
1259             hw->disp_a_stride, stride_alignment);
1260         return 1;
1261     }
1262 
1263     /* Set the palette to 8-bit mode. */
1264     *pipe_conf &= ~PIPECONF_GAMMA;
1265 
1266     if (var->vmode & FB_VMODE_INTERLACED)
1267         *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
1268     else
1269         *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
1270 
1271     return 0;
1272 }
1273 
1274 /* Program a (non-VGA) video mode. */
1275 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1276                const struct intelfb_hwstate *hw, int blank)
1277 {
1278     u32 tmp;
1279     const u32 *dpll, *fp0, *fp1, *pipe_conf;
1280     const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1281     u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
1282     u32 hsync_reg, htotal_reg, hblank_reg;
1283     u32 vsync_reg, vtotal_reg, vblank_reg;
1284     u32 src_size_reg;
1285     u32 count, tmp_val[3];
1286 
1287     /* Assume single pipe */
1288 
1289 #if VERBOSE > 0
1290     DBG_MSG("intelfbhw_program_mode\n");
1291 #endif
1292 
1293     /* Disable VGA */
1294     tmp = INREG(VGACNTRL);
1295     tmp |= VGA_DISABLE;
1296     OUTREG(VGACNTRL, tmp);
1297 
1298     dinfo->pipe = intelfbhw_active_pipe(hw);
1299 
1300     if (dinfo->pipe == PIPE_B) {
1301         dpll = &hw->dpll_b;
1302         fp0 = &hw->fpb0;
1303         fp1 = &hw->fpb1;
1304         pipe_conf = &hw->pipe_b_conf;
1305         hs = &hw->hsync_b;
1306         hb = &hw->hblank_b;
1307         ht = &hw->htotal_b;
1308         vs = &hw->vsync_b;
1309         vb = &hw->vblank_b;
1310         vt = &hw->vtotal_b;
1311         ss = &hw->src_size_b;
1312         dpll_reg = DPLL_B;
1313         fp0_reg = FPB0;
1314         fp1_reg = FPB1;
1315         pipe_conf_reg = PIPEBCONF;
1316         pipe_stat_reg = PIPEBSTAT;
1317         hsync_reg = HSYNC_B;
1318         htotal_reg = HTOTAL_B;
1319         hblank_reg = HBLANK_B;
1320         vsync_reg = VSYNC_B;
1321         vtotal_reg = VTOTAL_B;
1322         vblank_reg = VBLANK_B;
1323         src_size_reg = SRC_SIZE_B;
1324     } else {
1325         dpll = &hw->dpll_a;
1326         fp0 = &hw->fpa0;
1327         fp1 = &hw->fpa1;
1328         pipe_conf = &hw->pipe_a_conf;
1329         hs = &hw->hsync_a;
1330         hb = &hw->hblank_a;
1331         ht = &hw->htotal_a;
1332         vs = &hw->vsync_a;
1333         vb = &hw->vblank_a;
1334         vt = &hw->vtotal_a;
1335         ss = &hw->src_size_a;
1336         dpll_reg = DPLL_A;
1337         fp0_reg = FPA0;
1338         fp1_reg = FPA1;
1339         pipe_conf_reg = PIPEACONF;
1340         pipe_stat_reg = PIPEASTAT;
1341         hsync_reg = HSYNC_A;
1342         htotal_reg = HTOTAL_A;
1343         hblank_reg = HBLANK_A;
1344         vsync_reg = VSYNC_A;
1345         vtotal_reg = VTOTAL_A;
1346         vblank_reg = VBLANK_A;
1347         src_size_reg = SRC_SIZE_A;
1348     }
1349 
1350     /* turn off pipe */
1351     tmp = INREG(pipe_conf_reg);
1352     tmp &= ~PIPECONF_ENABLE;
1353     OUTREG(pipe_conf_reg, tmp);
1354 
1355     count = 0;
1356     do {
1357         tmp_val[count % 3] = INREG(PIPEA_DSL);
1358         if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
1359             break;
1360         count++;
1361         udelay(1);
1362         if (count % 200 == 0) {
1363             tmp = INREG(pipe_conf_reg);
1364             tmp &= ~PIPECONF_ENABLE;
1365             OUTREG(pipe_conf_reg, tmp);
1366         }
1367     } while (count < 2000);
1368 
1369     OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1370 
1371     /* Disable planes A and B. */
1372     tmp = INREG(DSPACNTR);
1373     tmp &= ~DISPPLANE_PLANE_ENABLE;
1374     OUTREG(DSPACNTR, tmp);
1375     tmp = INREG(DSPBCNTR);
1376     tmp &= ~DISPPLANE_PLANE_ENABLE;
1377     OUTREG(DSPBCNTR, tmp);
1378 
1379     /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1380     mdelay(20);
1381 
1382     OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1383     OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1384     OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1385 
1386     /* Disable Sync */
1387     tmp = INREG(ADPA);
1388     tmp &= ~ADPA_DPMS_CONTROL_MASK;
1389     tmp |= ADPA_DPMS_D3;
1390     OUTREG(ADPA, tmp);
1391 
1392     /* do some funky magic - xyzzy */
1393     OUTREG(0x61204, 0xabcd0000);
1394 
1395     /* turn off PLL */
1396     tmp = INREG(dpll_reg);
1397     tmp &= ~DPLL_VCO_ENABLE;
1398     OUTREG(dpll_reg, tmp);
1399 
1400     /* Set PLL parameters */
1401     OUTREG(fp0_reg, *fp0);
1402     OUTREG(fp1_reg, *fp1);
1403 
1404     /* Enable PLL */
1405     OUTREG(dpll_reg, *dpll);
1406 
1407     /* Set DVOs B/C */
1408     OUTREG(DVOB, hw->dvob);
1409     OUTREG(DVOC, hw->dvoc);
1410 
1411     /* undo funky magic */
1412     OUTREG(0x61204, 0x00000000);
1413 
1414     /* Set ADPA */
1415     OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1416     OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1417 
1418     /* Set pipe parameters */
1419     OUTREG(hsync_reg, *hs);
1420     OUTREG(hblank_reg, *hb);
1421     OUTREG(htotal_reg, *ht);
1422     OUTREG(vsync_reg, *vs);
1423     OUTREG(vblank_reg, *vb);
1424     OUTREG(vtotal_reg, *vt);
1425     OUTREG(src_size_reg, *ss);
1426 
1427     switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
1428                       FB_VMODE_ODD_FLD_FIRST)) {
1429     case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:
1430         OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);
1431         break;
1432     case FB_VMODE_INTERLACED: /* even lines first */
1433         OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);
1434         break;
1435     default:        /* non-interlaced */
1436         OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */
1437     }
1438     /* Enable pipe */
1439     OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1440 
1441     /* Enable sync */
1442     tmp = INREG(ADPA);
1443     tmp &= ~ADPA_DPMS_CONTROL_MASK;
1444     tmp |= ADPA_DPMS_D0;
1445     OUTREG(ADPA, tmp);
1446 
1447     /* setup display plane */
1448     if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1449         /*
1450          *      i830M errata: the display plane must be enabled
1451          *      to allow writes to the other bits in the plane
1452          *      control register.
1453          */
1454         tmp = INREG(DSPACNTR);
1455         if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1456             tmp |= DISPPLANE_PLANE_ENABLE;
1457             OUTREG(DSPACNTR, tmp);
1458             OUTREG(DSPACNTR,
1459                    hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1460             mdelay(1);
1461         }
1462     }
1463 
1464     OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1465     OUTREG(DSPASTRIDE, hw->disp_a_stride);
1466     OUTREG(DSPABASE, hw->disp_a_base);
1467 
1468     /* Enable plane */
1469     if (!blank) {
1470         tmp = INREG(DSPACNTR);
1471         tmp |= DISPPLANE_PLANE_ENABLE;
1472         OUTREG(DSPACNTR, tmp);
1473         OUTREG(DSPABASE, hw->disp_a_base);
1474     }
1475 
1476     return 0;
1477 }
1478 
1479 /* forward declarations */
1480 static void refresh_ring(struct intelfb_info *dinfo);
1481 static void reset_state(struct intelfb_info *dinfo);
1482 static void do_flush(struct intelfb_info *dinfo);
1483 
1484 static  u32 get_ring_space(struct intelfb_info *dinfo)
1485 {
1486     u32 ring_space;
1487 
1488     if (dinfo->ring_tail >= dinfo->ring_head)
1489         ring_space = dinfo->ring.size -
1490             (dinfo->ring_tail - dinfo->ring_head);
1491     else
1492         ring_space = dinfo->ring_head - dinfo->ring_tail;
1493 
1494     if (ring_space > RING_MIN_FREE)
1495         ring_space -= RING_MIN_FREE;
1496     else
1497         ring_space = 0;
1498 
1499     return ring_space;
1500 }
1501 
1502 static int wait_ring(struct intelfb_info *dinfo, int n)
1503 {
1504     int i = 0;
1505     unsigned long end;
1506     u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1507 
1508 #if VERBOSE > 0
1509     DBG_MSG("wait_ring: %d\n", n);
1510 #endif
1511 
1512     end = jiffies + (HZ * 3);
1513     while (dinfo->ring_space < n) {
1514         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1515         dinfo->ring_space = get_ring_space(dinfo);
1516 
1517         if (dinfo->ring_head != last_head) {
1518             end = jiffies + (HZ * 3);
1519             last_head = dinfo->ring_head;
1520         }
1521         i++;
1522         if (time_before(end, jiffies)) {
1523             if (!i) {
1524                 /* Try again */
1525                 reset_state(dinfo);
1526                 refresh_ring(dinfo);
1527                 do_flush(dinfo);
1528                 end = jiffies + (HZ * 3);
1529                 i = 1;
1530             } else {
1531                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1532                     dinfo->ring_space, n);
1533                 WRN_MSG("lockup - turning off hardware "
1534                     "acceleration\n");
1535                 dinfo->ring_lockup = 1;
1536                 break;
1537             }
1538         }
1539         udelay(1);
1540     }
1541     return i;
1542 }
1543 
1544 static void do_flush(struct intelfb_info *dinfo)
1545 {
1546     START_RING(2);
1547     OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1548     OUT_RING(MI_NOOP);
1549     ADVANCE_RING();
1550 }
1551 
1552 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1553 {
1554 #if VERBOSE > 0
1555     DBG_MSG("intelfbhw_do_sync\n");
1556 #endif
1557 
1558     if (!dinfo->accel)
1559         return;
1560 
1561     /*
1562      * Send a flush, then wait until the ring is empty.  This is what
1563      * the XFree86 driver does, and actually it doesn't seem a lot worse
1564      * than the recommended method (both have problems).
1565      */
1566     do_flush(dinfo);
1567     wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1568     dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1569 }
1570 
1571 static void refresh_ring(struct intelfb_info *dinfo)
1572 {
1573 #if VERBOSE > 0
1574     DBG_MSG("refresh_ring\n");
1575 #endif
1576 
1577     dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1578     dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1579     dinfo->ring_space = get_ring_space(dinfo);
1580 }
1581 
1582 static void reset_state(struct intelfb_info *dinfo)
1583 {
1584     int i;
1585     u32 tmp;
1586 
1587 #if VERBOSE > 0
1588     DBG_MSG("reset_state\n");
1589 #endif
1590 
1591     for (i = 0; i < FENCE_NUM; i++)
1592         OUTREG(FENCE + (i << 2), 0);
1593 
1594     /* Flush the ring buffer if it's enabled. */
1595     tmp = INREG(PRI_RING_LENGTH);
1596     if (tmp & RING_ENABLE) {
1597 #if VERBOSE > 0
1598         DBG_MSG("reset_state: ring was enabled\n");
1599 #endif
1600         refresh_ring(dinfo);
1601         intelfbhw_do_sync(dinfo);
1602         DO_RING_IDLE();
1603     }
1604 
1605     OUTREG(PRI_RING_LENGTH, 0);
1606     OUTREG(PRI_RING_HEAD, 0);
1607     OUTREG(PRI_RING_TAIL, 0);
1608     OUTREG(PRI_RING_START, 0);
1609 }
1610 
1611 /* Stop the 2D engine, and turn off the ring buffer. */
1612 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1613 {
1614 #if VERBOSE > 0
1615     DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
1616         dinfo->accel, dinfo->ring_active);
1617 #endif
1618 
1619     if (!dinfo->accel)
1620         return;
1621 
1622     dinfo->ring_active = 0;
1623     reset_state(dinfo);
1624 }
1625 
1626 /*
1627  * Enable the ring buffer, and initialise the 2D engine.
1628  * It is assumed that the graphics engine has been stopped by previously
1629  * calling intelfb_2d_stop().
1630  */
1631 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1632 {
1633 #if VERBOSE > 0
1634     DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1635         dinfo->accel, dinfo->ring_active);
1636 #endif
1637 
1638     if (!dinfo->accel)
1639         return;
1640 
1641     /* Initialise the primary ring buffer. */
1642     OUTREG(PRI_RING_LENGTH, 0);
1643     OUTREG(PRI_RING_TAIL, 0);
1644     OUTREG(PRI_RING_HEAD, 0);
1645 
1646     OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1647     OUTREG(PRI_RING_LENGTH,
1648         ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1649         RING_NO_REPORT | RING_ENABLE);
1650     refresh_ring(dinfo);
1651     dinfo->ring_active = 1;
1652 }
1653 
1654 /* 2D fillrect (solid fill or invert) */
1655 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1656                u32 h, u32 color, u32 pitch, u32 bpp, u32 rop)
1657 {
1658     u32 br00, br09, br13, br14, br16;
1659 
1660 #if VERBOSE > 0
1661     DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1662         "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1663 #endif
1664 
1665     br00 = COLOR_BLT_CMD;
1666     br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1667     br13 = (rop << ROP_SHIFT) | pitch;
1668     br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1669     br16 = color;
1670 
1671     switch (bpp) {
1672     case 8:
1673         br13 |= COLOR_DEPTH_8;
1674         break;
1675     case 16:
1676         br13 |= COLOR_DEPTH_16;
1677         break;
1678     case 32:
1679         br13 |= COLOR_DEPTH_32;
1680         br00 |= WRITE_ALPHA | WRITE_RGB;
1681         break;
1682     }
1683 
1684     START_RING(6);
1685     OUT_RING(br00);
1686     OUT_RING(br13);
1687     OUT_RING(br14);
1688     OUT_RING(br09);
1689     OUT_RING(br16);
1690     OUT_RING(MI_NOOP);
1691     ADVANCE_RING();
1692 
1693 #if VERBOSE > 0
1694     DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1695         dinfo->ring_tail, dinfo->ring_space);
1696 #endif
1697 }
1698 
1699 void
1700 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1701             u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1702 {
1703     u32 br00, br09, br11, br12, br13, br22, br23, br26;
1704 
1705 #if VERBOSE > 0
1706     DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1707         curx, cury, dstx, dsty, w, h, pitch, bpp);
1708 #endif
1709 
1710     br00 = XY_SRC_COPY_BLT_CMD;
1711     br09 = dinfo->fb_start;
1712     br11 = (pitch << PITCH_SHIFT);
1713     br12 = dinfo->fb_start;
1714     br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1715     br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1716     br23 = ((dstx + w) << WIDTH_SHIFT) |
1717            ((dsty + h) << HEIGHT_SHIFT);
1718     br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1719 
1720     switch (bpp) {
1721     case 8:
1722         br13 |= COLOR_DEPTH_8;
1723         break;
1724     case 16:
1725         br13 |= COLOR_DEPTH_16;
1726         break;
1727     case 32:
1728         br13 |= COLOR_DEPTH_32;
1729         br00 |= WRITE_ALPHA | WRITE_RGB;
1730         break;
1731     }
1732 
1733     START_RING(8);
1734     OUT_RING(br00);
1735     OUT_RING(br13);
1736     OUT_RING(br22);
1737     OUT_RING(br23);
1738     OUT_RING(br09);
1739     OUT_RING(br26);
1740     OUT_RING(br11);
1741     OUT_RING(br12);
1742     ADVANCE_RING();
1743 }
1744 
1745 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1746                u32 h, const u8* cdat, u32 x, u32 y, u32 pitch,
1747                u32 bpp)
1748 {
1749     int nbytes, ndwords, pad, tmp;
1750     u32 br00, br09, br13, br18, br19, br22, br23;
1751     int dat, ix, iy, iw;
1752     int i, j;
1753 
1754 #if VERBOSE > 0
1755     DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1756 #endif
1757 
1758     /* size in bytes of a padded scanline */
1759     nbytes = ROUND_UP_TO(w, 16) / 8;
1760 
1761     /* Total bytes of padded scanline data to write out. */
1762     nbytes = nbytes * h;
1763 
1764     /*
1765      * Check if the glyph data exceeds the immediate mode limit.
1766      * It would take a large font (1K pixels) to hit this limit.
1767      */
1768     if (nbytes > MAX_MONO_IMM_SIZE)
1769         return 0;
1770 
1771     /* Src data is packaged a dword (32-bit) at a time. */
1772     ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1773 
1774     /*
1775      * Ring has to be padded to a quad word. But because the command starts
1776        with 7 bytes, pad only if there is an even number of ndwords
1777      */
1778     pad = !(ndwords % 2);
1779 
1780     tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1781     br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1782     br09 = dinfo->fb_start;
1783     br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1784     br18 = bg;
1785     br19 = fg;
1786     br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1787     br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1788 
1789     switch (bpp) {
1790     case 8:
1791         br13 |= COLOR_DEPTH_8;
1792         break;
1793     case 16:
1794         br13 |= COLOR_DEPTH_16;
1795         break;
1796     case 32:
1797         br13 |= COLOR_DEPTH_32;
1798         br00 |= WRITE_ALPHA | WRITE_RGB;
1799         break;
1800     }
1801 
1802     START_RING(8 + ndwords);
1803     OUT_RING(br00);
1804     OUT_RING(br13);
1805     OUT_RING(br22);
1806     OUT_RING(br23);
1807     OUT_RING(br09);
1808     OUT_RING(br18);
1809     OUT_RING(br19);
1810     ix = iy = 0;
1811     iw = ROUND_UP_TO(w, 8) / 8;
1812     while (ndwords--) {
1813         dat = 0;
1814         for (j = 0; j < 2; ++j) {
1815             for (i = 0; i < 2; ++i) {
1816                 if (ix != iw || i == 0)
1817                     dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1818             }
1819             if (ix == iw && iy != (h-1)) {
1820                 ix = 0;
1821                 ++iy;
1822             }
1823         }
1824         OUT_RING(dat);
1825     }
1826     if (pad)
1827         OUT_RING(MI_NOOP);
1828     ADVANCE_RING();
1829 
1830     return 1;
1831 }
1832 
1833 /* HW cursor functions. */
1834 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1835 {
1836     u32 tmp;
1837 
1838 #if VERBOSE > 0
1839     DBG_MSG("intelfbhw_cursor_init\n");
1840 #endif
1841 
1842     if (dinfo->mobile || IS_I9XX(dinfo)) {
1843         if (!dinfo->cursor.physical)
1844             return;
1845         tmp = INREG(CURSOR_A_CONTROL);
1846         tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1847              CURSOR_MEM_TYPE_LOCAL |
1848              (1 << CURSOR_PIPE_SELECT_SHIFT));
1849         tmp |= CURSOR_MODE_DISABLE;
1850         OUTREG(CURSOR_A_CONTROL, tmp);
1851         OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1852     } else {
1853         tmp = INREG(CURSOR_CONTROL);
1854         tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1855              CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1856         tmp |= CURSOR_FORMAT_3C;
1857         OUTREG(CURSOR_CONTROL, tmp);
1858         OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1859         tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1860               (64 << CURSOR_SIZE_V_SHIFT);
1861         OUTREG(CURSOR_SIZE, tmp);
1862     }
1863 }
1864 
1865 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1866 {
1867     u32 tmp;
1868 
1869 #if VERBOSE > 0
1870     DBG_MSG("intelfbhw_cursor_hide\n");
1871 #endif
1872 
1873     dinfo->cursor_on = 0;
1874     if (dinfo->mobile || IS_I9XX(dinfo)) {
1875         if (!dinfo->cursor.physical)
1876             return;
1877         tmp = INREG(CURSOR_A_CONTROL);
1878         tmp &= ~CURSOR_MODE_MASK;
1879         tmp |= CURSOR_MODE_DISABLE;
1880         OUTREG(CURSOR_A_CONTROL, tmp);
1881         /* Flush changes */
1882         OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1883     } else {
1884         tmp = INREG(CURSOR_CONTROL);
1885         tmp &= ~CURSOR_ENABLE;
1886         OUTREG(CURSOR_CONTROL, tmp);
1887     }
1888 }
1889 
1890 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1891 {
1892     u32 tmp;
1893 
1894 #if VERBOSE > 0
1895     DBG_MSG("intelfbhw_cursor_show\n");
1896 #endif
1897 
1898     dinfo->cursor_on = 1;
1899 
1900     if (dinfo->cursor_blanked)
1901         return;
1902 
1903     if (dinfo->mobile || IS_I9XX(dinfo)) {
1904         if (!dinfo->cursor.physical)
1905             return;
1906         tmp = INREG(CURSOR_A_CONTROL);
1907         tmp &= ~CURSOR_MODE_MASK;
1908         tmp |= CURSOR_MODE_64_4C_AX;
1909         OUTREG(CURSOR_A_CONTROL, tmp);
1910         /* Flush changes */
1911         OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1912     } else {
1913         tmp = INREG(CURSOR_CONTROL);
1914         tmp |= CURSOR_ENABLE;
1915         OUTREG(CURSOR_CONTROL, tmp);
1916     }
1917 }
1918 
1919 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1920 {
1921     u32 tmp;
1922 
1923 #if VERBOSE > 0
1924     DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1925 #endif
1926 
1927     /*
1928      * Sets the position. The coordinates are assumed to already
1929      * have any offset adjusted. Assume that the cursor is never
1930      * completely off-screen, and that x, y are always >= 0.
1931      */
1932 
1933     tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1934           ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1935     OUTREG(CURSOR_A_POSITION, tmp);
1936 
1937     if (IS_I9XX(dinfo))
1938         OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1939 }
1940 
1941 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1942 {
1943 #if VERBOSE > 0
1944     DBG_MSG("intelfbhw_cursor_setcolor\n");
1945 #endif
1946 
1947     OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1948     OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1949     OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1950     OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1951 }
1952 
1953 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1954                u8 *data)
1955 {
1956     u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1957     int i, j, w = width / 8;
1958     int mod = width % 8, t_mask, d_mask;
1959 
1960 #if VERBOSE > 0
1961     DBG_MSG("intelfbhw_cursor_load\n");
1962 #endif
1963 
1964     if (!dinfo->cursor.virtual)
1965         return;
1966 
1967     t_mask = 0xff >> mod;
1968     d_mask = ~(0xff >> mod);
1969     for (i = height; i--; ) {
1970         for (j = 0; j < w; j++) {
1971             writeb(0x00, addr + j);
1972             writeb(*(data++), addr + j+8);
1973         }
1974         if (mod) {
1975             writeb(t_mask, addr + j);
1976             writeb(*(data++) & d_mask, addr + j+8);
1977         }
1978         addr += 16;
1979     }
1980 }
1981 
1982 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1983 {
1984     u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1985     int i, j;
1986 
1987 #if VERBOSE > 0
1988     DBG_MSG("intelfbhw_cursor_reset\n");
1989 #endif
1990 
1991     if (!dinfo->cursor.virtual)
1992         return;
1993 
1994     for (i = 64; i--; ) {
1995         for (j = 0; j < 8; j++) {
1996             writeb(0xff, addr + j+0);
1997             writeb(0x00, addr + j+8);
1998         }
1999         addr += 16;
2000     }
2001 }
2002 
2003 static irqreturn_t intelfbhw_irq(int irq, void *dev_id)
2004 {
2005     u16 tmp;
2006     struct intelfb_info *dinfo = dev_id;
2007 
2008     spin_lock(&dinfo->int_lock);
2009 
2010     tmp = INREG16(IIR);
2011     if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2012         tmp &= PIPE_A_EVENT_INTERRUPT;
2013     else
2014         tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2015 
2016     if (tmp == 0) {
2017         spin_unlock(&dinfo->int_lock);
2018         return IRQ_RETVAL(0); /* not us */
2019     }
2020 
2021     /* clear status bits 0-15 ASAP and don't touch bits 16-31 */
2022     OUTREG(PIPEASTAT, INREG(PIPEASTAT));
2023 
2024     OUTREG16(IIR, tmp);
2025     if (dinfo->vsync.pan_display) {
2026         dinfo->vsync.pan_display = 0;
2027         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2028     }
2029 
2030     dinfo->vsync.count++;
2031     wake_up_interruptible(&dinfo->vsync.wait);
2032 
2033     spin_unlock(&dinfo->int_lock);
2034 
2035     return IRQ_RETVAL(1);
2036 }
2037 
2038 int intelfbhw_enable_irq(struct intelfb_info *dinfo)
2039 {
2040     u16 tmp;
2041     if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2042         if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2043                 "intelfb", dinfo)) {
2044             clear_bit(0, &dinfo->irq_flags);
2045             return -EINVAL;
2046         }
2047 
2048         spin_lock_irq(&dinfo->int_lock);
2049         OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */
2050         OUTREG16(IMR, 0);
2051     } else
2052         spin_lock_irq(&dinfo->int_lock);
2053 
2054     if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2055         tmp = PIPE_A_EVENT_INTERRUPT;
2056     else
2057         tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2058     if (tmp != INREG16(IER)) {
2059         DBG_MSG("changing IER to 0x%X\n", tmp);
2060         OUTREG16(IER, tmp);
2061     }
2062 
2063     spin_unlock_irq(&dinfo->int_lock);
2064     return 0;
2065 }
2066 
2067 void intelfbhw_disable_irq(struct intelfb_info *dinfo)
2068 {
2069     if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2070         if (dinfo->vsync.pan_display) {
2071             dinfo->vsync.pan_display = 0;
2072             OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2073         }
2074         spin_lock_irq(&dinfo->int_lock);
2075         OUTREG16(HWSTAM, 0xffff);
2076         OUTREG16(IMR, 0xffff);
2077         OUTREG16(IER, 0x0);
2078 
2079         OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
2080         spin_unlock_irq(&dinfo->int_lock);
2081 
2082         free_irq(dinfo->pdev->irq, dinfo);
2083     }
2084 }
2085 
2086 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2087 {
2088     struct intelfb_vsync *vsync;
2089     unsigned int count;
2090     int ret;
2091 
2092     switch (pipe) {
2093         case 0:
2094             vsync = &dinfo->vsync;
2095             break;
2096         default:
2097             return -ENODEV;
2098     }
2099 
2100     ret = intelfbhw_enable_irq(dinfo);
2101     if (ret)
2102         return ret;
2103 
2104     count = vsync->count;
2105     ret = wait_event_interruptible_timeout(vsync->wait,
2106                            count != vsync->count, HZ / 10);
2107     if (ret < 0)
2108         return ret;
2109     if (ret == 0) {
2110         DBG_MSG("wait_for_vsync timed out!\n");
2111         return -ETIMEDOUT;
2112     }
2113 
2114     return 0;
2115 }
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