fbdev/i810/i810.h

0001 /*-*- linux-c -*-
0002  *  linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
0003  *
0004  *      Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
0005  *      All Rights Reserved
0006  *
0007  *
0008  *  This file is subject to the terms and conditions of the GNU General Public
0009  *  License. See the file COPYING in the main directory of this archive for
0010  *  more details.
0011  */
0012
0013 #ifndef __I810_H__
0014 #define __I810_H__
0015
0016 #include <linux/list.h>
0017 #include <linux/agp_backend.h>
0018 #include <linux/fb.h>
0019 #include <linux/i2c.h>
0020 #include <linux/i2c-algo-bit.h>
0021 #include <video/vga.h>
0022
0023 /* Fence */
0024 #define TILEWALK_X            (0 << 12)
0025 #define TILEWALK_Y            (1 << 12)
0026
0027 /* Raster ops */
0028 #define COLOR_COPY_ROP        0xF0
0029 #define PAT_COPY_ROP          0xCC
0030 #define CLEAR_ROP             0x00
0031 #define WHITE_ROP             0xFF
0032 #define INVERT_ROP            0x55
0033 #define XOR_ROP               0x5A
0034
0035 /* 2D Engine definitions */
0036 #define SOLIDPATTERN          0x80000000
0037 #define NONSOLID              0x00000000
0038 #define BPP8                  (0 << 24)
0039 #define BPP16                 (1 << 24)
0040 #define BPP24                 (2 << 24)
0041
0042 #define PIXCONF8              (2 << 16)
0043 #define PIXCONF15             (4 << 16)
0044 #define PIXCONF16             (5 << 16)
0045 #define PIXCONF24             (6 << 16)
0046 #define PIXCONF32             (7 << 16)
0047
0048 #define DYN_COLOR_EN          (1 << 26)
0049 #define DYN_COLOR_DIS         (0 << 26)
0050 #define INCREMENT             0x00000000
0051 #define DECREMENT             (0x01 << 30)
0052 #define ARB_ON                0x00000001
0053 #define ARB_OFF               0x00000000
0054 #define SYNC_FLIP             0x00000000
0055 #define ASYNC_FLIP            0x00000040
0056 #define OPTYPE_MASK           0xE0000000
0057 #define PARSER_MASK           0x001F8000
0058 #define D2_MASK               0x001FC000         /* 2D mask */
0059
0060 /* Instruction type */
0061 /* There are more but pertains to 3D */
0062 #define PARSER                0x00000000
0063 #define BLIT                  (0x02 << 29)
0064 #define RENDER                (0x03 << 29)
0065
0066 /* Parser */
0067 #define NOP                   0x00               /* No operation, padding */
0068 #define BP_INT                (0x01 << 23)         /* Breakpoint interrupt */
0069 #define USR_INT               (0x02 << 23)         /* User interrupt */
0070 #define WAIT_FOR_EVNT         (0x03 << 23)         /* Wait for event */
0071 #define FLUSH                 (0x04 << 23)
0072 #define CONTEXT_SEL           (0x05 << 23)
0073 #define REPORT_HEAD           (0x07 << 23)
0074 #define ARB_ON_OFF            (0x08 << 23)
0075 #define OVERLAY_FLIP          (0x11 << 23)
0076 #define LOAD_SCAN_INC         (0x12 << 23)
0077 #define LOAD_SCAN_EX          (0x13 << 23)
0078 #define FRONT_BUFFER          (0x14 << 23)
0079 #define DEST_BUFFER           (0x15 << 23)
0080 #define Z_BUFFER              (0x16 << 23)
0081
0082 #define STORE_DWORD_IMM       (0x20 << 23)
0083 #define STORE_DWORD_IDX       (0x21 << 23)
0084 #define BATCH_BUFFER          (0x30 << 23)
0085
0086 /* Blit */
0087 #define SETUP_BLIT                      0x00
0088 #define SETUP_MONO_PATTERN_SL_BLT       (0x10 << 22)
0089 #define PIXEL_BLT                       (0x20 << 22)
0090 #define SCANLINE_BLT                    (0x21 << 22)
0091 #define TEXT_BLT                        (0x22 << 22)
0092 #define TEXT_IMM_BLT                    (0x30 << 22)
0093 #define COLOR_BLT                       (0x40 << 22)
0094 #define MONO_PAT_BLIT                   (0x42 << 22)
0095 #define SOURCE_COPY_BLIT                (0x43 << 22)
0096 #define MONO_SOURCE_COPY_BLIT           (0x44 << 22)
0097 #define SOURCE_COPY_IMMEDIATE           (0x60 << 22)
0098 #define MONO_SOURCE_COPY_IMMEDIATE      (0x61 << 22)
0099
0100 #define VERSION_MAJOR            0
0101 #define VERSION_MINOR            9
0102 #define VERSION_TEENIE           0
0103 #define BRANCH_VERSION           ""
0104
0105
0106 /* mvo: intel i815 */
0107 #ifndef PCI_DEVICE_ID_INTEL_82815_100
0108   #define PCI_DEVICE_ID_INTEL_82815_100           0x1102
0109 #endif
0110 #ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
0111   #define PCI_DEVICE_ID_INTEL_82815_NOAGP         0x1112
0112 #endif
0113 #ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
0114   #define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL     0x1130
0115 #endif
0116
0117 /* General Defines */
0118 #define I810_PAGESIZE               4096
0119 #define MAX_DMA_SIZE                (1024 * 4096)
0120 #define SAREA_SIZE                  4096
0121 #define PCI_I810_MISCC              0x72
0122 #define MMIO_SIZE                   (512*1024)
0123 #define GTT_SIZE                    (16*1024)
0124 #define RINGBUFFER_SIZE             (64*1024)
0125 #define CURSOR_SIZE                 4096
0126 #define OFF                         0
0127 #define ON                          1
0128 #define MAX_KEY                     256
0129 #define WAIT_COUNT                  10000000
0130 #define IRING_PAD                   8
0131 #define FONTDATAMAX                 8192
0132 /* Masks (AND ops) and OR's */
0133 #define FB_START_MASK               (0x3f << (32 - 6))
0134 #define MMIO_ADDR_MASK              (0x1FFF << (32 - 13))
0135 #define FREQ_MASK                   (1 << 4)
0136 #define SCR_OFF                     0x20
0137 #define DRAM_ON                     0x08
0138 #define DRAM_OFF                    0xE7
0139 #define PG_ENABLE_MASK              0x01
0140 #define RING_SIZE_MASK              (RINGBUFFER_SIZE - 1)
0141
0142 /* defines for restoring registers partially */
0143 #define ADDR_MAP_MASK               (0x07 << 5)
0144 #define DISP_CTRL                   ~0
0145 #define PIXCONF_0                   (0x64 << 8)
0146 #define PIXCONF_2                   (0xF3 << 24)
0147 #define PIXCONF_1                   (0xF0 << 16)
0148 #define MN_MASK                     0x3FF03FF
0149 #define P_OR                        (0x7 << 4)
0150 #define DAC_BIT                     (1 << 16)
0151 #define INTERLACE_BIT               (1 << 7)
0152 #define IER_MASK                    (3 << 13)
0153 #define IMR_MASK                    (3 << 13)
0154
0155 /* Power Management */
0156 #define DPMS_MASK                   0xF0000
0157 #define POWERON                     0x00000
0158 #define STANDBY                     0x20000
0159 #define SUSPEND                     0x80000
0160 #define POWERDOWN                   0xA0000
0161 #define EMR_MASK                    ~0x3F
0162 #define FW_BLC_MASK                 ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
0163
0164 /* Ringbuffer */
0165 #define RBUFFER_START_MASK          0xFFFFF000
0166 #define RBUFFER_SIZE_MASK           0x001FF000
0167 #define RBUFFER_HEAD_MASK           0x001FFFFC
0168 #define RBUFFER_TAIL_MASK           0x001FFFF8
0169
0170 /* Video Timings */
0171 #define REF_FREQ                    24000000
0172 #define TARGET_N_MAX                30
0173
0174 #define MAX_PIXELCLOCK              230000000
0175 #define MIN_PIXELCLOCK               15000000
0176 #define VFMAX                       60
0177 #define VFMIN                       60
0178 #define HFMAX                       30000
0179 #define HFMIN                       29000
0180
0181 /* Cursor */
0182 #define CURSOR_ENABLE_MASK          0x1000
0183 #define CURSOR_MODE_64_TRANS        4
0184 #define CURSOR_MODE_64_XOR      5
0185 #define CURSOR_MODE_64_3C       6
0186 #define COORD_INACTIVE              0
0187 #define COORD_ACTIVE                (1 << 4)
0188 #define EXTENDED_PALETTE        1
0189
0190 /* AGP Memory Types*/
0191 #define AGP_NORMAL_MEMORY           0
0192 #define AGP_DCACHE_MEMORY       1
0193 #define AGP_PHYSICAL_MEMORY         2
0194
0195 /* Allocated resource Flags */
0196 #define FRAMEBUFFER_REQ             1
0197 #define MMIO_REQ                    2
0198 #define PCI_DEVICE_ENABLED          4
0199 #define HAS_FONTCACHE               8
0200
0201 /* driver flags */
0202 #define HAS_ACCELERATION            2
0203 #define ALWAYS_SYNC                 4
0204 #define LOCKUP                      8
0205
0206 struct gtt_data {
0207     struct agp_memory *i810_fb_memory;
0208     struct agp_memory *i810_cursor_memory;
0209 };
0210
0211 struct mode_registers {
0212     u32 pixclock, M, N, P;
0213     u8 cr00, cr01, cr02, cr03;
0214     u8 cr04, cr05, cr06, cr07;
0215     u8 cr09, cr10, cr11, cr12;
0216     u8 cr13, cr15, cr16, cr30;
0217     u8 cr31, cr32, cr33, cr35, cr39;
0218     u32 bpp8_100, bpp16_100;
0219     u32 bpp24_100, bpp8_133;
0220     u32 bpp16_133, bpp24_133;
0221     u8 msr;
0222 };
0223
0224 struct heap_data {
0225         unsigned long physical;
0226     __u8 __iomem *virtual;
0227     u32 offset;
0228     u32 size;
0229 };
0230
0231 struct state_registers {
0232     u32 dclk_1d, dclk_2d, dclk_0ds;
0233     u32 pixconf, fw_blc, pgtbl_ctl;
0234     u32 fence0, hws_pga, dplystas;
0235     u16 bltcntl, hwstam, ier, iir, imr;
0236     u8 cr00, cr01, cr02, cr03, cr04;
0237     u8 cr05, cr06, cr07, cr08, cr09;
0238     u8 cr10, cr11, cr12, cr13, cr14;
0239     u8 cr15, cr16, cr17, cr80, gr10;
0240     u8 cr30, cr31, cr32, cr33, cr35;
0241     u8 cr39, cr41, cr70, sr01, msr;
0242 };
0243
0244 struct i810fb_par;
0245
0246 struct i810fb_i2c_chan {
0247     struct i810fb_par *par;
0248     struct i2c_adapter adapter;
0249     struct i2c_algo_bit_data algo;
0250     unsigned long ddc_base;
0251 };
0252
0253 struct i810fb_par {
0254     struct mode_registers    regs;
0255     struct state_registers   hw_state;
0256     struct gtt_data          i810_gtt;
0257     struct fb_ops            i810fb_ops;
0258     struct pci_dev           *dev;
0259     struct heap_data         aperture;
0260     struct heap_data         fb;
0261     struct heap_data         iring;
0262     struct heap_data         cursor_heap;
0263     struct vgastate          state;
0264     struct i810fb_i2c_chan   chan[3];
0265     struct mutex         open_lock;
0266     unsigned int         use_count;
0267     u32 pseudo_palette[16];
0268     unsigned long mmio_start_phys;
0269     u8 __iomem *mmio_start_virtual;
0270     u8 *edid;
0271     u32 pitch;
0272     u32 pixconf;
0273     u32 watermark;
0274     u32 mem_freq;
0275     u32 res_flags;
0276     u32 dev_flags;
0277     u32 cur_tail;
0278     u32 depth;
0279     u32 blit_bpp;
0280     u32 ovract;
0281     u32 cur_state;
0282     u32 ddc_num;
0283     int wc_cookie;
0284     u16 bltcntl;
0285     u8 interlace;
0286 };
0287
0288 /*
0289  * Register I/O
0290  */
0291 #define i810_readb(where, mmio) readb(mmio + where)
0292 #define i810_readw(where, mmio) readw(mmio + where)
0293 #define i810_readl(where, mmio) readl(mmio + where)
0294 #define i810_writeb(where, mmio, val) writeb(val, mmio + where)
0295 #define i810_writew(where, mmio, val) writew(val, mmio + where)
0296 #define i810_writel(where, mmio, val) writel(val, mmio + where)
0297
0298 #endif /* __I810_H__ */