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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * i740fb - framebuffer driver for Intel740
0004  * Copyright (c) 2011 Ondrej Zary
0005  *
0006  * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru>
0007  * which was partially based on:
0008  *  VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org>
0009  *  and Petr Vandrovec <VANDROVE@vc.cvut.cz>
0010  *  i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
0011  *  Texas.
0012  *  i740fb by Patrick LERDA, v0.9
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/kernel.h>
0017 #include <linux/errno.h>
0018 #include <linux/string.h>
0019 #include <linux/mm.h>
0020 #include <linux/slab.h>
0021 #include <linux/delay.h>
0022 #include <linux/fb.h>
0023 #include <linux/init.h>
0024 #include <linux/pci.h>
0025 #include <linux/pci_ids.h>
0026 #include <linux/i2c.h>
0027 #include <linux/i2c-algo-bit.h>
0028 #include <linux/console.h>
0029 #include <video/vga.h>
0030 
0031 #include "i740_reg.h"
0032 
0033 static char *mode_option;
0034 static int mtrr = 1;
0035 
0036 struct i740fb_par {
0037     unsigned char __iomem *regs;
0038     bool has_sgram;
0039     int wc_cookie;
0040     bool ddc_registered;
0041     struct i2c_adapter ddc_adapter;
0042     struct i2c_algo_bit_data ddc_algo;
0043     u32 pseudo_palette[16];
0044     struct mutex open_lock;
0045     unsigned int ref_count;
0046 
0047     u8 crtc[VGA_CRT_C];
0048     u8 atc[VGA_ATT_C];
0049     u8 gdc[VGA_GFX_C];
0050     u8 seq[VGA_SEQ_C];
0051     u8 misc;
0052     u8 vss;
0053 
0054     /* i740 specific registers */
0055     u8 display_cntl;
0056     u8 pixelpipe_cfg0;
0057     u8 pixelpipe_cfg1;
0058     u8 pixelpipe_cfg2;
0059     u8 video_clk2_m;
0060     u8 video_clk2_n;
0061     u8 video_clk2_mn_msbs;
0062     u8 video_clk2_div_sel;
0063     u8 pll_cntl;
0064     u8 address_mapping;
0065     u8 io_cntl;
0066     u8 bitblt_cntl;
0067     u8 ext_vert_total;
0068     u8 ext_vert_disp_end;
0069     u8 ext_vert_sync_start;
0070     u8 ext_vert_blank_start;
0071     u8 ext_horiz_total;
0072     u8 ext_horiz_blank;
0073     u8 ext_offset;
0074     u8 interlace_cntl;
0075     u32 lmi_fifo_watermark;
0076     u8 ext_start_addr;
0077     u8 ext_start_addr_hi;
0078 };
0079 
0080 #define DACSPEED8   203
0081 #define DACSPEED16  163
0082 #define DACSPEED24_SG   136
0083 #define DACSPEED24_SD   128
0084 #define DACSPEED32  86
0085 
0086 static const struct fb_fix_screeninfo i740fb_fix = {
0087     .id =       "i740fb",
0088     .type =     FB_TYPE_PACKED_PIXELS,
0089     .visual =   FB_VISUAL_TRUECOLOR,
0090     .xpanstep = 8,
0091     .ypanstep = 1,
0092     .accel =    FB_ACCEL_NONE,
0093 };
0094 
0095 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
0096 {
0097     vga_mm_w(par->regs, port, val);
0098 }
0099 static inline u8 i740inb(struct i740fb_par *par, u16 port)
0100 {
0101     return vga_mm_r(par->regs, port);
0102 }
0103 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
0104 {
0105     vga_mm_w_fast(par->regs, port, reg, val);
0106 }
0107 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
0108 {
0109     vga_mm_w(par->regs, port, reg);
0110     return vga_mm_r(par->regs, port+1);
0111 }
0112 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
0113                    u8 val, u8 mask)
0114 {
0115     vga_mm_w_fast(par->regs, port, reg, (val & mask)
0116         | (i740inreg(par, port, reg) & ~mask));
0117 }
0118 
0119 #define REG_DDC_DRIVE   0x62
0120 #define REG_DDC_STATE   0x63
0121 #define DDC_SCL     (1 << 3)
0122 #define DDC_SDA     (1 << 2)
0123 
0124 static void i740fb_ddc_setscl(void *data, int val)
0125 {
0126     struct i740fb_par *par = data;
0127 
0128     i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
0129     i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
0130 }
0131 
0132 static void i740fb_ddc_setsda(void *data, int val)
0133 {
0134     struct i740fb_par *par = data;
0135 
0136     i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
0137     i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
0138 }
0139 
0140 static int i740fb_ddc_getscl(void *data)
0141 {
0142     struct i740fb_par *par = data;
0143 
0144     i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
0145 
0146     return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
0147 }
0148 
0149 static int i740fb_ddc_getsda(void *data)
0150 {
0151     struct i740fb_par *par = data;
0152 
0153     i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
0154 
0155     return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
0156 }
0157 
0158 static int i740fb_setup_ddc_bus(struct fb_info *info)
0159 {
0160     struct i740fb_par *par = info->par;
0161 
0162     strscpy(par->ddc_adapter.name, info->fix.id,
0163         sizeof(par->ddc_adapter.name));
0164     par->ddc_adapter.owner      = THIS_MODULE;
0165     par->ddc_adapter.class      = I2C_CLASS_DDC;
0166     par->ddc_adapter.algo_data  = &par->ddc_algo;
0167     par->ddc_adapter.dev.parent = info->device;
0168     par->ddc_algo.setsda        = i740fb_ddc_setsda;
0169     par->ddc_algo.setscl        = i740fb_ddc_setscl;
0170     par->ddc_algo.getsda        = i740fb_ddc_getsda;
0171     par->ddc_algo.getscl        = i740fb_ddc_getscl;
0172     par->ddc_algo.udelay        = 10;
0173     par->ddc_algo.timeout       = 20;
0174     par->ddc_algo.data      = par;
0175 
0176     i2c_set_adapdata(&par->ddc_adapter, par);
0177 
0178     return i2c_bit_add_bus(&par->ddc_adapter);
0179 }
0180 
0181 static int i740fb_open(struct fb_info *info, int user)
0182 {
0183     struct i740fb_par *par = info->par;
0184 
0185     mutex_lock(&(par->open_lock));
0186     par->ref_count++;
0187     mutex_unlock(&(par->open_lock));
0188 
0189     return 0;
0190 }
0191 
0192 static int i740fb_release(struct fb_info *info, int user)
0193 {
0194     struct i740fb_par *par = info->par;
0195 
0196     mutex_lock(&(par->open_lock));
0197     if (par->ref_count == 0) {
0198         fb_err(info, "release called with zero refcount\n");
0199         mutex_unlock(&(par->open_lock));
0200         return -EINVAL;
0201     }
0202 
0203     par->ref_count--;
0204     mutex_unlock(&(par->open_lock));
0205 
0206     return 0;
0207 }
0208 
0209 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
0210 {
0211     /*
0212      * Would like to calculate these values automatically, but a generic
0213      * algorithm does not seem possible.  Note: These FIFO water mark
0214      * values were tested on several cards and seem to eliminate the
0215      * all of the snow and vertical banding, but fine adjustments will
0216      * probably be required for other cards.
0217      */
0218 
0219     u32 wm;
0220 
0221     switch (bpp) {
0222     case 8:
0223         if  (freq > 200)
0224             wm = 0x18120000;
0225         else if (freq > 175)
0226             wm = 0x16110000;
0227         else if (freq > 135)
0228             wm = 0x120E0000;
0229         else
0230             wm = 0x100D0000;
0231         break;
0232     case 15:
0233     case 16:
0234         if (par->has_sgram) {
0235             if  (freq > 140)
0236                 wm = 0x2C1D0000;
0237             else if (freq > 120)
0238                 wm = 0x2C180000;
0239             else if (freq > 100)
0240                 wm = 0x24160000;
0241             else if (freq >  90)
0242                 wm = 0x18120000;
0243             else if (freq >  50)
0244                 wm = 0x16110000;
0245             else if (freq >  32)
0246                 wm = 0x13100000;
0247             else
0248                 wm = 0x120E0000;
0249         } else {
0250             if  (freq > 160)
0251                 wm = 0x28200000;
0252             else if (freq > 140)
0253                 wm = 0x2A1E0000;
0254             else if (freq > 130)
0255                 wm = 0x2B1A0000;
0256             else if (freq > 120)
0257                 wm = 0x2C180000;
0258             else if (freq > 100)
0259                 wm = 0x24180000;
0260             else if (freq >  90)
0261                 wm = 0x18120000;
0262             else if (freq >  50)
0263                 wm = 0x16110000;
0264             else if (freq >  32)
0265                 wm = 0x13100000;
0266             else
0267                 wm = 0x120E0000;
0268         }
0269         break;
0270     case 24:
0271         if (par->has_sgram) {
0272             if  (freq > 130)
0273                 wm = 0x31200000;
0274             else if (freq > 120)
0275                 wm = 0x2E200000;
0276             else if (freq > 100)
0277                 wm = 0x2C1D0000;
0278             else if (freq >  80)
0279                 wm = 0x25180000;
0280             else if (freq >  64)
0281                 wm = 0x24160000;
0282             else if (freq >  49)
0283                 wm = 0x18120000;
0284             else if (freq >  32)
0285                 wm = 0x16110000;
0286             else
0287                 wm = 0x13100000;
0288         } else {
0289             if  (freq > 120)
0290                 wm = 0x311F0000;
0291             else if (freq > 100)
0292                 wm = 0x2C1D0000;
0293             else if (freq >  80)
0294                 wm = 0x25180000;
0295             else if (freq >  64)
0296                 wm = 0x24160000;
0297             else if (freq >  49)
0298                 wm = 0x18120000;
0299             else if (freq >  32)
0300                 wm = 0x16110000;
0301             else
0302                 wm = 0x13100000;
0303         }
0304         break;
0305     case 32:
0306         if (par->has_sgram) {
0307             if  (freq >  80)
0308                 wm = 0x2A200000;
0309             else if (freq >  60)
0310                 wm = 0x281A0000;
0311             else if (freq >  49)
0312                 wm = 0x25180000;
0313             else if (freq >  32)
0314                 wm = 0x18120000;
0315             else
0316                 wm = 0x16110000;
0317         } else {
0318             if  (freq >  80)
0319                 wm = 0x29200000;
0320             else if (freq >  60)
0321                 wm = 0x281A0000;
0322             else if (freq >  49)
0323                 wm = 0x25180000;
0324             else if (freq >  32)
0325                 wm = 0x18120000;
0326             else
0327                 wm = 0x16110000;
0328         }
0329         break;
0330     }
0331 
0332     return wm;
0333 }
0334 
0335 /* clock calculation from i740fb by Patrick LERDA */
0336 
0337 #define I740_RFREQ      1000000
0338 #define TARGET_MAX_N        30
0339 #define I740_FFIX       (1 << 8)
0340 #define I740_RFREQ_FIX      (I740_RFREQ / I740_FFIX)
0341 #define I740_REF_FREQ       (6667 * I740_FFIX / 100)    /* 66.67 MHz */
0342 #define I740_MAX_VCO_FREQ   (450 * I740_FFIX)       /* 450 MHz */
0343 
0344 static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
0345 {
0346     const u32 err_max    = freq / (200  * I740_RFREQ / I740_FFIX);
0347     const u32 err_target = freq / (1000 * I740_RFREQ / I740_FFIX);
0348     u32 err_best = 512 * I740_FFIX;
0349     u32 f_err, f_vco;
0350     int m_best = 0, n_best = 0, p_best = 0;
0351     int m, n;
0352 
0353     p_best = min(15, ilog2(I740_MAX_VCO_FREQ / (freq / I740_RFREQ_FIX)));
0354     f_vco = (freq * (1 << p_best)) / I740_RFREQ_FIX;
0355     freq = freq / I740_RFREQ_FIX;
0356 
0357     n = 2;
0358     do {
0359         n++;
0360         m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
0361 
0362         if (m < 3)
0363             m = 3;
0364 
0365         {
0366             u32 f_out = (((m * I740_REF_FREQ * 4)
0367                  / n) + ((1 << p_best) / 2)) / (1 << p_best);
0368 
0369             f_err = (freq - f_out);
0370 
0371             if (abs(f_err) < err_max) {
0372                 m_best = m;
0373                 n_best = n;
0374                 err_best = f_err;
0375             }
0376         }
0377     } while ((abs(f_err) >= err_target) &&
0378          ((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
0379 
0380     if (abs(f_err) < err_target) {
0381         m_best = m;
0382         n_best = n;
0383     }
0384 
0385     par->video_clk2_m = (m_best - 2) & 0xFF;
0386     par->video_clk2_n = (n_best - 2) & 0xFF;
0387     par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
0388                  | (((m_best - 2) >> 8) & VCO_M_MSBS));
0389     par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1);
0390 }
0391 
0392 static int i740fb_decode_var(const struct fb_var_screeninfo *var,
0393                  struct i740fb_par *par, struct fb_info *info)
0394 {
0395     /*
0396      * Get the video params out of 'var'.
0397      * If a value doesn't fit, round it up, if it's too big, return -EINVAL.
0398      */
0399 
0400     u32 xres, right, hslen, left, xtotal;
0401     u32 yres, lower, vslen, upper, ytotal;
0402     u32 vxres, xoffset, vyres, yoffset;
0403     u32 bpp, base, dacspeed24, mem, freq;
0404     u8 r7;
0405     int i;
0406 
0407     dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
0408           var->xres, var->yres, var->xres_virtual, var->xres_virtual);
0409     dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
0410           var->xoffset, var->yoffset, var->bits_per_pixel,
0411           var->grayscale);
0412     dev_dbg(info->device, " activate: %i, nonstd: %i, vmode: %i\n",
0413           var->activate, var->nonstd, var->vmode);
0414     dev_dbg(info->device, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
0415           var->pixclock, var->hsync_len, var->vsync_len);
0416     dev_dbg(info->device, " left: %i, right: %i, up:%i, lower:%i\n",
0417           var->left_margin, var->right_margin, var->upper_margin,
0418           var->lower_margin);
0419 
0420 
0421     bpp = var->bits_per_pixel;
0422     switch (bpp) {
0423     case 1 ... 8:
0424         bpp = 8;
0425         if ((1000000 / var->pixclock) > DACSPEED8) {
0426             dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
0427                 1000000 / var->pixclock, DACSPEED8);
0428             return -EINVAL;
0429         }
0430         break;
0431     case 9 ... 15:
0432         bpp = 15;
0433         fallthrough;
0434     case 16:
0435         if ((1000000 / var->pixclock) > DACSPEED16) {
0436             dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
0437                 1000000 / var->pixclock, DACSPEED16);
0438             return -EINVAL;
0439         }
0440         break;
0441     case 17 ... 24:
0442         bpp = 24;
0443         dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
0444         if ((1000000 / var->pixclock) > dacspeed24) {
0445             dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
0446                 1000000 / var->pixclock, dacspeed24);
0447             return -EINVAL;
0448         }
0449         break;
0450     case 25 ... 32:
0451         bpp = 32;
0452         if ((1000000 / var->pixclock) > DACSPEED32) {
0453             dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
0454                 1000000 / var->pixclock, DACSPEED32);
0455             return -EINVAL;
0456         }
0457         break;
0458     default:
0459         return -EINVAL;
0460     }
0461 
0462     xres = ALIGN(var->xres, 8);
0463     vxres = ALIGN(var->xres_virtual, 16);
0464     if (vxres < xres)
0465         vxres = xres;
0466 
0467     xoffset = ALIGN(var->xoffset, 8);
0468     if (xres + xoffset > vxres)
0469         xoffset = vxres - xres;
0470 
0471     left = ALIGN(var->left_margin, 8);
0472     right = ALIGN(var->right_margin, 8);
0473     hslen = ALIGN(var->hsync_len, 8);
0474 
0475     yres = var->yres;
0476     vyres = var->yres_virtual;
0477     if (yres > vyres)
0478         vyres = yres;
0479 
0480     yoffset = var->yoffset;
0481     if (yres + yoffset > vyres)
0482         yoffset = vyres - yres;
0483 
0484     lower = var->lower_margin;
0485     vslen = var->vsync_len;
0486     upper = var->upper_margin;
0487 
0488     mem = vxres * vyres * ((bpp + 1) / 8);
0489     if (mem > info->screen_size) {
0490         dev_err(info->device, "not enough video memory (%d KB requested, %ld KB available)\n",
0491             mem >> 10, info->screen_size >> 10);
0492         return -ENOMEM;
0493     }
0494 
0495     if (yoffset + yres > vyres)
0496         yoffset = vyres - yres;
0497 
0498     xtotal = xres + right + hslen + left;
0499     ytotal = yres + lower + vslen + upper;
0500 
0501     par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
0502     par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
0503     par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
0504     par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
0505     par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
0506         | ((((xres + right + hslen) >> 3) & 0x20) << 2);
0507     par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
0508         | 0x80;
0509 
0510     par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
0511 
0512     r7 = 0x10;  /* disable linecompare */
0513     if (ytotal & 0x100)
0514         r7 |= 0x01;
0515     if (ytotal & 0x200)
0516         r7 |= 0x20;
0517 
0518     par->crtc[VGA_CRTC_PRESET_ROW] = 0;
0519     par->crtc[VGA_CRTC_MAX_SCAN] = 0x40;    /* 1 scanline, no linecmp */
0520     if (var->vmode & FB_VMODE_DOUBLE)
0521         par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
0522     par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
0523     par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
0524     par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
0525     par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
0526     par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
0527     if ((yres-1) & 0x100)
0528         r7 |= 0x02;
0529     if ((yres-1) & 0x200)
0530         r7 |= 0x40;
0531 
0532     par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
0533     par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
0534     if ((yres + lower - 1) & 0x100)
0535         r7 |= 0x0C;
0536     if ((yres + lower - 1) & 0x200) {
0537         par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
0538         r7 |= 0x80;
0539     }
0540 
0541     /* disabled IRQ */
0542     par->crtc[VGA_CRTC_V_SYNC_END] =
0543         ((yres + lower - 1 + vslen) & 0x0F) & ~0x10;
0544     /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
0545     par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
0546 
0547     par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
0548     par->crtc[VGA_CRTC_MODE] = 0xC3 ;
0549     par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
0550     par->crtc[VGA_CRTC_OVERFLOW] = r7;
0551 
0552     par->vss = 0x00;    /* 3DA */
0553 
0554     for (i = 0x00; i < 0x10; i++)
0555         par->atc[i] = i;
0556     par->atc[VGA_ATC_MODE] = 0x81;
0557     par->atc[VGA_ATC_OVERSCAN] = 0x00;  /* 0 for EGA, 0xFF for VGA */
0558     par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
0559     par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
0560 
0561     par->misc = 0xC3;
0562     if (var->sync & FB_SYNC_HOR_HIGH_ACT)
0563         par->misc &= ~0x40;
0564     if (var->sync & FB_SYNC_VERT_HIGH_ACT)
0565         par->misc &= ~0x80;
0566 
0567     par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
0568     par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
0569     par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
0570     par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
0571 
0572     par->gdc[VGA_GFX_SR_VALUE] = 0x00;
0573     par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
0574     par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
0575     par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
0576     par->gdc[VGA_GFX_PLANE_READ] = 0;
0577     par->gdc[VGA_GFX_MODE] = 0x02;
0578     par->gdc[VGA_GFX_MISC] = 0x05;
0579     par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
0580     par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
0581 
0582     base = (yoffset * vxres + (xoffset & ~7)) >> 2;
0583     switch (bpp) {
0584     case 8:
0585         par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
0586         par->ext_offset = vxres >> 11;
0587         par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
0588         par->bitblt_cntl = COLEXP_8BPP;
0589         break;
0590     case 15: /* 0rrrrrgg gggbbbbb */
0591     case 16: /* rrrrrggg gggbbbbb */
0592         par->pixelpipe_cfg1 = (var->green.length == 6) ?
0593             DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
0594         par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
0595         par->ext_offset = vxres >> 10;
0596         par->bitblt_cntl = COLEXP_16BPP;
0597         base *= 2;
0598         break;
0599     case 24:
0600         par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
0601         par->ext_offset = (vxres * 3) >> 11;
0602         par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
0603         par->bitblt_cntl = COLEXP_24BPP;
0604         base &= 0xFFFFFFFE; /* ...ignore the last bit. */
0605         base *= 3;
0606         break;
0607     case 32:
0608         par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
0609         par->ext_offset = vxres >> 9;
0610         par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
0611         par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
0612         base *= 4;
0613         break;
0614     }
0615 
0616     par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
0617     par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
0618     par->ext_start_addr =
0619         ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
0620     par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
0621 
0622     par->pixelpipe_cfg0 = DAC_8_BIT;
0623 
0624     par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
0625     par->io_cntl = EXTENDED_CRTC_CNTL;
0626     par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
0627     par->display_cntl = HIRES_MODE;
0628 
0629     /* Set the MCLK freq */
0630     par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
0631 
0632     /* Calculate the extended CRTC regs */
0633     par->ext_vert_total = (ytotal - 2) >> 8;
0634     par->ext_vert_disp_end = (yres - 1) >> 8;
0635     par->ext_vert_sync_start = (yres + lower) >> 8;
0636     par->ext_vert_blank_start = (yres + lower) >> 8;
0637     par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
0638     par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
0639 
0640     par->interlace_cntl = INTERLACE_DISABLE;
0641 
0642     /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
0643     par->atc[VGA_ATC_OVERSCAN] = 0;
0644 
0645     /* Calculate VCLK that most closely matches the requested dot clock */
0646     freq = (((u32)1e9) / var->pixclock) * (u32)(1e3);
0647     if (freq < I740_RFREQ_FIX) {
0648         fb_dbg(info, "invalid pixclock\n");
0649         freq = I740_RFREQ_FIX;
0650     }
0651     i740_calc_vclk(freq, par);
0652 
0653     /* Since we program the clocks ourselves, always use VCLK2. */
0654     par->misc |= 0x0C;
0655 
0656     /* Calculate the FIFO Watermark and Burst Length. */
0657     par->lmi_fifo_watermark =
0658         i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
0659 
0660     return 0;
0661 }
0662 
0663 static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
0664 {
0665     if (!var->pixclock)
0666         return -EINVAL;
0667 
0668     switch (var->bits_per_pixel) {
0669     case 8:
0670         var->red.offset = var->green.offset = var->blue.offset = 0;
0671         var->red.length = var->green.length = var->blue.length = 8;
0672         break;
0673     case 16:
0674         switch (var->green.length) {
0675         default:
0676         case 5:
0677             var->red.offset = 10;
0678             var->green.offset = 5;
0679             var->blue.offset = 0;
0680             var->red.length = 5;
0681             var->green.length = 5;
0682             var->blue.length = 5;
0683             break;
0684         case 6:
0685             var->red.offset = 11;
0686             var->green.offset = 5;
0687             var->blue.offset = 0;
0688             var->red.length = var->blue.length = 5;
0689             break;
0690         }
0691         break;
0692     case 24:
0693         var->red.offset = 16;
0694         var->green.offset = 8;
0695         var->blue.offset = 0;
0696         var->red.length = var->green.length = var->blue.length = 8;
0697         break;
0698     case 32:
0699         var->transp.offset = 24;
0700         var->red.offset = 16;
0701         var->green.offset = 8;
0702         var->blue.offset = 0;
0703         var->transp.length = 8;
0704         var->red.length = var->green.length = var->blue.length = 8;
0705         break;
0706     default:
0707         return -EINVAL;
0708     }
0709 
0710     if (var->xres > var->xres_virtual)
0711         var->xres_virtual = var->xres;
0712 
0713     if (var->yres > var->yres_virtual)
0714         var->yres_virtual = var->yres;
0715 
0716     if (info->monspecs.hfmax && info->monspecs.vfmax &&
0717         info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
0718         return -EINVAL;
0719 
0720     return 0;
0721 }
0722 
0723 static void vga_protect(struct i740fb_par *par)
0724 {
0725     /* disable the display */
0726     i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
0727 
0728     i740inb(par, 0x3DA);
0729     i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */
0730 }
0731 
0732 static void vga_unprotect(struct i740fb_par *par)
0733 {
0734     /* reenable display */
0735     i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
0736 
0737     i740inb(par, 0x3DA);
0738     i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */
0739 }
0740 
0741 static int i740fb_set_par(struct fb_info *info)
0742 {
0743     struct i740fb_par *par = info->par;
0744     u32 itemp;
0745     int i;
0746 
0747     i = i740fb_decode_var(&info->var, par, info);
0748     if (i)
0749         return i;
0750 
0751     memset_io(info->screen_base, 0, info->screen_size);
0752 
0753     vga_protect(par);
0754 
0755     i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
0756 
0757     mdelay(1);
0758 
0759     i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
0760     i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
0761     i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
0762     i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
0763 
0764     i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
0765             par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
0766 
0767     i740inb(par, 0x3DA);
0768     i740outb(par, 0x3C0, 0x00);
0769 
0770     /* update misc output register */
0771     i740outb(par, VGA_MIS_W, par->misc | 0x01);
0772 
0773     /* synchronous reset on */
0774     i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
0775     /* write sequencer registers */
0776     i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
0777             par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
0778     for (i = 2; i < VGA_SEQ_C; i++)
0779         i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
0780 
0781     /* synchronous reset off */
0782     i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
0783 
0784     /* deprotect CRT registers 0-7 */
0785     i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
0786             par->crtc[VGA_CRTC_V_SYNC_END]);
0787 
0788     /* write CRT registers */
0789     for (i = 0; i < VGA_CRT_C; i++)
0790         i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
0791 
0792     /* write graphics controller registers */
0793     for (i = 0; i < VGA_GFX_C; i++)
0794         i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
0795 
0796     /* write attribute controller registers */
0797     for (i = 0; i < VGA_ATT_C; i++) {
0798         i740inb(par, VGA_IS1_RC);       /* reset flip-flop */
0799         i740outb(par, VGA_ATT_IW, i);
0800         i740outb(par, VGA_ATT_IW, par->atc[i]);
0801     }
0802 
0803     i740inb(par, VGA_IS1_RC);
0804     i740outb(par, VGA_ATT_IW, 0x20);
0805 
0806     i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
0807     i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
0808     i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
0809             par->ext_vert_sync_start);
0810     i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
0811             par->ext_vert_blank_start);
0812     i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
0813     i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
0814     i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
0815     i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
0816     i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
0817 
0818     i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
0819             par->interlace_cntl, INTERLACE_ENABLE);
0820     i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
0821     i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
0822     i740outreg_mask(par, XRX, DISPLAY_CNTL,
0823             par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
0824     i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
0825     i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
0826 
0827     i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
0828 
0829     i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
0830             par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
0831 
0832     itemp = readl(par->regs + FWATER_BLC);
0833     itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
0834     itemp |= par->lmi_fifo_watermark;
0835     writel(itemp, par->regs + FWATER_BLC);
0836 
0837     i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
0838 
0839     i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
0840     i740outreg_mask(par, XRX, IO_CTNL,
0841             par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
0842 
0843     if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
0844         i740outb(par, VGA_PEL_MSK, 0xFF);
0845         i740outb(par, VGA_PEL_IW, 0x00);
0846         for (i = 0; i < 256; i++) {
0847             itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
0848             i740outb(par, VGA_PEL_D, itemp);
0849             i740outb(par, VGA_PEL_D, itemp);
0850             i740outb(par, VGA_PEL_D, itemp);
0851         }
0852     }
0853 
0854     /* Wait for screen to stabilize. */
0855     mdelay(50);
0856     vga_unprotect(par);
0857 
0858     info->fix.line_length =
0859             info->var.xres_virtual * info->var.bits_per_pixel / 8;
0860     if (info->var.bits_per_pixel == 8)
0861         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
0862     else
0863         info->fix.visual = FB_VISUAL_TRUECOLOR;
0864 
0865     return 0;
0866 }
0867 
0868 static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
0869                unsigned blue, unsigned transp,
0870                struct fb_info *info)
0871 {
0872     u32 r, g, b;
0873 
0874     dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
0875         regno, red, green, blue, transp, info->var.bits_per_pixel);
0876 
0877     switch (info->fix.visual) {
0878     case FB_VISUAL_PSEUDOCOLOR:
0879         if (regno >= 256)
0880             return -EINVAL;
0881         i740outb(info->par, VGA_PEL_IW, regno);
0882         i740outb(info->par, VGA_PEL_D, red >> 8);
0883         i740outb(info->par, VGA_PEL_D, green >> 8);
0884         i740outb(info->par, VGA_PEL_D, blue >> 8);
0885         break;
0886     case FB_VISUAL_TRUECOLOR:
0887         if (regno >= 16)
0888             return -EINVAL;
0889         r = (red >> (16 - info->var.red.length))
0890             << info->var.red.offset;
0891         b = (blue >> (16 - info->var.blue.length))
0892             << info->var.blue.offset;
0893         g = (green >> (16 - info->var.green.length))
0894             << info->var.green.offset;
0895         ((u32 *) info->pseudo_palette)[regno] = r | g | b;
0896         break;
0897     default:
0898         return -EINVAL;
0899     }
0900 
0901     return 0;
0902 }
0903 
0904 static int i740fb_pan_display(struct fb_var_screeninfo *var,
0905                  struct fb_info *info)
0906 {
0907     struct i740fb_par *par = info->par;
0908     u32 base = (var->yoffset * info->var.xres_virtual
0909          + (var->xoffset & ~7)) >> 2;
0910 
0911     dev_dbg(info->device, "pan_display: xoffset: %i yoffset: %i base: %i\n",
0912         var->xoffset, var->yoffset, base);
0913 
0914     switch (info->var.bits_per_pixel) {
0915     case 8:
0916         break;
0917     case 15:
0918     case 16:
0919         base *= 2;
0920         break;
0921     case 24:
0922         /*
0923          * The last bit does not seem to have any effect on the start
0924          * address register in 24bpp mode, so...
0925          */
0926         base &= 0xFFFFFFFE; /* ...ignore the last bit. */
0927         base *= 3;
0928         break;
0929     case 32:
0930         base *= 4;
0931         break;
0932     }
0933 
0934     par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
0935     par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
0936     par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
0937     par->ext_start_addr =
0938             ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
0939 
0940     i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO,  base & 0x000000FF);
0941     i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
0942             (base & 0x0000FF00) >> 8);
0943     i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
0944             (base & 0x3FC00000) >> 22);
0945     i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
0946             ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
0947 
0948     return 0;
0949 }
0950 
0951 static int i740fb_blank(int blank_mode, struct fb_info *info)
0952 {
0953     struct i740fb_par *par = info->par;
0954 
0955     unsigned char SEQ01;
0956     int DPMSSyncSelect;
0957 
0958     switch (blank_mode) {
0959     case FB_BLANK_UNBLANK:
0960     case FB_BLANK_NORMAL:
0961         SEQ01 = 0x00;
0962         DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
0963         break;
0964     case FB_BLANK_VSYNC_SUSPEND:
0965         SEQ01 = 0x20;
0966         DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
0967         break;
0968     case FB_BLANK_HSYNC_SUSPEND:
0969         SEQ01 = 0x20;
0970         DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
0971         break;
0972     case FB_BLANK_POWERDOWN:
0973         SEQ01 = 0x20;
0974         DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
0975         break;
0976     default:
0977         return -EINVAL;
0978     }
0979     /* Turn the screen on/off */
0980     i740outb(par, SRX, 0x01);
0981     SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
0982     i740outb(par, SRX, 0x01);
0983     i740outb(par, SRX + 1, SEQ01);
0984 
0985     /* Set the DPMS mode */
0986     i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
0987 
0988     /* Let fbcon do a soft blank for us */
0989     return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
0990 }
0991 
0992 static const struct fb_ops i740fb_ops = {
0993     .owner      = THIS_MODULE,
0994     .fb_open    = i740fb_open,
0995     .fb_release = i740fb_release,
0996     .fb_check_var   = i740fb_check_var,
0997     .fb_set_par = i740fb_set_par,
0998     .fb_setcolreg   = i740fb_setcolreg,
0999     .fb_blank   = i740fb_blank,
1000     .fb_pan_display = i740fb_pan_display,
1001     .fb_fillrect    = cfb_fillrect,
1002     .fb_copyarea    = cfb_copyarea,
1003     .fb_imageblit   = cfb_imageblit,
1004 };
1005 
1006 /* ------------------------------------------------------------------------- */
1007 
1008 static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1009 {
1010     struct fb_info *info;
1011     struct i740fb_par *par;
1012     int ret, tmp;
1013     bool found = false;
1014     u8 *edid;
1015 
1016     info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
1017     if (!info)
1018         return -ENOMEM;
1019 
1020     par = info->par;
1021     mutex_init(&par->open_lock);
1022 
1023     info->var.activate = FB_ACTIVATE_NOW;
1024     info->var.bits_per_pixel = 8;
1025     info->fbops = &i740fb_ops;
1026     info->pseudo_palette = par->pseudo_palette;
1027 
1028     ret = pci_enable_device(dev);
1029     if (ret) {
1030         dev_err(info->device, "cannot enable PCI device\n");
1031         goto err_enable_device;
1032     }
1033 
1034     ret = pci_request_regions(dev, info->fix.id);
1035     if (ret) {
1036         dev_err(info->device, "error requesting regions\n");
1037         goto err_request_regions;
1038     }
1039 
1040     info->screen_base = pci_ioremap_wc_bar(dev, 0);
1041     if (!info->screen_base) {
1042         dev_err(info->device, "error remapping base\n");
1043         ret = -ENOMEM;
1044         goto err_ioremap_1;
1045     }
1046 
1047     par->regs = pci_ioremap_bar(dev, 1);
1048     if (!par->regs) {
1049         dev_err(info->device, "error remapping MMIO\n");
1050         ret = -ENOMEM;
1051         goto err_ioremap_2;
1052     }
1053 
1054     /* detect memory size */
1055     if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1056                             == DRAM_ROW_1_SDRAM)
1057         i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1058     else
1059         i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1060     info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1061     /* detect memory type */
1062     tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
1063     par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
1064                (tmp & DRAM_RAS_PRECHARGE));
1065 
1066     fb_info(info, "Intel740 on %s, %ld KB %s\n",
1067         pci_name(dev), info->screen_size >> 10,
1068         par->has_sgram ? "SGRAM" : "SDRAM");
1069 
1070     info->fix = i740fb_fix;
1071     info->fix.mmio_start = pci_resource_start(dev, 1);
1072     info->fix.mmio_len = pci_resource_len(dev, 1);
1073     info->fix.smem_start = pci_resource_start(dev, 0);
1074     info->fix.smem_len = info->screen_size;
1075     info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1076 
1077     if (i740fb_setup_ddc_bus(info) == 0) {
1078         par->ddc_registered = true;
1079         edid = fb_ddc_read(&par->ddc_adapter);
1080         if (edid) {
1081             fb_edid_to_monspecs(edid, &info->monspecs);
1082             kfree(edid);
1083             if (!info->monspecs.modedb)
1084                 dev_err(info->device,
1085                     "error getting mode database\n");
1086             else {
1087                 const struct fb_videomode *m;
1088 
1089                 fb_videomode_to_modelist(
1090                     info->monspecs.modedb,
1091                     info->monspecs.modedb_len,
1092                     &info->modelist);
1093                 m = fb_find_best_display(&info->monspecs,
1094                              &info->modelist);
1095                 if (m) {
1096                     fb_videomode_to_var(&info->var, m);
1097                     /* fill all other info->var's fields */
1098                     if (!i740fb_check_var(&info->var, info))
1099                         found = true;
1100                 }
1101             }
1102         }
1103     }
1104 
1105     if (!mode_option && !found)
1106         mode_option = "640x480-8@60";
1107 
1108     if (mode_option) {
1109         ret = fb_find_mode(&info->var, info, mode_option,
1110                    info->monspecs.modedb,
1111                    info->monspecs.modedb_len,
1112                    NULL, info->var.bits_per_pixel);
1113         if (!ret || ret == 4) {
1114             dev_err(info->device, "mode %s not found\n",
1115                 mode_option);
1116             ret = -EINVAL;
1117         }
1118     }
1119 
1120     fb_destroy_modedb(info->monspecs.modedb);
1121     info->monspecs.modedb = NULL;
1122 
1123     /* maximize virtual vertical size for fast scrolling */
1124     info->var.yres_virtual = info->fix.smem_len * 8 /
1125             (info->var.bits_per_pixel * info->var.xres_virtual);
1126 
1127     if (ret == -EINVAL)
1128         goto err_find_mode;
1129 
1130     ret = fb_alloc_cmap(&info->cmap, 256, 0);
1131     if (ret) {
1132         dev_err(info->device, "cannot allocate colormap\n");
1133         goto err_alloc_cmap;
1134     }
1135 
1136     ret = register_framebuffer(info);
1137     if (ret) {
1138         dev_err(info->device, "error registering framebuffer\n");
1139         goto err_reg_framebuffer;
1140     }
1141 
1142     fb_info(info, "%s frame buffer device\n", info->fix.id);
1143     pci_set_drvdata(dev, info);
1144     if (mtrr)
1145         par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1146                           info->fix.smem_len);
1147     return 0;
1148 
1149 err_reg_framebuffer:
1150     fb_dealloc_cmap(&info->cmap);
1151 err_alloc_cmap:
1152 err_find_mode:
1153     if (par->ddc_registered)
1154         i2c_del_adapter(&par->ddc_adapter);
1155     pci_iounmap(dev, par->regs);
1156 err_ioremap_2:
1157     pci_iounmap(dev, info->screen_base);
1158 err_ioremap_1:
1159     pci_release_regions(dev);
1160 err_request_regions:
1161 /*  pci_disable_device(dev); */
1162 err_enable_device:
1163     framebuffer_release(info);
1164     return ret;
1165 }
1166 
1167 static void i740fb_remove(struct pci_dev *dev)
1168 {
1169     struct fb_info *info = pci_get_drvdata(dev);
1170 
1171     if (info) {
1172         struct i740fb_par *par = info->par;
1173         arch_phys_wc_del(par->wc_cookie);
1174         unregister_framebuffer(info);
1175         fb_dealloc_cmap(&info->cmap);
1176         if (par->ddc_registered)
1177             i2c_del_adapter(&par->ddc_adapter);
1178         pci_iounmap(dev, par->regs);
1179         pci_iounmap(dev, info->screen_base);
1180         pci_release_regions(dev);
1181 /*      pci_disable_device(dev); */
1182         framebuffer_release(info);
1183     }
1184 }
1185 
1186 static int __maybe_unused i740fb_suspend(struct device *dev)
1187 {
1188     struct fb_info *info = dev_get_drvdata(dev);
1189     struct i740fb_par *par = info->par;
1190 
1191     console_lock();
1192     mutex_lock(&(par->open_lock));
1193 
1194     /* do nothing if framebuffer is not active */
1195     if (par->ref_count == 0) {
1196         mutex_unlock(&(par->open_lock));
1197         console_unlock();
1198         return 0;
1199     }
1200 
1201     fb_set_suspend(info, 1);
1202 
1203     mutex_unlock(&(par->open_lock));
1204     console_unlock();
1205 
1206     return 0;
1207 }
1208 
1209 static int __maybe_unused i740fb_resume(struct device *dev)
1210 {
1211     struct fb_info *info = dev_get_drvdata(dev);
1212     struct i740fb_par *par = info->par;
1213 
1214     console_lock();
1215     mutex_lock(&(par->open_lock));
1216 
1217     if (par->ref_count == 0)
1218         goto fail;
1219 
1220     i740fb_set_par(info);
1221     fb_set_suspend(info, 0);
1222 
1223 fail:
1224     mutex_unlock(&(par->open_lock));
1225     console_unlock();
1226     return 0;
1227 }
1228 
1229 static const struct dev_pm_ops i740fb_pm_ops = {
1230 #ifdef CONFIG_PM_SLEEP
1231     .suspend    = i740fb_suspend,
1232     .resume     = i740fb_resume,
1233     .freeze     = NULL,
1234     .thaw       = i740fb_resume,
1235     .poweroff   = i740fb_suspend,
1236     .restore    = i740fb_resume,
1237 #endif /* CONFIG_PM_SLEEP */
1238 };
1239 
1240 #define I740_ID_PCI 0x00d1
1241 #define I740_ID_AGP 0x7800
1242 
1243 static const struct pci_device_id i740fb_id_table[] = {
1244     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
1245     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
1246     { 0 }
1247 };
1248 MODULE_DEVICE_TABLE(pci, i740fb_id_table);
1249 
1250 static struct pci_driver i740fb_driver = {
1251     .name       = "i740fb",
1252     .id_table   = i740fb_id_table,
1253     .probe      = i740fb_probe,
1254     .remove     = i740fb_remove,
1255     .driver.pm  = &i740fb_pm_ops,
1256 };
1257 
1258 #ifndef MODULE
1259 static int  __init i740fb_setup(char *options)
1260 {
1261     char *opt;
1262 
1263     if (!options || !*options)
1264         return 0;
1265 
1266     while ((opt = strsep(&options, ",")) != NULL) {
1267         if (!*opt)
1268             continue;
1269         else if (!strncmp(opt, "mtrr:", 5))
1270             mtrr = simple_strtoul(opt + 5, NULL, 0);
1271         else
1272             mode_option = opt;
1273     }
1274 
1275     return 0;
1276 }
1277 #endif
1278 
1279 static int __init i740fb_init(void)
1280 {
1281 #ifndef MODULE
1282     char *option = NULL;
1283 
1284     if (fb_get_options("i740fb", &option))
1285         return -ENODEV;
1286     i740fb_setup(option);
1287 #endif
1288 
1289     return pci_register_driver(&i740fb_driver);
1290 }
1291 
1292 static void __exit i740fb_exit(void)
1293 {
1294     pci_unregister_driver(&i740fb_driver);
1295 }
1296 
1297 module_init(i740fb_init);
1298 module_exit(i740fb_exit);
1299 
1300 MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
1301 MODULE_LICENSE("GPL");
1302 MODULE_DESCRIPTION("fbdev driver for Intel740");
1303 
1304 module_param(mode_option, charp, 0444);
1305 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
1306 
1307 module_param(mtrr, int, 0444);
1308 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
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