fbdev/geode/lxfb.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Geode LX framebuffer driver
0003  *
0004  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
0005  * Copyright (c) 2008  Andres Salomon <dilinger@debian.org>
0006  */
0007 #ifndef _LXFB_H_
0008 #define _LXFB_H_
0009
0010 #include <linux/fb.h>
0011
0012 #define GP_REG_COUNT    (0x7c / 4)
0013 #define DC_REG_COUNT    (0xf0 / 4)
0014 #define VP_REG_COUNT    (0x158 / 8)
0015 #define FP_REG_COUNT    (0x60 / 8)
0016
0017 #define DC_PAL_COUNT    0x104
0018 #define DC_HFILT_COUNT  0x100
0019 #define DC_VFILT_COUNT  0x100
0020 #define VP_COEFF_SIZE   0x1000
0021 #define VP_PAL_COUNT    0x100
0022
0023 #define OUTPUT_CRT   0x01
0024 #define OUTPUT_PANEL 0x02
0025
0026 struct lxfb_par {
0027     int output;
0028
0029     void __iomem *gp_regs;
0030     void __iomem *dc_regs;
0031     void __iomem *vp_regs;
0032     int powered_down;
0033
0034     /* register state, for power mgmt functionality */
0035     struct {
0036         uint64_t padsel;
0037         uint64_t dotpll;
0038         uint64_t dfglcfg;
0039         uint64_t dcspare;
0040     } msr;
0041
0042     uint32_t gp[GP_REG_COUNT];
0043     uint32_t dc[DC_REG_COUNT];
0044     uint64_t vp[VP_REG_COUNT];
0045     uint64_t fp[FP_REG_COUNT];
0046
0047     uint32_t dc_pal[DC_PAL_COUNT];
0048     uint32_t vp_pal[VP_PAL_COUNT];
0049     uint32_t hcoeff[DC_HFILT_COUNT * 2];
0050     uint32_t vcoeff[DC_VFILT_COUNT];
0051     uint32_t vp_coeff[VP_COEFF_SIZE / 4];
0052 };
0053
0054 static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
0055 {
0056     return (((xres * (bpp >> 3)) + 7) & ~7);
0057 }
0058
0059 void lx_set_mode(struct fb_info *);
0060 unsigned int lx_framebuffer_size(void);
0061 int lx_blank_display(struct fb_info *, int);
0062 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
0063             unsigned int, unsigned int);
0064
0065 int lx_powerdown(struct fb_info *info);
0066 int lx_powerup(struct fb_info *info);
0067
0068 /* Graphics Processor registers (table 6-29 from the data book) */
0069 enum gp_registers {
0070     GP_DST_OFFSET = 0,
0071     GP_SRC_OFFSET,
0072     GP_STRIDE,
0073     GP_WID_HEIGHT,
0074
0075     GP_SRC_COLOR_FG,
0076     GP_SRC_COLOR_BG,
0077     GP_PAT_COLOR_0,
0078     GP_PAT_COLOR_1,
0079
0080     GP_PAT_COLOR_2,
0081     GP_PAT_COLOR_3,
0082     GP_PAT_COLOR_4,
0083     GP_PAT_COLOR_5,
0084
0085     GP_PAT_DATA_0,
0086     GP_PAT_DATA_1,
0087     GP_RASTER_MODE,
0088     GP_VECTOR_MODE,
0089
0090     GP_BLT_MODE,
0091     GP_BLT_STATUS,
0092     GP_HST_SRC,
0093     GP_BASE_OFFSET,
0094
0095     GP_CMD_TOP,
0096     GP_CMD_BOT,
0097     GP_CMD_READ,
0098     GP_CMD_WRITE,
0099
0100     GP_CH3_OFFSET,
0101     GP_CH3_MODE_STR,
0102     GP_CH3_WIDHI,
0103     GP_CH3_HSRC,
0104
0105     GP_LUT_INDEX,
0106     GP_LUT_DATA,
0107     GP_INT_CNTRL, /* 0x78 */
0108 };
0109
0110 #define GP_BLT_STATUS_CE        (1 << 4)    /* cmd buf empty */
0111 #define GP_BLT_STATUS_PB        (1 << 0)    /* primitive busy */
0112
0113
0114 /* Display Controller registers (table 6-47 from the data book) */
0115 enum dc_registers {
0116     DC_UNLOCK = 0,
0117     DC_GENERAL_CFG,
0118     DC_DISPLAY_CFG,
0119     DC_ARB_CFG,
0120
0121     DC_FB_ST_OFFSET,
0122     DC_CB_ST_OFFSET,
0123     DC_CURS_ST_OFFSET,
0124     DC_RSVD_0,
0125
0126     DC_VID_Y_ST_OFFSET,
0127     DC_VID_U_ST_OFFSET,
0128     DC_VID_V_ST_OFFSET,
0129     DC_DV_TOP,
0130
0131     DC_LINE_SIZE,
0132     DC_GFX_PITCH,
0133     DC_VID_YUV_PITCH,
0134     DC_RSVD_1,
0135
0136     DC_H_ACTIVE_TIMING,
0137     DC_H_BLANK_TIMING,
0138     DC_H_SYNC_TIMING,
0139     DC_RSVD_2,
0140
0141     DC_V_ACTIVE_TIMING,
0142     DC_V_BLANK_TIMING,
0143     DC_V_SYNC_TIMING,
0144     DC_FB_ACTIVE,
0145
0146     DC_CURSOR_X,
0147     DC_CURSOR_Y,
0148     DC_RSVD_3,
0149     DC_LINE_CNT,
0150
0151     DC_PAL_ADDRESS,
0152     DC_PAL_DATA,
0153     DC_DFIFO_DIAG,
0154     DC_CFIFO_DIAG,
0155
0156     DC_VID_DS_DELTA,
0157     DC_GLIU0_MEM_OFFSET,
0158     DC_DV_CTL,
0159     DC_DV_ACCESS,
0160
0161     DC_GFX_SCALE,
0162     DC_IRQ_FILT_CTL,
0163     DC_FILT_COEFF1,
0164     DC_FILT_COEFF2,
0165
0166     DC_VBI_EVEN_CTL,
0167     DC_VBI_ODD_CTL,
0168     DC_VBI_HOR,
0169     DC_VBI_LN_ODD,
0170
0171     DC_VBI_LN_EVEN,
0172     DC_VBI_PITCH,
0173     DC_CLR_KEY,
0174     DC_CLR_KEY_MASK,
0175
0176     DC_CLR_KEY_X,
0177     DC_CLR_KEY_Y,
0178     DC_IRQ,
0179     DC_RSVD_4,
0180
0181     DC_RSVD_5,
0182     DC_GENLK_CTL,
0183     DC_VID_EVEN_Y_ST_OFFSET,
0184     DC_VID_EVEN_U_ST_OFFSET,
0185
0186     DC_VID_EVEN_V_ST_OFFSET,
0187     DC_V_ACTIVE_EVEN_TIMING,
0188     DC_V_BLANK_EVEN_TIMING,
0189     DC_V_SYNC_EVEN_TIMING,  /* 0xec */
0190 };
0191
0192 #define DC_UNLOCK_LOCK          0x00000000
0193 #define DC_UNLOCK_UNLOCK        0x00004758  /* magic value */
0194
0195 #define DC_GENERAL_CFG_FDTY     (1 << 17)
0196 #define DC_GENERAL_CFG_DFHPEL_SHIFT (12)
0197 #define DC_GENERAL_CFG_DFHPSL_SHIFT (8)
0198 #define DC_GENERAL_CFG_VGAE     (1 << 7)
0199 #define DC_GENERAL_CFG_DECE     (1 << 6)
0200 #define DC_GENERAL_CFG_CMPE     (1 << 5)
0201 #define DC_GENERAL_CFG_VIDE     (1 << 3)
0202 #define DC_GENERAL_CFG_DFLE     (1 << 0)
0203
0204 #define DC_DISPLAY_CFG_VISL     (1 << 27)
0205 #define DC_DISPLAY_CFG_PALB     (1 << 25)
0206 #define DC_DISPLAY_CFG_DCEN     (1 << 24)
0207 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
0208 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
0209 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
0210 #define DC_DISPLAY_CFG_TRUP     (1 << 6)
0211 #define DC_DISPLAY_CFG_VDEN     (1 << 4)
0212 #define DC_DISPLAY_CFG_GDEN     (1 << 3)
0213 #define DC_DISPLAY_CFG_TGEN     (1 << 0)
0214
0215 #define DC_DV_TOP_DV_TOP_EN     (1 << 0)
0216
0217 #define DC_DV_CTL_DV_LINE_SIZE      ((1 << 10) | (1 << 11))
0218 #define DC_DV_CTL_DV_LINE_SIZE_1K   (0)
0219 #define DC_DV_CTL_DV_LINE_SIZE_2K   (1 << 10)
0220 #define DC_DV_CTL_DV_LINE_SIZE_4K   (1 << 11)
0221 #define DC_DV_CTL_DV_LINE_SIZE_8K   ((1 << 10) | (1 << 11))
0222 #define DC_DV_CTL_CLEAR_DV_RAM      (1 << 0)
0223
0224 #define DC_IRQ_FILT_CTL_H_FILT_SEL  (1 << 10)
0225
0226 #define DC_CLR_KEY_CLR_KEY_EN       (1 << 24)
0227
0228 #define DC_IRQ_VIP_VSYNC_IRQ_STATUS (1 << 21)   /* undocumented? */
0229 #define DC_IRQ_STATUS           (1 << 20)   /* undocumented? */
0230 #define DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK  (1 << 1)
0231 #define DC_IRQ_MASK         (1 << 0)
0232
0233 #define DC_GENLK_CTL_FLICK_SEL_MASK (0x0F << 28)
0234 #define DC_GENLK_CTL_ALPHA_FLICK_EN (1 << 25)
0235 #define DC_GENLK_CTL_FLICK_EN       (1 << 24)
0236 #define DC_GENLK_CTL_GENLK_EN       (1 << 18)
0237
0238
0239 /*
0240  * Video Processor registers (table 6-71).
0241  * There is space for 64 bit values, but we never use more than the
0242  * lower 32 bits.  The actual register save/restore code only bothers
0243  * to restore those 32 bits.
0244  */
0245 enum vp_registers {
0246     VP_VCFG = 0,
0247     VP_DCFG,
0248
0249     VP_VX,
0250     VP_VY,
0251
0252     VP_SCL,
0253     VP_VCK,
0254
0255     VP_VCM,
0256     VP_PAR,
0257
0258     VP_PDR,
0259     VP_SLR,
0260
0261     VP_MISC,
0262     VP_CCS,
0263
0264     VP_VYS,
0265     VP_VXS,
0266
0267     VP_RSVD_0,
0268     VP_VDC,
0269
0270     VP_RSVD_1,
0271     VP_CRC,
0272
0273     VP_CRC32,
0274     VP_VDE,
0275
0276     VP_CCK,
0277     VP_CCM,
0278
0279     VP_CC1,
0280     VP_CC2,
0281
0282     VP_A1X,
0283     VP_A1Y,
0284
0285     VP_A1C,
0286     VP_A1T,
0287
0288     VP_A2X,
0289     VP_A2Y,
0290
0291     VP_A2C,
0292     VP_A2T,
0293
0294     VP_A3X,
0295     VP_A3Y,
0296
0297     VP_A3C,
0298     VP_A3T,
0299
0300     VP_VRR,
0301     VP_AWT,
0302
0303     VP_VTM,
0304     VP_VYE,
0305
0306     VP_A1YE,
0307     VP_A2YE,
0308
0309     VP_A3YE,    /* 0x150 */
0310
0311     VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
0312 };
0313
0314 #define VP_VCFG_VID_EN          (1 << 0)
0315
0316 #define VP_DCFG_GV_GAM          (1 << 21)
0317 #define VP_DCFG_PWR_SEQ_DELAY       ((1 << 17) | (1 << 18) | (1 << 19))
0318 #define VP_DCFG_PWR_SEQ_DELAY_DEFAULT   (1 << 19)   /* undocumented */
0319 #define VP_DCFG_CRT_SYNC_SKW        ((1 << 14) | (1 << 15) | (1 << 16))
0320 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
0321 #define VP_DCFG_CRT_VSYNC_POL       (1 << 9)
0322 #define VP_DCFG_CRT_HSYNC_POL       (1 << 8)
0323 #define VP_DCFG_DAC_BL_EN       (1 << 3)
0324 #define VP_DCFG_VSYNC_EN        (1 << 2)
0325 #define VP_DCFG_HSYNC_EN        (1 << 1)
0326 #define VP_DCFG_CRT_EN          (1 << 0)
0327
0328 #define VP_MISC_APWRDN          (1 << 11)
0329 #define VP_MISC_DACPWRDN        (1 << 10)
0330 #define VP_MISC_BYP_BOTH        (1 << 0)
0331
0332
0333 /*
0334  * Flat Panel registers (table 6-71).
0335  * Also 64 bit registers; see above note about 32-bit handling.
0336  */
0337
0338 /* we're actually in the VP register space, starting at address 0x400 */
0339 #define VP_FP_START 0x400
0340
0341 enum fp_registers {
0342     FP_PT1 = 0,
0343     FP_PT2,
0344
0345     FP_PM,
0346     FP_DFC,
0347
0348     FP_RSVD_0,
0349     FP_RSVD_1,
0350
0351     FP_RSVD_2,
0352     FP_RSVD_3,
0353
0354     FP_RSVD_4,
0355     FP_DCA,
0356
0357     FP_DMD,
0358     FP_CRC, /* 0x458 */
0359 };
0360
0361 #define FP_PT2_HSP          (1 << 22)
0362 #define FP_PT2_VSP          (1 << 23)
0363 #define FP_PT2_SCRC         (1 << 27)   /* shfclk free */
0364
0365 #define FP_PM_P             (1 << 24)   /* panel power ctl */
0366 #define FP_PM_PANEL_PWR_UP      (1 << 3)    /* r/o */
0367 #define FP_PM_PANEL_PWR_DOWN        (1 << 2)    /* r/o */
0368 #define FP_PM_PANEL_OFF         (1 << 1)    /* r/o */
0369 #define FP_PM_PANEL_ON          (1 << 0)    /* r/o */
0370
0371 #define FP_DFC_BC           ((1 << 4) | (1 << 5) | (1 << 6))
0372
0373
0374 /* register access functions */
0375
0376 static inline uint32_t read_gp(struct lxfb_par *par, int reg)
0377 {
0378     return readl(par->gp_regs + 4*reg);
0379 }
0380
0381 static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
0382 {
0383     writel(val, par->gp_regs + 4*reg);
0384 }
0385
0386 static inline uint32_t read_dc(struct lxfb_par *par, int reg)
0387 {
0388     return readl(par->dc_regs + 4*reg);
0389 }
0390
0391 static inline void write_dc(struct lxfb_par *par, int reg, uint32_t val)
0392 {
0393     writel(val, par->dc_regs + 4*reg);
0394 }
0395
0396 static inline uint32_t read_vp(struct lxfb_par *par, int reg)
0397 {
0398     return readl(par->vp_regs + 8*reg);
0399 }
0400
0401 static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
0402 {
0403     writel(val, par->vp_regs + 8*reg);
0404 }
0405
0406 static inline uint32_t read_fp(struct lxfb_par *par, int reg)
0407 {
0408     return readl(par->vp_regs + 8*reg + VP_FP_START);
0409 }
0410
0411 static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
0412 {
0413     writel(val, par->vp_regs + 8*reg + VP_FP_START);
0414 }
0415
0416
0417 /* MSRs are defined in linux/cs5535.h; their bitfields are here */
0418
0419 #define MSR_GLCP_DOTPLL_LOCK        (1 << 25)   /* r/o */
0420 #define MSR_GLCP_DOTPLL_HALFPIX     (1 << 24)
0421 #define MSR_GLCP_DOTPLL_BYPASS      (1 << 15)
0422 #define MSR_GLCP_DOTPLL_DOTRESET    (1 << 0)
0423
0424 /* note: this is actually the VP's GLD_MSR_CONFIG */
0425 #define MSR_LX_GLD_MSR_CONFIG_FMT   ((1 << 3) | (1 << 4) | (1 << 5))
0426 #define MSR_LX_GLD_MSR_CONFIG_FMT_FP    (1 << 3)
0427 #define MSR_LX_GLD_MSR_CONFIG_FMT_CRT   (0)
0428 #define MSR_LX_GLD_MSR_CONFIG_FPC   (1 << 15)   /* FP *and* CRT */
0429
0430 #define MSR_LX_MSR_PADSEL_TFT_SEL_LOW   0xDFFFFFFF  /* ??? */
0431 #define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH  0x0000003F  /* ??? */
0432
0433 #define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO  (1 << 11)   /* undocumented */
0434 #define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL  (1 << 10)   /* undocumented */
0435 #define MSR_LX_SPARE_MSR_WM_LPEN_OVRD   (1 << 9)    /* undocumented */
0436 #define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8)    /* undocumented */
0437 #define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7)    /* undocumented */
0438 #define MSR_LX_SPARE_MSR_DIS_VIFO_WM    (1 << 6)
0439 #define MSR_LX_SPARE_MSR_DIS_CWD_CHECK  (1 << 5)    /* undocumented */
0440 #define MSR_LX_SPARE_MSR_PIX8_PAN_FIX   (1 << 4)    /* undocumented */
0441 #define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1)    /* undocumented */
0442
0443 #endif