fbdev/geode/gxfb.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2008 Andres Salomon <dilinger@debian.org>
0004  *
0005  * Geode GX2 header information
0006  */
0007 #ifndef _GXFB_H_
0008 #define _GXFB_H_
0009
0010 #include <linux/io.h>
0011
0012 #define GP_REG_COUNT   (0x50 / 4)
0013 #define DC_REG_COUNT   (0x90 / 4)
0014 #define VP_REG_COUNT   (0x138 / 8)
0015 #define FP_REG_COUNT   (0x68 / 8)
0016
0017 #define DC_PAL_COUNT   0x104
0018
0019 struct gxfb_par {
0020     int enable_crt;
0021     void __iomem *dc_regs;
0022     void __iomem *vid_regs;
0023     void __iomem *gp_regs;
0024     int powered_down;
0025
0026     /* register state, for power management functionality */
0027     struct {
0028         uint64_t padsel;
0029         uint64_t dotpll;
0030     } msr;
0031
0032     uint32_t gp[GP_REG_COUNT];
0033     uint32_t dc[DC_REG_COUNT];
0034     uint64_t vp[VP_REG_COUNT];
0035     uint64_t fp[FP_REG_COUNT];
0036
0037     uint32_t pal[DC_PAL_COUNT];
0038 };
0039
0040 unsigned int gx_frame_buffer_size(void);
0041 int gx_line_delta(int xres, int bpp);
0042 void gx_set_mode(struct fb_info *info);
0043 void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
0044         unsigned red, unsigned green, unsigned blue);
0045
0046 void gx_set_dclk_frequency(struct fb_info *info);
0047 void gx_configure_display(struct fb_info *info);
0048 int gx_blank_display(struct fb_info *info, int blank_mode);
0049
0050 int gx_powerdown(struct fb_info *info);
0051 int gx_powerup(struct fb_info *info);
0052
0053 /* Graphics Processor registers (table 6-23 from the data book) */
0054 enum gp_registers {
0055     GP_DST_OFFSET = 0,
0056     GP_SRC_OFFSET,
0057     GP_STRIDE,
0058     GP_WID_HEIGHT,
0059
0060     GP_SRC_COLOR_FG,
0061     GP_SRC_COLOR_BG,
0062     GP_PAT_COLOR_0,
0063     GP_PAT_COLOR_1,
0064
0065     GP_PAT_COLOR_2,
0066     GP_PAT_COLOR_3,
0067     GP_PAT_COLOR_4,
0068     GP_PAT_COLOR_5,
0069
0070     GP_PAT_DATA_0,
0071     GP_PAT_DATA_1,
0072     GP_RASTER_MODE,
0073     GP_VECTOR_MODE,
0074
0075     GP_BLT_MODE,
0076     GP_BLT_STATUS,
0077     GP_HST_SRC,
0078     GP_BASE_OFFSET, /* 0x4c */
0079 };
0080
0081 #define GP_BLT_STATUS_BLT_PENDING   (1 << 2)
0082 #define GP_BLT_STATUS_BLT_BUSY      (1 << 0)
0083
0084
0085 /* Display Controller registers (table 6-38 from the data book) */
0086 enum dc_registers {
0087     DC_UNLOCK = 0,
0088     DC_GENERAL_CFG,
0089     DC_DISPLAY_CFG,
0090     DC_RSVD_0,
0091
0092     DC_FB_ST_OFFSET,
0093     DC_CB_ST_OFFSET,
0094     DC_CURS_ST_OFFSET,
0095     DC_ICON_ST_OFFSET,
0096
0097     DC_VID_Y_ST_OFFSET,
0098     DC_VID_U_ST_OFFSET,
0099     DC_VID_V_ST_OFFSET,
0100     DC_RSVD_1,
0101
0102     DC_LINE_SIZE,
0103     DC_GFX_PITCH,
0104     DC_VID_YUV_PITCH,
0105     DC_RSVD_2,
0106
0107     DC_H_ACTIVE_TIMING,
0108     DC_H_BLANK_TIMING,
0109     DC_H_SYNC_TIMING,
0110     DC_RSVD_3,
0111
0112     DC_V_ACTIVE_TIMING,
0113     DC_V_BLANK_TIMING,
0114     DC_V_SYNC_TIMING,
0115     DC_RSVD_4,
0116
0117     DC_CURSOR_X,
0118     DC_CURSOR_Y,
0119     DC_ICON_X,
0120     DC_LINE_CNT,
0121
0122     DC_PAL_ADDRESS,
0123     DC_PAL_DATA,
0124     DC_DFIFO_DIAG,
0125     DC_CFIFO_DIAG,
0126
0127     DC_VID_DS_DELTA,
0128     DC_GLIU0_MEM_OFFSET,
0129     DC_RSVD_5,
0130     DC_DV_ACC, /* 0x8c */
0131 };
0132
0133 #define DC_UNLOCK_LOCK          0x00000000
0134 #define DC_UNLOCK_UNLOCK        0x00004758  /* magic value */
0135
0136 #define DC_GENERAL_CFG_YUVM     (1 << 20)
0137 #define DC_GENERAL_CFG_VDSE     (1 << 19)
0138 #define DC_GENERAL_CFG_DFHPEL_SHIFT 12
0139 #define DC_GENERAL_CFG_DFHPSL_SHIFT 8
0140 #define DC_GENERAL_CFG_DECE     (1 << 6)
0141 #define DC_GENERAL_CFG_CMPE     (1 << 5)
0142 #define DC_GENERAL_CFG_VIDE     (1 << 3)
0143 #define DC_GENERAL_CFG_ICNE     (1 << 2)
0144 #define DC_GENERAL_CFG_CURE     (1 << 1)
0145 #define DC_GENERAL_CFG_DFLE     (1 << 0)
0146
0147 #define DC_DISPLAY_CFG_A20M     (1 << 31)
0148 #define DC_DISPLAY_CFG_A18M     (1 << 30)
0149 #define DC_DISPLAY_CFG_PALB     (1 << 25)
0150 #define DC_DISPLAY_CFG_DISP_MODE_24BPP  (1 << 9)
0151 #define DC_DISPLAY_CFG_DISP_MODE_16BPP  (1 << 8)
0152 #define DC_DISPLAY_CFG_DISP_MODE_8BPP   (0)
0153 #define DC_DISPLAY_CFG_VDEN     (1 << 4)
0154 #define DC_DISPLAY_CFG_GDEN     (1 << 3)
0155 #define DC_DISPLAY_CFG_TGEN     (1 << 0)
0156
0157
0158 /*
0159  * Video Processor registers (table 6-54).
0160  * There is space for 64 bit values, but we never use more than the
0161  * lower 32 bits.  The actual register save/restore code only bothers
0162  * to restore those 32 bits.
0163  */
0164 enum vp_registers {
0165     VP_VCFG = 0,
0166     VP_DCFG,
0167
0168     VP_VX,
0169     VP_VY,
0170
0171     VP_VS,
0172     VP_VCK,
0173
0174     VP_VCM,
0175     VP_GAR,
0176
0177     VP_GDR,
0178     VP_RSVD_0,
0179
0180     VP_MISC,
0181     VP_CCS,
0182
0183     VP_RSVD_1,
0184     VP_RSVD_2,
0185
0186     VP_RSVD_3,
0187     VP_VDC,
0188
0189     VP_VCO,
0190     VP_CRC,
0191
0192     VP_CRC32,
0193     VP_VDE,
0194
0195     VP_CCK,
0196     VP_CCM,
0197
0198     VP_CC1,
0199     VP_CC2,
0200
0201     VP_A1X,
0202     VP_A1Y,
0203
0204     VP_A1C,
0205     VP_A1T,
0206
0207     VP_A2X,
0208     VP_A2Y,
0209
0210     VP_A2C,
0211     VP_A2T,
0212
0213     VP_A3X,
0214     VP_A3Y,
0215
0216     VP_A3C,
0217     VP_A3T,
0218
0219     VP_VRR,
0220     VP_AWT,
0221
0222     VP_VTM, /* 0x130 */
0223 };
0224
0225 #define VP_VCFG_VID_EN          (1 << 0)
0226
0227 #define VP_DCFG_DAC_VREF        (1 << 26)
0228 #define VP_DCFG_GV_GAM          (1 << 21)
0229 #define VP_DCFG_VG_CK           (1 << 20)
0230 #define VP_DCFG_CRT_SYNC_SKW_DEFAULT    (1 << 16)
0231 #define VP_DCFG_CRT_SYNC_SKW        ((1 << 14) | (1 << 15) | (1 << 16))
0232 #define VP_DCFG_CRT_VSYNC_POL       (1 << 9)
0233 #define VP_DCFG_CRT_HSYNC_POL       (1 << 8)
0234 #define VP_DCFG_FP_DATA_EN      (1 << 7)    /* undocumented */
0235 #define VP_DCFG_FP_PWR_EN       (1 << 6)    /* undocumented */
0236 #define VP_DCFG_DAC_BL_EN       (1 << 3)
0237 #define VP_DCFG_VSYNC_EN        (1 << 2)
0238 #define VP_DCFG_HSYNC_EN        (1 << 1)
0239 #define VP_DCFG_CRT_EN          (1 << 0)
0240
0241 #define VP_MISC_GAM_EN          (1 << 0)
0242 #define VP_MISC_DACPWRDN        (1 << 10)
0243 #define VP_MISC_APWRDN          (1 << 11)
0244
0245
0246 /*
0247  * Flat Panel registers (table 6-55).
0248  * Also 64 bit registers; see above note about 32-bit handling.
0249  */
0250
0251 /* we're actually in the VP register space, starting at address 0x400 */
0252 #define VP_FP_START     0x400
0253
0254 enum fp_registers {
0255     FP_PT1 = 0,
0256     FP_PT2,
0257
0258     FP_PM,
0259     FP_DFC,
0260
0261     FP_BLFSR,
0262     FP_RLFSR,
0263
0264     FP_FMI,
0265     FP_FMD,
0266
0267     FP_RSVD_0,
0268     FP_DCA,
0269
0270     FP_DMD,
0271     FP_CRC,
0272
0273     FP_FBB, /* 0x460 */
0274 };
0275
0276 #define FP_PT1_VSIZE_SHIFT      16      /* undocumented? */
0277 #define FP_PT1_VSIZE_MASK       0x7FF0000   /* undocumented? */
0278
0279 #define FP_PT2_HSP          (1 << 22)
0280 #define FP_PT2_VSP          (1 << 23)
0281
0282 #define FP_PM_P             (1 << 24)       /* panel power on */
0283 #define FP_PM_PANEL_PWR_UP      (1 << 3)        /* r/o */
0284 #define FP_PM_PANEL_PWR_DOWN        (1 << 2)        /* r/o */
0285 #define FP_PM_PANEL_OFF         (1 << 1)        /* r/o */
0286 #define FP_PM_PANEL_ON          (1 << 0)        /* r/o */
0287
0288 #define FP_DFC_NFI          ((1 << 4) | (1 << 5) | (1 << 6))
0289
0290
0291 /* register access functions */
0292
0293 static inline uint32_t read_gp(struct gxfb_par *par, int reg)
0294 {
0295     return readl(par->gp_regs + 4*reg);
0296 }
0297
0298 static inline void write_gp(struct gxfb_par *par, int reg, uint32_t val)
0299 {
0300     writel(val, par->gp_regs + 4*reg);
0301 }
0302
0303 static inline uint32_t read_dc(struct gxfb_par *par, int reg)
0304 {
0305     return readl(par->dc_regs + 4*reg);
0306 }
0307
0308 static inline void write_dc(struct gxfb_par *par, int reg, uint32_t val)
0309 {
0310     writel(val, par->dc_regs + 4*reg);
0311 }
0312
0313 static inline uint32_t read_vp(struct gxfb_par *par, int reg)
0314 {
0315     return readl(par->vid_regs + 8*reg);
0316 }
0317
0318 static inline void write_vp(struct gxfb_par *par, int reg, uint32_t val)
0319 {
0320     writel(val, par->vid_regs + 8*reg);
0321 }
0322
0323 static inline uint32_t read_fp(struct gxfb_par *par, int reg)
0324 {
0325     return readl(par->vid_regs + 8*reg + VP_FP_START);
0326 }
0327
0328 static inline void write_fp(struct gxfb_par *par, int reg, uint32_t val)
0329 {
0330     writel(val, par->vid_regs + 8*reg + VP_FP_START);
0331 }
0332
0333
0334 /* MSRs are defined in linux/cs5535.h; their bitfields are here */
0335
0336 #define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (1 << 3)
0337 #define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (1 << 2)
0338 #define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2  (1 << 1)
0339
0340 #define MSR_GLCP_DOTPLL_LOCK        (1 << 25)   /* r/o */
0341 #define MSR_GLCP_DOTPLL_BYPASS      (1 << 15)
0342 #define MSR_GLCP_DOTPLL_DOTRESET    (1 << 0)
0343
0344 #define MSR_GX_MSR_PADSEL_MASK      0x3FFFFFFF  /* undocumented? */
0345 #define MSR_GX_MSR_PADSEL_TFT       0x1FFFFFFF  /* undocumented? */
0346
0347 #define MSR_GX_GLD_MSR_CONFIG_FP    (1 << 3)
0348
0349 #endif