video/fbdev/dnfb.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #include <linux/kernel.h>
0003 #include <linux/errno.h>
0004 #include <linux/string.h>
0005 #include <linux/mm.h>
0006 #include <linux/delay.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/platform_device.h>
0009
0010 #include <asm/setup.h>
0011 #include <asm/irq.h>
0012 #include <asm/amigahw.h>
0013 #include <asm/amigaints.h>
0014 #include <asm/apollohw.h>
0015 #include <linux/fb.h>
0016 #include <linux/module.h>
0017
0018 /* apollo video HW definitions */
0019
0020 /*
0021  * Control Registers.   IOBASE + $x
0022  *
0023  * Note: these are the Memory/IO BASE definitions for a mono card set to the
0024  * alternate address
0025  *
0026  * Control 3A and 3B serve identical functions except that 3A
0027  * deals with control 1 and 3b deals with Color LUT reg.
0028  */
0029
0030 #define AP_IOBASE       0x3b0   /* Base address of 1 plane board. */
0031 #define AP_STATUS       isaIO2mem(AP_IOBASE+0)  /* Status register.  Read */
0032 #define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0)  /* Write Enable Register Write */
0033 #define AP_DEVICE_ID    isaIO2mem(AP_IOBASE+1)  /* Device ID Register. Read */
0034 #define AP_ROP_1        isaIO2mem(AP_IOBASE+2)  /* Raster Operation reg. Write Word */
0035 #define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4)  /* Diagnostic Memory Request. Write Word */
0036 #define AP_CONTROL_0    isaIO2mem(AP_IOBASE+8)  /* Control Register 0.  Read/Write */
0037 #define AP_CONTROL_1    isaIO2mem(AP_IOBASE+0xa)    /* Control Register 1.  Read/Write */
0038 #define AP_CONTROL_3A   isaIO2mem(AP_IOBASE+0xe)    /* Control Register 3a. Read/Write */
0039 #define AP_CONTROL_2    isaIO2mem(AP_IOBASE+0xc)    /* Control Register 2. Read/Write */
0040
0041
0042 #define FRAME_BUFFER_START 0x0FA0000
0043 #define FRAME_BUFFER_LEN 0x40000
0044
0045 /* CREG 0 */
0046 #define VECTOR_MODE 0x40    /* 010x.xxxx */
0047 #define DBLT_MODE   0x80    /* 100x.xxxx */
0048 #define NORMAL_MODE 0xE0    /* 111x.xxxx */
0049 #define SHIFT_BITS  0x1F    /* xxx1.1111 */
0050     /* other bits are Shift value */
0051
0052 /* CREG 1 */
0053 #define AD_BLT      0x80    /* 1xxx.xxxx */
0054 #define NORMAL      0x80 /* 1xxx.xxxx */    /* What is happening here ?? */
0055 #define INVERSE     0x00 /* 0xxx.xxxx */    /* Clearing this reverses the screen */
0056 #define PIX_BLT     0x00    /* 0xxx.xxxx */
0057
0058 #define AD_HIBIT        0x40    /* xIxx.xxxx */
0059
0060 #define ROP_EN          0x10    /* xxx1.xxxx */
0061 #define DST_EQ_SRC      0x00    /* xxx0.xxxx */
0062 #define nRESET_SYNC     0x08    /* xxxx.1xxx */
0063 #define SYNC_ENAB       0x02    /* xxxx.xx1x */
0064
0065 #define BLANK_DISP      0x00    /* xxxx.xxx0 */
0066 #define ENAB_DISP       0x01    /* xxxx.xxx1 */
0067
0068 #define NORM_CREG1      (nRESET_SYNC | SYNC_ENAB | ENAB_DISP)   /* no reset sync */
0069
0070 /* CREG 2 */
0071
0072 /*
0073  * Following 3 defines are common to 1, 4 and 8 plane.
0074  */
0075
0076 #define S_DATA_1s   0x00 /* 00xx.xxxx */    /* set source to all 1's -- vector drawing */
0077 #define S_DATA_PIX  0x40 /* 01xx.xxxx */    /* takes source from ls-bits and replicates over 16 bits */
0078 #define S_DATA_PLN  0xC0 /* 11xx.xxxx */    /* normal, each data access =16-bits in
0079                            one plane of image mem */
0080
0081 /* CREG 3A/CREG 3B */
0082 #       define RESET_CREG 0x80  /* 1000.0000 */
0083
0084 /* ROP REG  -  all one nibble */
0085 /*      ********* NOTE : this is used r0,r1,r2,r3 *********** */
0086 #define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
0087 #define DEST_ZERO               0x0
0088 #define SRC_AND_DEST    0x1
0089 #define SRC_AND_nDEST   0x2
0090 #define SRC                             0x3
0091 #define nSRC_AND_DEST   0x4
0092 #define DEST                    0x5
0093 #define SRC_XOR_DEST    0x6
0094 #define SRC_OR_DEST             0x7
0095 #define SRC_NOR_DEST    0x8
0096 #define SRC_XNOR_DEST   0x9
0097 #define nDEST                   0xA
0098 #define SRC_OR_nDEST    0xB
0099 #define nSRC                    0xC
0100 #define nSRC_OR_DEST    0xD
0101 #define SRC_NAND_DEST   0xE
0102 #define DEST_ONE                0xF
0103
0104 #define SWAP(A) ((A>>8) | ((A&0xff) <<8))
0105
0106 /* frame buffer operations */
0107
0108 static int dnfb_blank(int blank, struct fb_info *info);
0109 static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
0110
0111 static const struct fb_ops dn_fb_ops = {
0112     .owner      = THIS_MODULE,
0113     .fb_blank   = dnfb_blank,
0114     .fb_fillrect    = cfb_fillrect,
0115     .fb_copyarea    = dnfb_copyarea,
0116     .fb_imageblit   = cfb_imageblit,
0117 };
0118
0119 static const struct fb_var_screeninfo dnfb_var = {
0120     .xres       = 1280,
0121     .yres       = 1024,
0122     .xres_virtual   = 2048,
0123     .yres_virtual   = 1024,
0124     .bits_per_pixel = 1,
0125     .height     = -1,
0126     .width      = -1,
0127     .vmode      = FB_VMODE_NONINTERLACED,
0128 };
0129
0130 static const struct fb_fix_screeninfo dnfb_fix = {
0131     .id     = "Apollo Mono",
0132     .smem_start = (FRAME_BUFFER_START + IO_BASE),
0133     .smem_len   = FRAME_BUFFER_LEN,
0134     .type       = FB_TYPE_PACKED_PIXELS,
0135     .visual     = FB_VISUAL_MONO10,
0136     .line_length    = 256,
0137 };
0138
0139 static int dnfb_blank(int blank, struct fb_info *info)
0140 {
0141     if (blank)
0142         out_8(AP_CONTROL_3A, 0x0);
0143     else
0144         out_8(AP_CONTROL_3A, 0x1);
0145     return 0;
0146 }
0147
0148 static
0149 void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
0150 {
0151
0152     int incr, y_delta, pre_read = 0, x_end, x_word_count;
0153     uint start_mask, end_mask, dest;
0154     ushort *src, dummy;
0155     short i, j;
0156
0157     incr = (area->dy <= area->sy) ? 1 : -1;
0158
0159     src = (ushort *)(info->screen_base + area->sy * info->fix.line_length +
0160             (area->sx >> 4));
0161     dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4);
0162
0163     if (incr > 0) {
0164         y_delta = (info->fix.line_length * 8) - area->sx - area->width;
0165         x_end = area->dx + area->width - 1;
0166         x_word_count = (x_end >> 4) - (area->dx >> 4) + 1;
0167         start_mask = 0xffff0000 >> (area->dx & 0xf);
0168         end_mask = 0x7ffff >> (x_end & 0xf);
0169         out_8(AP_CONTROL_0,
0170              (((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5));
0171         if ((area->dx & 0xf) < (area->sx & 0xf))
0172             pre_read = 1;
0173     } else {
0174         y_delta = -((info->fix.line_length * 8) - area->sx - area->width);
0175         x_end = area->dx - area->width + 1;
0176         x_word_count = (area->dx >> 4) - (x_end >> 4) + 1;
0177         start_mask = 0x7ffff >> (area->dx & 0xf);
0178         end_mask = 0xffff0000 >> (x_end & 0xf);
0179         out_8(AP_CONTROL_0,
0180              ((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) |
0181              (0x4 << 5));
0182         if ((area->dx & 0xf) > (area->sx & 0xf))
0183             pre_read = 1;
0184     }
0185
0186     for (i = 0; i < area->height; i++) {
0187
0188         out_8(AP_CONTROL_3A, 0xc | (dest >> 16));
0189
0190         if (pre_read) {
0191             dummy = *src;
0192             src += incr;
0193         }
0194
0195         if (x_word_count) {
0196             out_8(AP_WRITE_ENABLE, start_mask);
0197             *src = dest;
0198             src += incr;
0199             dest += incr;
0200             out_8(AP_WRITE_ENABLE, 0);
0201
0202             for (j = 1; j < (x_word_count - 1); j++) {
0203                 *src = dest;
0204                 src += incr;
0205                 dest += incr;
0206             }
0207
0208             out_8(AP_WRITE_ENABLE, start_mask);
0209             *src = dest;
0210             dest += incr;
0211             src += incr;
0212         } else {
0213             out_8(AP_WRITE_ENABLE, start_mask | end_mask);
0214             *src = dest;
0215             dest += incr;
0216             src += incr;
0217         }
0218         src += (y_delta / 16);
0219         dest += (y_delta / 16);
0220     }
0221     out_8(AP_CONTROL_0, NORMAL_MODE);
0222 }
0223
0224 /*
0225  * Initialization
0226  */
0227
0228 static int dnfb_probe(struct platform_device *dev)
0229 {
0230     struct fb_info *info;
0231     int err = 0;
0232
0233     info = framebuffer_alloc(0, &dev->dev);
0234     if (!info)
0235         return -ENOMEM;
0236
0237     info->fbops = &dn_fb_ops;
0238     info->fix = dnfb_fix;
0239     info->var = dnfb_var;
0240     info->var.red.length = 1;
0241     info->var.red.offset = 0;
0242     info->var.green = info->var.blue = info->var.red;
0243     info->screen_base = (u_char *) info->fix.smem_start;
0244
0245     err = fb_alloc_cmap(&info->cmap, 2, 0);
0246     if (err < 0)
0247         goto release_framebuffer;
0248
0249     err = register_framebuffer(info);
0250     if (err < 0) {
0251         fb_dealloc_cmap(&info->cmap);
0252         goto release_framebuffer;
0253     }
0254     platform_set_drvdata(dev, info);
0255
0256     /* now we have registered we can safely setup the hardware */
0257     out_8(AP_CONTROL_3A, RESET_CREG);
0258     out_be16(AP_WRITE_ENABLE, 0x0);
0259     out_8(AP_CONTROL_0, NORMAL_MODE);
0260     out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1));
0261     out_8(AP_CONTROL_2, S_DATA_PLN);
0262     out_be16(AP_ROP_1, SWAP(0x3));
0263
0264     printk("apollo frame buffer alive and kicking !\n");
0265     return err;
0266
0267 release_framebuffer:
0268     framebuffer_release(info);
0269     return err;
0270 }
0271
0272 static struct platform_driver dnfb_driver = {
0273     .probe  = dnfb_probe,
0274     .driver = {
0275         .name   = "dnfb",
0276     },
0277 };
0278
0279 static struct platform_device dnfb_device = {
0280     .name   = "dnfb",
0281 };
0282
0283 static int __init dnfb_init(void)
0284 {
0285     int ret;
0286
0287     if (!MACH_IS_APOLLO)
0288         return -ENODEV;
0289
0290     if (fb_get_options("dnfb", NULL))
0291         return -ENODEV;
0292
0293     ret = platform_driver_register(&dnfb_driver);
0294
0295     if (!ret) {
0296         ret = platform_device_register(&dnfb_device);
0297         if (ret)
0298             platform_driver_unregister(&dnfb_driver);
0299     }
0300     return ret;
0301 }
0302
0303 module_init(dnfb_init);
0304
0305 MODULE_LICENSE("GPL");