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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2008-2009 MontaVista Software Inc.
0004  * Copyright (C) 2008-2009 Texas Instruments Inc
0005  *
0006  * Based on the LCD driver for TI Avalanche processors written by
0007  * Ajay Singh and Shalom Hai.
0008  */
0009 #include <linux/module.h>
0010 #include <linux/kernel.h>
0011 #include <linux/fb.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/uaccess.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/wait.h>
0019 #include <linux/clk.h>
0020 #include <linux/cpufreq.h>
0021 #include <linux/console.h>
0022 #include <linux/regulator/consumer.h>
0023 #include <linux/spinlock.h>
0024 #include <linux/slab.h>
0025 #include <linux/delay.h>
0026 #include <linux/lcm.h>
0027 #include <video/da8xx-fb.h>
0028 #include <asm/div64.h>
0029 
0030 #define DRIVER_NAME "da8xx_lcdc"
0031 
0032 #define LCD_VERSION_1   1
0033 #define LCD_VERSION_2   2
0034 
0035 /* LCD Status Register */
0036 #define LCD_END_OF_FRAME1       BIT(9)
0037 #define LCD_END_OF_FRAME0       BIT(8)
0038 #define LCD_PL_LOAD_DONE        BIT(6)
0039 #define LCD_FIFO_UNDERFLOW      BIT(5)
0040 #define LCD_SYNC_LOST           BIT(2)
0041 #define LCD_FRAME_DONE          BIT(0)
0042 
0043 /* LCD DMA Control Register */
0044 #define LCD_DMA_BURST_SIZE(x)       ((x) << 4)
0045 #define LCD_DMA_BURST_1         0x0
0046 #define LCD_DMA_BURST_2         0x1
0047 #define LCD_DMA_BURST_4         0x2
0048 #define LCD_DMA_BURST_8         0x3
0049 #define LCD_DMA_BURST_16        0x4
0050 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
0051 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
0052 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
0053 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
0054 
0055 /* LCD Control Register */
0056 #define LCD_CLK_DIVISOR(x)      ((x) << 8)
0057 #define LCD_RASTER_MODE         0x01
0058 
0059 /* LCD Raster Control Register */
0060 #define LCD_PALETTE_LOAD_MODE(x)    ((x) << 20)
0061 #define PALETTE_AND_DATA        0x00
0062 #define PALETTE_ONLY            0x01
0063 #define DATA_ONLY           0x02
0064 
0065 #define LCD_MONO_8BIT_MODE      BIT(9)
0066 #define LCD_RASTER_ORDER        BIT(8)
0067 #define LCD_TFT_MODE            BIT(7)
0068 #define LCD_V1_UNDERFLOW_INT_ENA    BIT(6)
0069 #define LCD_V2_UNDERFLOW_INT_ENA    BIT(5)
0070 #define LCD_V1_PL_INT_ENA       BIT(4)
0071 #define LCD_V2_PL_INT_ENA       BIT(6)
0072 #define LCD_MONOCHROME_MODE     BIT(1)
0073 #define LCD_RASTER_ENABLE       BIT(0)
0074 #define LCD_TFT_ALT_ENABLE      BIT(23)
0075 #define LCD_STN_565_ENABLE      BIT(24)
0076 #define LCD_V2_DMA_CLK_EN       BIT(2)
0077 #define LCD_V2_LIDD_CLK_EN      BIT(1)
0078 #define LCD_V2_CORE_CLK_EN      BIT(0)
0079 #define LCD_V2_LPP_B10          26
0080 #define LCD_V2_TFT_24BPP_MODE       BIT(25)
0081 #define LCD_V2_TFT_24BPP_UNPACK     BIT(26)
0082 
0083 /* LCD Raster Timing 2 Register */
0084 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)  ((x) << 16)
0085 #define LCD_AC_BIAS_FREQUENCY(x)        ((x) << 8)
0086 #define LCD_SYNC_CTRL               BIT(25)
0087 #define LCD_SYNC_EDGE               BIT(24)
0088 #define LCD_INVERT_PIXEL_CLOCK          BIT(22)
0089 #define LCD_INVERT_LINE_CLOCK           BIT(21)
0090 #define LCD_INVERT_FRAME_CLOCK          BIT(20)
0091 
0092 /* LCD Block */
0093 #define  LCD_PID_REG                0x0
0094 #define  LCD_CTRL_REG               0x4
0095 #define  LCD_STAT_REG               0x8
0096 #define  LCD_RASTER_CTRL_REG            0x28
0097 #define  LCD_RASTER_TIMING_0_REG        0x2C
0098 #define  LCD_RASTER_TIMING_1_REG        0x30
0099 #define  LCD_RASTER_TIMING_2_REG        0x34
0100 #define  LCD_DMA_CTRL_REG           0x40
0101 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG    0x44
0102 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
0103 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG    0x4C
0104 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
0105 
0106 /* Interrupt Registers available only in Version 2 */
0107 #define  LCD_RAW_STAT_REG           0x58
0108 #define  LCD_MASKED_STAT_REG            0x5c
0109 #define  LCD_INT_ENABLE_SET_REG         0x60
0110 #define  LCD_INT_ENABLE_CLR_REG         0x64
0111 #define  LCD_END_OF_INT_IND_REG         0x68
0112 
0113 /* Clock registers available only on Version 2 */
0114 #define  LCD_CLK_ENABLE_REG         0x6c
0115 #define  LCD_CLK_RESET_REG          0x70
0116 #define  LCD_CLK_MAIN_RESET         BIT(3)
0117 
0118 #define LCD_NUM_BUFFERS 2
0119 
0120 #define PALETTE_SIZE    256
0121 
0122 #define CLK_MIN_DIV 2
0123 #define CLK_MAX_DIV 255
0124 
0125 static void __iomem *da8xx_fb_reg_base;
0126 static unsigned int lcd_revision;
0127 static irq_handler_t lcdc_irq_handler;
0128 static wait_queue_head_t frame_done_wq;
0129 static int frame_done_flag;
0130 
0131 static unsigned int lcdc_read(unsigned int addr)
0132 {
0133     return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
0134 }
0135 
0136 static void lcdc_write(unsigned int val, unsigned int addr)
0137 {
0138     __raw_writel(val, da8xx_fb_reg_base + (addr));
0139 }
0140 
0141 struct da8xx_fb_par {
0142     struct device       *dev;
0143     dma_addr_t      p_palette_base;
0144     unsigned char *v_palette_base;
0145     dma_addr_t      vram_phys;
0146     unsigned long       vram_size;
0147     void            *vram_virt;
0148     unsigned int        dma_start;
0149     unsigned int        dma_end;
0150     struct clk *lcdc_clk;
0151     int irq;
0152     unsigned int palette_sz;
0153     int blank;
0154     wait_queue_head_t   vsync_wait;
0155     int         vsync_flag;
0156     int         vsync_timeout;
0157     spinlock_t      lock_for_chan_update;
0158 
0159     /*
0160      * LCDC has 2 ping pong DMA channels, channel 0
0161      * and channel 1.
0162      */
0163     unsigned int        which_dma_channel_done;
0164 #ifdef CONFIG_CPU_FREQ
0165     struct notifier_block   freq_transition;
0166 #endif
0167     unsigned int        lcdc_clk_rate;
0168     struct regulator    *lcd_supply;
0169     u32 pseudo_palette[16];
0170     struct fb_videomode mode;
0171     struct lcd_ctrl_config  cfg;
0172 };
0173 
0174 static struct fb_var_screeninfo da8xx_fb_var;
0175 
0176 static struct fb_fix_screeninfo da8xx_fb_fix = {
0177     .id = "DA8xx FB Drv",
0178     .type = FB_TYPE_PACKED_PIXELS,
0179     .type_aux = 0,
0180     .visual = FB_VISUAL_PSEUDOCOLOR,
0181     .xpanstep = 0,
0182     .ypanstep = 1,
0183     .ywrapstep = 0,
0184     .accel = FB_ACCEL_NONE
0185 };
0186 
0187 static struct fb_videomode known_lcd_panels[] = {
0188     /* Sharp LCD035Q3DG01 */
0189     [0] = {
0190         .name           = "Sharp_LCD035Q3DG01",
0191         .xres           = 320,
0192         .yres           = 240,
0193         .pixclock       = KHZ2PICOS(4607),
0194         .left_margin    = 6,
0195         .right_margin   = 8,
0196         .upper_margin   = 2,
0197         .lower_margin   = 2,
0198         .hsync_len      = 0,
0199         .vsync_len      = 0,
0200         .sync           = FB_SYNC_CLK_INVERT,
0201     },
0202     /* Sharp LK043T1DG01 */
0203     [1] = {
0204         .name           = "Sharp_LK043T1DG01",
0205         .xres           = 480,
0206         .yres           = 272,
0207         .pixclock       = KHZ2PICOS(7833),
0208         .left_margin    = 2,
0209         .right_margin   = 2,
0210         .upper_margin   = 2,
0211         .lower_margin   = 2,
0212         .hsync_len      = 41,
0213         .vsync_len      = 10,
0214         .sync           = 0,
0215         .flag           = 0,
0216     },
0217     [2] = {
0218         /* Hitachi SP10Q010 */
0219         .name           = "SP10Q010",
0220         .xres           = 320,
0221         .yres           = 240,
0222         .pixclock       = KHZ2PICOS(7833),
0223         .left_margin    = 10,
0224         .right_margin   = 10,
0225         .upper_margin   = 10,
0226         .lower_margin   = 10,
0227         .hsync_len      = 10,
0228         .vsync_len      = 10,
0229         .sync           = 0,
0230         .flag           = 0,
0231     },
0232     [3] = {
0233         /* Densitron 84-0023-001T */
0234         .name           = "Densitron_84-0023-001T",
0235         .xres           = 320,
0236         .yres           = 240,
0237         .pixclock       = KHZ2PICOS(6400),
0238         .left_margin    = 0,
0239         .right_margin   = 0,
0240         .upper_margin   = 0,
0241         .lower_margin   = 0,
0242         .hsync_len      = 30,
0243         .vsync_len      = 3,
0244         .sync           = 0,
0245     },
0246 };
0247 
0248 static bool da8xx_fb_is_raster_enabled(void)
0249 {
0250     return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
0251 }
0252 
0253 /* Enable the Raster Engine of the LCD Controller */
0254 static void lcd_enable_raster(void)
0255 {
0256     u32 reg;
0257 
0258     /* Put LCDC in reset for several cycles */
0259     if (lcd_revision == LCD_VERSION_2)
0260         /* Write 1 to reset LCDC */
0261         lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
0262     mdelay(1);
0263 
0264     /* Bring LCDC out of reset */
0265     if (lcd_revision == LCD_VERSION_2)
0266         lcdc_write(0, LCD_CLK_RESET_REG);
0267     mdelay(1);
0268 
0269     /* Above reset sequence doesnot reset register context */
0270     reg = lcdc_read(LCD_RASTER_CTRL_REG);
0271     if (!(reg & LCD_RASTER_ENABLE))
0272         lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
0273 }
0274 
0275 /* Disable the Raster Engine of the LCD Controller */
0276 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
0277 {
0278     u32 reg;
0279     int ret;
0280 
0281     reg = lcdc_read(LCD_RASTER_CTRL_REG);
0282     if (reg & LCD_RASTER_ENABLE)
0283         lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
0284     else
0285         /* return if already disabled */
0286         return;
0287 
0288     if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
0289             (lcd_revision == LCD_VERSION_2)) {
0290         frame_done_flag = 0;
0291         ret = wait_event_interruptible_timeout(frame_done_wq,
0292                 frame_done_flag != 0,
0293                 msecs_to_jiffies(50));
0294         if (ret == 0)
0295             pr_err("LCD Controller timed out\n");
0296     }
0297 }
0298 
0299 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
0300 {
0301     u32 start;
0302     u32 end;
0303     u32 reg_ras;
0304     u32 reg_dma;
0305     u32 reg_int;
0306 
0307     /* init reg to clear PLM (loading mode) fields */
0308     reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
0309     reg_ras &= ~(3 << 20);
0310 
0311     reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
0312 
0313     if (load_mode == LOAD_DATA) {
0314         start    = par->dma_start;
0315         end      = par->dma_end;
0316 
0317         reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
0318         if (lcd_revision == LCD_VERSION_1) {
0319             reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
0320         } else {
0321             reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
0322                 LCD_V2_END_OF_FRAME0_INT_ENA |
0323                 LCD_V2_END_OF_FRAME1_INT_ENA |
0324                 LCD_FRAME_DONE | LCD_SYNC_LOST;
0325             lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
0326         }
0327         reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
0328 
0329         lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
0330         lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
0331         lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
0332         lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
0333     } else if (load_mode == LOAD_PALETTE) {
0334         start    = par->p_palette_base;
0335         end      = start + par->palette_sz - 1;
0336 
0337         reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
0338 
0339         if (lcd_revision == LCD_VERSION_1) {
0340             reg_ras |= LCD_V1_PL_INT_ENA;
0341         } else {
0342             reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
0343                 LCD_V2_PL_INT_ENA;
0344             lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
0345         }
0346 
0347         lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
0348         lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
0349     }
0350 
0351     lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
0352     lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
0353 
0354     /*
0355      * The Raster enable bit must be set after all other control fields are
0356      * set.
0357      */
0358     lcd_enable_raster();
0359 }
0360 
0361 /* Configure the Burst Size and fifo threhold of DMA */
0362 static int lcd_cfg_dma(int burst_size, int fifo_th)
0363 {
0364     u32 reg;
0365 
0366     reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
0367     switch (burst_size) {
0368     case 1:
0369         reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
0370         break;
0371     case 2:
0372         reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
0373         break;
0374     case 4:
0375         reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
0376         break;
0377     case 8:
0378         reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
0379         break;
0380     case 16:
0381     default:
0382         reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
0383         break;
0384     }
0385 
0386     reg |= (fifo_th << 8);
0387 
0388     lcdc_write(reg, LCD_DMA_CTRL_REG);
0389 
0390     return 0;
0391 }
0392 
0393 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
0394 {
0395     u32 reg;
0396 
0397     /* Set the AC Bias Period and Number of Transisitons per Interrupt */
0398     reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
0399     reg |= LCD_AC_BIAS_FREQUENCY(period) |
0400         LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
0401     lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
0402 }
0403 
0404 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
0405         int front_porch)
0406 {
0407     u32 reg;
0408 
0409     reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
0410     reg |= (((back_porch-1) & 0xff) << 24)
0411         | (((front_porch-1) & 0xff) << 16)
0412         | (((pulse_width-1) & 0x3f) << 10);
0413     lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
0414 
0415     /*
0416      * LCDC Version 2 adds some extra bits that increase the allowable
0417      * size of the horizontal timing registers.
0418      * remember that the registers use 0 to represent 1 so all values
0419      * that get set into register need to be decremented by 1
0420      */
0421     if (lcd_revision == LCD_VERSION_2) {
0422         /* Mask off the bits we want to change */
0423         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
0424         reg |= ((front_porch-1) & 0x300) >> 8;
0425         reg |= ((back_porch-1) & 0x300) >> 4;
0426         reg |= ((pulse_width-1) & 0x3c0) << 21;
0427         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
0428     }
0429 }
0430 
0431 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
0432         int front_porch)
0433 {
0434     u32 reg;
0435 
0436     reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
0437     reg |= ((back_porch & 0xff) << 24)
0438         | ((front_porch & 0xff) << 16)
0439         | (((pulse_width-1) & 0x3f) << 10);
0440     lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
0441 }
0442 
0443 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
0444         struct fb_videomode *panel)
0445 {
0446     u32 reg;
0447     u32 reg_int;
0448 
0449     reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
0450                         LCD_MONO_8BIT_MODE |
0451                         LCD_MONOCHROME_MODE);
0452 
0453     switch (cfg->panel_shade) {
0454     case MONOCHROME:
0455         reg |= LCD_MONOCHROME_MODE;
0456         if (cfg->mono_8bit_mode)
0457             reg |= LCD_MONO_8BIT_MODE;
0458         break;
0459     case COLOR_ACTIVE:
0460         reg |= LCD_TFT_MODE;
0461         if (cfg->tft_alt_mode)
0462             reg |= LCD_TFT_ALT_ENABLE;
0463         break;
0464 
0465     case COLOR_PASSIVE:
0466         /* AC bias applicable only for Pasive panels */
0467         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
0468         if (cfg->bpp == 12 && cfg->stn_565_mode)
0469             reg |= LCD_STN_565_ENABLE;
0470         break;
0471 
0472     default:
0473         return -EINVAL;
0474     }
0475 
0476     /* enable additional interrupts here */
0477     if (lcd_revision == LCD_VERSION_1) {
0478         reg |= LCD_V1_UNDERFLOW_INT_ENA;
0479     } else {
0480         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
0481             LCD_V2_UNDERFLOW_INT_ENA;
0482         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
0483     }
0484 
0485     lcdc_write(reg, LCD_RASTER_CTRL_REG);
0486 
0487     reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
0488 
0489     reg |= LCD_SYNC_CTRL;
0490 
0491     if (cfg->sync_edge)
0492         reg |= LCD_SYNC_EDGE;
0493     else
0494         reg &= ~LCD_SYNC_EDGE;
0495 
0496     if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
0497         reg |= LCD_INVERT_LINE_CLOCK;
0498     else
0499         reg &= ~LCD_INVERT_LINE_CLOCK;
0500 
0501     if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
0502         reg |= LCD_INVERT_FRAME_CLOCK;
0503     else
0504         reg &= ~LCD_INVERT_FRAME_CLOCK;
0505 
0506     lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
0507 
0508     return 0;
0509 }
0510 
0511 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
0512         u32 bpp, u32 raster_order)
0513 {
0514     u32 reg;
0515 
0516     if (bpp > 16 && lcd_revision == LCD_VERSION_1)
0517         return -EINVAL;
0518 
0519     /* Set the Panel Width */
0520     /* Pixels per line = (PPL + 1)*16 */
0521     if (lcd_revision == LCD_VERSION_1) {
0522         /*
0523          * 0x3F in bits 4..9 gives max horizontal resolution = 1024
0524          * pixels.
0525          */
0526         width &= 0x3f0;
0527     } else {
0528         /*
0529          * 0x7F in bits 4..10 gives max horizontal resolution = 2048
0530          * pixels.
0531          */
0532         width &= 0x7f0;
0533     }
0534 
0535     reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
0536     reg &= 0xfffffc00;
0537     if (lcd_revision == LCD_VERSION_1) {
0538         reg |= ((width >> 4) - 1) << 4;
0539     } else {
0540         width = (width >> 4) - 1;
0541         reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
0542     }
0543     lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
0544 
0545     /* Set the Panel Height */
0546     /* Set bits 9:0 of Lines Per Pixel */
0547     reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
0548     reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
0549     lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
0550 
0551     /* Set bit 10 of Lines Per Pixel */
0552     if (lcd_revision == LCD_VERSION_2) {
0553         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
0554         reg |= ((height - 1) & 0x400) << 16;
0555         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
0556     }
0557 
0558     /* Set the Raster Order of the Frame Buffer */
0559     reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
0560     if (raster_order)
0561         reg |= LCD_RASTER_ORDER;
0562 
0563     par->palette_sz = 16 * 2;
0564 
0565     switch (bpp) {
0566     case 1:
0567     case 2:
0568     case 4:
0569     case 16:
0570         break;
0571     case 24:
0572         reg |= LCD_V2_TFT_24BPP_MODE;
0573         break;
0574     case 32:
0575         reg |= LCD_V2_TFT_24BPP_MODE;
0576         reg |= LCD_V2_TFT_24BPP_UNPACK;
0577         break;
0578     case 8:
0579         par->palette_sz = 256 * 2;
0580         break;
0581 
0582     default:
0583         return -EINVAL;
0584     }
0585 
0586     lcdc_write(reg, LCD_RASTER_CTRL_REG);
0587 
0588     return 0;
0589 }
0590 
0591 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
0592 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
0593                   unsigned blue, unsigned transp,
0594                   struct fb_info *info)
0595 {
0596     struct da8xx_fb_par *par = info->par;
0597     unsigned short *palette = (unsigned short *) par->v_palette_base;
0598     u_short pal;
0599     int update_hw = 0;
0600 
0601     if (regno > 255)
0602         return 1;
0603 
0604     if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
0605         return 1;
0606 
0607     if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
0608         return -EINVAL;
0609 
0610     switch (info->fix.visual) {
0611     case FB_VISUAL_TRUECOLOR:
0612         red = CNVT_TOHW(red, info->var.red.length);
0613         green = CNVT_TOHW(green, info->var.green.length);
0614         blue = CNVT_TOHW(blue, info->var.blue.length);
0615         break;
0616     case FB_VISUAL_PSEUDOCOLOR:
0617         switch (info->var.bits_per_pixel) {
0618         case 4:
0619             if (regno > 15)
0620                 return -EINVAL;
0621 
0622             if (info->var.grayscale) {
0623                 pal = regno;
0624             } else {
0625                 red >>= 4;
0626                 green >>= 8;
0627                 blue >>= 12;
0628 
0629                 pal = red & 0x0f00;
0630                 pal |= green & 0x00f0;
0631                 pal |= blue & 0x000f;
0632             }
0633             if (regno == 0)
0634                 pal |= 0x2000;
0635             palette[regno] = pal;
0636             break;
0637 
0638         case 8:
0639             red >>= 4;
0640             green >>= 8;
0641             blue >>= 12;
0642 
0643             pal = (red & 0x0f00);
0644             pal |= (green & 0x00f0);
0645             pal |= (blue & 0x000f);
0646 
0647             if (palette[regno] != pal) {
0648                 update_hw = 1;
0649                 palette[regno] = pal;
0650             }
0651             break;
0652         }
0653         break;
0654     }
0655 
0656     /* Truecolor has hardware independent palette */
0657     if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
0658         u32 v;
0659 
0660         if (regno > 15)
0661             return -EINVAL;
0662 
0663         v = (red << info->var.red.offset) |
0664             (green << info->var.green.offset) |
0665             (blue << info->var.blue.offset);
0666 
0667         ((u32 *) (info->pseudo_palette))[regno] = v;
0668         if (palette[0] != 0x4000) {
0669             update_hw = 1;
0670             palette[0] = 0x4000;
0671         }
0672     }
0673 
0674     /* Update the palette in the h/w as needed. */
0675     if (update_hw)
0676         lcd_blit(LOAD_PALETTE, par);
0677 
0678     return 0;
0679 }
0680 #undef CNVT_TOHW
0681 
0682 static void da8xx_fb_lcd_reset(void)
0683 {
0684     /* DMA has to be disabled */
0685     lcdc_write(0, LCD_DMA_CTRL_REG);
0686     lcdc_write(0, LCD_RASTER_CTRL_REG);
0687 
0688     if (lcd_revision == LCD_VERSION_2) {
0689         lcdc_write(0, LCD_INT_ENABLE_SET_REG);
0690         /* Write 1 to reset */
0691         lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
0692         lcdc_write(0, LCD_CLK_RESET_REG);
0693     }
0694 }
0695 
0696 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
0697                           unsigned lcdc_clk_div,
0698                           unsigned lcdc_clk_rate)
0699 {
0700     int ret;
0701 
0702     if (par->lcdc_clk_rate != lcdc_clk_rate) {
0703         ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
0704         if (ret) {
0705             dev_err(par->dev,
0706                 "unable to set clock rate at %u\n",
0707                 lcdc_clk_rate);
0708             return ret;
0709         }
0710         par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
0711     }
0712 
0713     /* Configure the LCD clock divisor. */
0714     lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
0715             (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
0716 
0717     if (lcd_revision == LCD_VERSION_2)
0718         lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
0719                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
0720 
0721     return 0;
0722 }
0723 
0724 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
0725                           unsigned pixclock,
0726                           unsigned *lcdc_clk_rate)
0727 {
0728     unsigned lcdc_clk_div;
0729 
0730     pixclock = PICOS2KHZ(pixclock) * 1000;
0731 
0732     *lcdc_clk_rate = par->lcdc_clk_rate;
0733 
0734     if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
0735         *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
0736                         pixclock * CLK_MAX_DIV);
0737         lcdc_clk_div = CLK_MAX_DIV;
0738     } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
0739         *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
0740                         pixclock * CLK_MIN_DIV);
0741         lcdc_clk_div = CLK_MIN_DIV;
0742     } else {
0743         lcdc_clk_div = *lcdc_clk_rate / pixclock;
0744     }
0745 
0746     return lcdc_clk_div;
0747 }
0748 
0749 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
0750                         struct fb_videomode *mode)
0751 {
0752     unsigned lcdc_clk_rate;
0753     unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
0754                               &lcdc_clk_rate);
0755 
0756     return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
0757 }
0758 
0759 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
0760                       unsigned pixclock)
0761 {
0762     unsigned lcdc_clk_div, lcdc_clk_rate;
0763 
0764     lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
0765     return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
0766 }
0767 
0768 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
0769         struct fb_videomode *panel)
0770 {
0771     u32 bpp;
0772     int ret = 0;
0773 
0774     ret = da8xx_fb_calc_config_clk_divider(par, panel);
0775     if (ret) {
0776         dev_err(par->dev, "unable to configure clock\n");
0777         return ret;
0778     }
0779 
0780     if (panel->sync & FB_SYNC_CLK_INVERT)
0781         lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
0782             LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
0783     else
0784         lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
0785             ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
0786 
0787     /* Configure the DMA burst size and fifo threshold. */
0788     ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
0789     if (ret < 0)
0790         return ret;
0791 
0792     /* Configure the vertical and horizontal sync properties. */
0793     lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
0794             panel->lower_margin);
0795     lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
0796             panel->right_margin);
0797 
0798     /* Configure for disply */
0799     ret = lcd_cfg_display(cfg, panel);
0800     if (ret < 0)
0801         return ret;
0802 
0803     bpp = cfg->bpp;
0804 
0805     if (bpp == 12)
0806         bpp = 16;
0807     ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
0808                 (unsigned int)panel->yres, bpp,
0809                 cfg->raster_order);
0810     if (ret < 0)
0811         return ret;
0812 
0813     /* Configure FDD */
0814     lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
0815                (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
0816 
0817     return 0;
0818 }
0819 
0820 /* IRQ handler for version 2 of LCDC */
0821 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
0822 {
0823     struct da8xx_fb_par *par = arg;
0824     u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
0825 
0826     if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
0827         lcd_disable_raster(DA8XX_FRAME_NOWAIT);
0828         lcdc_write(stat, LCD_MASKED_STAT_REG);
0829         lcd_enable_raster();
0830     } else if (stat & LCD_PL_LOAD_DONE) {
0831         /*
0832          * Must disable raster before changing state of any control bit.
0833          * And also must be disabled before clearing the PL loading
0834          * interrupt via the following write to the status register. If
0835          * this is done after then one gets multiple PL done interrupts.
0836          */
0837         lcd_disable_raster(DA8XX_FRAME_NOWAIT);
0838 
0839         lcdc_write(stat, LCD_MASKED_STAT_REG);
0840 
0841         /* Disable PL completion interrupt */
0842         lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
0843 
0844         /* Setup and start data loading mode */
0845         lcd_blit(LOAD_DATA, par);
0846     } else {
0847         lcdc_write(stat, LCD_MASKED_STAT_REG);
0848 
0849         if (stat & LCD_END_OF_FRAME0) {
0850             par->which_dma_channel_done = 0;
0851             lcdc_write(par->dma_start,
0852                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
0853             lcdc_write(par->dma_end,
0854                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
0855             par->vsync_flag = 1;
0856             wake_up_interruptible(&par->vsync_wait);
0857         }
0858 
0859         if (stat & LCD_END_OF_FRAME1) {
0860             par->which_dma_channel_done = 1;
0861             lcdc_write(par->dma_start,
0862                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
0863             lcdc_write(par->dma_end,
0864                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
0865             par->vsync_flag = 1;
0866             wake_up_interruptible(&par->vsync_wait);
0867         }
0868 
0869         /* Set only when controller is disabled and at the end of
0870          * active frame
0871          */
0872         if (stat & BIT(0)) {
0873             frame_done_flag = 1;
0874             wake_up_interruptible(&frame_done_wq);
0875         }
0876     }
0877 
0878     lcdc_write(0, LCD_END_OF_INT_IND_REG);
0879     return IRQ_HANDLED;
0880 }
0881 
0882 /* IRQ handler for version 1 LCDC */
0883 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
0884 {
0885     struct da8xx_fb_par *par = arg;
0886     u32 stat = lcdc_read(LCD_STAT_REG);
0887     u32 reg_ras;
0888 
0889     if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
0890         lcd_disable_raster(DA8XX_FRAME_NOWAIT);
0891         lcdc_write(stat, LCD_STAT_REG);
0892         lcd_enable_raster();
0893     } else if (stat & LCD_PL_LOAD_DONE) {
0894         /*
0895          * Must disable raster before changing state of any control bit.
0896          * And also must be disabled before clearing the PL loading
0897          * interrupt via the following write to the status register. If
0898          * this is done after then one gets multiple PL done interrupts.
0899          */
0900         lcd_disable_raster(DA8XX_FRAME_NOWAIT);
0901 
0902         lcdc_write(stat, LCD_STAT_REG);
0903 
0904         /* Disable PL completion inerrupt */
0905         reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
0906         reg_ras &= ~LCD_V1_PL_INT_ENA;
0907         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
0908 
0909         /* Setup and start data loading mode */
0910         lcd_blit(LOAD_DATA, par);
0911     } else {
0912         lcdc_write(stat, LCD_STAT_REG);
0913 
0914         if (stat & LCD_END_OF_FRAME0) {
0915             par->which_dma_channel_done = 0;
0916             lcdc_write(par->dma_start,
0917                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
0918             lcdc_write(par->dma_end,
0919                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
0920             par->vsync_flag = 1;
0921             wake_up_interruptible(&par->vsync_wait);
0922         }
0923 
0924         if (stat & LCD_END_OF_FRAME1) {
0925             par->which_dma_channel_done = 1;
0926             lcdc_write(par->dma_start,
0927                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
0928             lcdc_write(par->dma_end,
0929                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
0930             par->vsync_flag = 1;
0931             wake_up_interruptible(&par->vsync_wait);
0932         }
0933     }
0934 
0935     return IRQ_HANDLED;
0936 }
0937 
0938 static int fb_check_var(struct fb_var_screeninfo *var,
0939             struct fb_info *info)
0940 {
0941     int err = 0;
0942     struct da8xx_fb_par *par = info->par;
0943     int bpp = var->bits_per_pixel >> 3;
0944     unsigned long line_size = var->xres_virtual * bpp;
0945 
0946     if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
0947         return -EINVAL;
0948 
0949     switch (var->bits_per_pixel) {
0950     case 1:
0951     case 8:
0952         var->red.offset = 0;
0953         var->red.length = 8;
0954         var->green.offset = 0;
0955         var->green.length = 8;
0956         var->blue.offset = 0;
0957         var->blue.length = 8;
0958         var->transp.offset = 0;
0959         var->transp.length = 0;
0960         var->nonstd = 0;
0961         break;
0962     case 4:
0963         var->red.offset = 0;
0964         var->red.length = 4;
0965         var->green.offset = 0;
0966         var->green.length = 4;
0967         var->blue.offset = 0;
0968         var->blue.length = 4;
0969         var->transp.offset = 0;
0970         var->transp.length = 0;
0971         var->nonstd = FB_NONSTD_REV_PIX_IN_B;
0972         break;
0973     case 16:        /* RGB 565 */
0974         var->red.offset = 11;
0975         var->red.length = 5;
0976         var->green.offset = 5;
0977         var->green.length = 6;
0978         var->blue.offset = 0;
0979         var->blue.length = 5;
0980         var->transp.offset = 0;
0981         var->transp.length = 0;
0982         var->nonstd = 0;
0983         break;
0984     case 24:
0985         var->red.offset = 16;
0986         var->red.length = 8;
0987         var->green.offset = 8;
0988         var->green.length = 8;
0989         var->blue.offset = 0;
0990         var->blue.length = 8;
0991         var->nonstd = 0;
0992         break;
0993     case 32:
0994         var->transp.offset = 24;
0995         var->transp.length = 8;
0996         var->red.offset = 16;
0997         var->red.length = 8;
0998         var->green.offset = 8;
0999         var->green.length = 8;
1000         var->blue.offset = 0;
1001         var->blue.length = 8;
1002         var->nonstd = 0;
1003         break;
1004     default:
1005         err = -EINVAL;
1006     }
1007 
1008     var->red.msb_right = 0;
1009     var->green.msb_right = 0;
1010     var->blue.msb_right = 0;
1011     var->transp.msb_right = 0;
1012 
1013     if (line_size * var->yres_virtual > par->vram_size)
1014         var->yres_virtual = par->vram_size / line_size;
1015 
1016     if (var->yres > var->yres_virtual)
1017         var->yres = var->yres_virtual;
1018 
1019     if (var->xres > var->xres_virtual)
1020         var->xres = var->xres_virtual;
1021 
1022     if (var->xres + var->xoffset > var->xres_virtual)
1023         var->xoffset = var->xres_virtual - var->xres;
1024     if (var->yres + var->yoffset > var->yres_virtual)
1025         var->yoffset = var->yres_virtual - var->yres;
1026 
1027     var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1028 
1029     return err;
1030 }
1031 
1032 #ifdef CONFIG_CPU_FREQ
1033 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
1034                      unsigned long val, void *data)
1035 {
1036     struct da8xx_fb_par *par;
1037 
1038     par = container_of(nb, struct da8xx_fb_par, freq_transition);
1039     if (val == CPUFREQ_POSTCHANGE) {
1040         if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1041             par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1042             lcd_disable_raster(DA8XX_FRAME_WAIT);
1043             da8xx_fb_calc_config_clk_divider(par, &par->mode);
1044             if (par->blank == FB_BLANK_UNBLANK)
1045                 lcd_enable_raster();
1046         }
1047     }
1048 
1049     return 0;
1050 }
1051 
1052 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1053 {
1054     par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1055 
1056     return cpufreq_register_notifier(&par->freq_transition,
1057                      CPUFREQ_TRANSITION_NOTIFIER);
1058 }
1059 
1060 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1061 {
1062     cpufreq_unregister_notifier(&par->freq_transition,
1063                     CPUFREQ_TRANSITION_NOTIFIER);
1064 }
1065 #endif
1066 
1067 static int fb_remove(struct platform_device *dev)
1068 {
1069     struct fb_info *info = platform_get_drvdata(dev);
1070     struct da8xx_fb_par *par = info->par;
1071     int ret;
1072 
1073 #ifdef CONFIG_CPU_FREQ
1074     lcd_da8xx_cpufreq_deregister(par);
1075 #endif
1076     if (par->lcd_supply) {
1077         ret = regulator_disable(par->lcd_supply);
1078         if (ret)
1079             return ret;
1080     }
1081 
1082     lcd_disable_raster(DA8XX_FRAME_WAIT);
1083     lcdc_write(0, LCD_RASTER_CTRL_REG);
1084 
1085     /* disable DMA  */
1086     lcdc_write(0, LCD_DMA_CTRL_REG);
1087 
1088     unregister_framebuffer(info);
1089     fb_dealloc_cmap(&info->cmap);
1090     pm_runtime_put_sync(&dev->dev);
1091     pm_runtime_disable(&dev->dev);
1092     framebuffer_release(info);
1093 
1094     return 0;
1095 }
1096 
1097 /*
1098  * Function to wait for vertical sync which for this LCD peripheral
1099  * translates into waiting for the current raster frame to complete.
1100  */
1101 static int fb_wait_for_vsync(struct fb_info *info)
1102 {
1103     struct da8xx_fb_par *par = info->par;
1104     int ret;
1105 
1106     /*
1107      * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1108      * race condition here where the ISR could have occurred just before or
1109      * just after this set. But since we are just coarsely waiting for
1110      * a frame to complete then that's OK. i.e. if the frame completed
1111      * just before this code executed then we have to wait another full
1112      * frame time but there is no way to avoid such a situation. On the
1113      * other hand if the frame completed just after then we don't need
1114      * to wait long at all. Either way we are guaranteed to return to the
1115      * user immediately after a frame completion which is all that is
1116      * required.
1117      */
1118     par->vsync_flag = 0;
1119     ret = wait_event_interruptible_timeout(par->vsync_wait,
1120                            par->vsync_flag != 0,
1121                            par->vsync_timeout);
1122     if (ret < 0)
1123         return ret;
1124     if (ret == 0)
1125         return -ETIMEDOUT;
1126 
1127     return 0;
1128 }
1129 
1130 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1131               unsigned long arg)
1132 {
1133     struct lcd_sync_arg sync_arg;
1134 
1135     switch (cmd) {
1136     case FBIOGET_CONTRAST:
1137     case FBIOPUT_CONTRAST:
1138     case FBIGET_BRIGHTNESS:
1139     case FBIPUT_BRIGHTNESS:
1140     case FBIGET_COLOR:
1141     case FBIPUT_COLOR:
1142         return -ENOTTY;
1143     case FBIPUT_HSYNC:
1144         if (copy_from_user(&sync_arg, (char *)arg,
1145                 sizeof(struct lcd_sync_arg)))
1146             return -EFAULT;
1147         lcd_cfg_horizontal_sync(sync_arg.back_porch,
1148                     sync_arg.pulse_width,
1149                     sync_arg.front_porch);
1150         break;
1151     case FBIPUT_VSYNC:
1152         if (copy_from_user(&sync_arg, (char *)arg,
1153                 sizeof(struct lcd_sync_arg)))
1154             return -EFAULT;
1155         lcd_cfg_vertical_sync(sync_arg.back_porch,
1156                     sync_arg.pulse_width,
1157                     sync_arg.front_porch);
1158         break;
1159     case FBIO_WAITFORVSYNC:
1160         return fb_wait_for_vsync(info);
1161     default:
1162         return -EINVAL;
1163     }
1164     return 0;
1165 }
1166 
1167 static int cfb_blank(int blank, struct fb_info *info)
1168 {
1169     struct da8xx_fb_par *par = info->par;
1170     int ret = 0;
1171 
1172     if (par->blank == blank)
1173         return 0;
1174 
1175     par->blank = blank;
1176     switch (blank) {
1177     case FB_BLANK_UNBLANK:
1178         lcd_enable_raster();
1179 
1180         if (par->lcd_supply) {
1181             ret = regulator_enable(par->lcd_supply);
1182             if (ret)
1183                 return ret;
1184         }
1185         break;
1186     case FB_BLANK_NORMAL:
1187     case FB_BLANK_VSYNC_SUSPEND:
1188     case FB_BLANK_HSYNC_SUSPEND:
1189     case FB_BLANK_POWERDOWN:
1190         if (par->lcd_supply) {
1191             ret = regulator_disable(par->lcd_supply);
1192             if (ret)
1193                 return ret;
1194         }
1195 
1196         lcd_disable_raster(DA8XX_FRAME_WAIT);
1197         break;
1198     default:
1199         ret = -EINVAL;
1200     }
1201 
1202     return ret;
1203 }
1204 
1205 /*
1206  * Set new x,y offsets in the virtual display for the visible area and switch
1207  * to the new mode.
1208  */
1209 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1210                  struct fb_info *fbi)
1211 {
1212     int ret = 0;
1213     struct fb_var_screeninfo new_var;
1214     struct da8xx_fb_par         *par = fbi->par;
1215     struct fb_fix_screeninfo    *fix = &fbi->fix;
1216     unsigned int end;
1217     unsigned int start;
1218     unsigned long irq_flags;
1219 
1220     if (var->xoffset != fbi->var.xoffset ||
1221             var->yoffset != fbi->var.yoffset) {
1222         memcpy(&new_var, &fbi->var, sizeof(new_var));
1223         new_var.xoffset = var->xoffset;
1224         new_var.yoffset = var->yoffset;
1225         if (fb_check_var(&new_var, fbi))
1226             ret = -EINVAL;
1227         else {
1228             memcpy(&fbi->var, &new_var, sizeof(new_var));
1229 
1230             start   = fix->smem_start +
1231                 new_var.yoffset * fix->line_length +
1232                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1233             end = start + fbi->var.yres * fix->line_length - 1;
1234             par->dma_start  = start;
1235             par->dma_end    = end;
1236             spin_lock_irqsave(&par->lock_for_chan_update,
1237                     irq_flags);
1238             if (par->which_dma_channel_done == 0) {
1239                 lcdc_write(par->dma_start,
1240                        LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1241                 lcdc_write(par->dma_end,
1242                        LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1243             } else if (par->which_dma_channel_done == 1) {
1244                 lcdc_write(par->dma_start,
1245                        LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1246                 lcdc_write(par->dma_end,
1247                        LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1248             }
1249             spin_unlock_irqrestore(&par->lock_for_chan_update,
1250                     irq_flags);
1251         }
1252     }
1253 
1254     return ret;
1255 }
1256 
1257 static int da8xxfb_set_par(struct fb_info *info)
1258 {
1259     struct da8xx_fb_par *par = info->par;
1260     int ret;
1261     bool raster = da8xx_fb_is_raster_enabled();
1262 
1263     if (raster)
1264         lcd_disable_raster(DA8XX_FRAME_WAIT);
1265 
1266     fb_var_to_videomode(&par->mode, &info->var);
1267 
1268     par->cfg.bpp = info->var.bits_per_pixel;
1269 
1270     info->fix.visual = (par->cfg.bpp <= 8) ?
1271                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1272     info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1273 
1274     ret = lcd_init(par, &par->cfg, &par->mode);
1275     if (ret < 0) {
1276         dev_err(par->dev, "lcd init failed\n");
1277         return ret;
1278     }
1279 
1280     par->dma_start = info->fix.smem_start +
1281              info->var.yoffset * info->fix.line_length +
1282              info->var.xoffset * info->var.bits_per_pixel / 8;
1283     par->dma_end   = par->dma_start +
1284              info->var.yres * info->fix.line_length - 1;
1285 
1286     lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1287     lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1288     lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1289     lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1290 
1291     if (raster)
1292         lcd_enable_raster();
1293 
1294     return 0;
1295 }
1296 
1297 static const struct fb_ops da8xx_fb_ops = {
1298     .owner = THIS_MODULE,
1299     .fb_check_var = fb_check_var,
1300     .fb_set_par = da8xxfb_set_par,
1301     .fb_setcolreg = fb_setcolreg,
1302     .fb_pan_display = da8xx_pan_display,
1303     .fb_ioctl = fb_ioctl,
1304     .fb_fillrect = cfb_fillrect,
1305     .fb_copyarea = cfb_copyarea,
1306     .fb_imageblit = cfb_imageblit,
1307     .fb_blank = cfb_blank,
1308 };
1309 
1310 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
1311 {
1312     struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
1313     struct fb_videomode *lcdc_info;
1314     int i;
1315 
1316     for (i = 0, lcdc_info = known_lcd_panels;
1317         i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
1318         if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1319             break;
1320     }
1321 
1322     if (i == ARRAY_SIZE(known_lcd_panels)) {
1323         dev_err(&dev->dev, "no panel found\n");
1324         return NULL;
1325     }
1326     dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
1327 
1328     return lcdc_info;
1329 }
1330 
1331 static int fb_probe(struct platform_device *device)
1332 {
1333     struct da8xx_lcdc_platform_data *fb_pdata =
1334                         dev_get_platdata(&device->dev);
1335     struct lcd_ctrl_config *lcd_cfg;
1336     struct fb_videomode *lcdc_info;
1337     struct fb_info *da8xx_fb_info;
1338     struct da8xx_fb_par *par;
1339     struct clk *tmp_lcdc_clk;
1340     int ret;
1341     unsigned long ulcm;
1342 
1343     if (fb_pdata == NULL) {
1344         dev_err(&device->dev, "Can not get platform data\n");
1345         return -ENOENT;
1346     }
1347 
1348     lcdc_info = da8xx_fb_get_videomode(device);
1349     if (lcdc_info == NULL)
1350         return -ENODEV;
1351 
1352     da8xx_fb_reg_base = devm_platform_ioremap_resource(device, 0);
1353     if (IS_ERR(da8xx_fb_reg_base))
1354         return PTR_ERR(da8xx_fb_reg_base);
1355 
1356     tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
1357     if (IS_ERR(tmp_lcdc_clk))
1358         return dev_err_probe(&device->dev, PTR_ERR(tmp_lcdc_clk),
1359                      "Can not get device clock\n");
1360 
1361     pm_runtime_enable(&device->dev);
1362     pm_runtime_get_sync(&device->dev);
1363 
1364     /* Determine LCD IP Version */
1365     switch (lcdc_read(LCD_PID_REG)) {
1366     case 0x4C100102:
1367         lcd_revision = LCD_VERSION_1;
1368         break;
1369     case 0x4F200800:
1370     case 0x4F201000:
1371         lcd_revision = LCD_VERSION_2;
1372         break;
1373     default:
1374         dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1375                 "defaulting to LCD revision 1\n",
1376                 lcdc_read(LCD_PID_REG));
1377         lcd_revision = LCD_VERSION_1;
1378         break;
1379     }
1380 
1381     lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1382 
1383     if (!lcd_cfg) {
1384         ret = -EINVAL;
1385         goto err_pm_runtime_disable;
1386     }
1387 
1388     da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1389                     &device->dev);
1390     if (!da8xx_fb_info) {
1391         ret = -ENOMEM;
1392         goto err_pm_runtime_disable;
1393     }
1394 
1395     par = da8xx_fb_info->par;
1396     par->dev = &device->dev;
1397     par->lcdc_clk = tmp_lcdc_clk;
1398     par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1399 
1400     par->lcd_supply = devm_regulator_get_optional(&device->dev, "lcd");
1401     if (IS_ERR(par->lcd_supply)) {
1402         if (PTR_ERR(par->lcd_supply) == -EPROBE_DEFER) {
1403             ret = -EPROBE_DEFER;
1404             goto err_release_fb;
1405         }
1406 
1407         par->lcd_supply = NULL;
1408     } else {
1409         ret = regulator_enable(par->lcd_supply);
1410         if (ret)
1411             goto err_release_fb;
1412     }
1413 
1414     fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1415     par->cfg = *lcd_cfg;
1416 
1417     da8xx_fb_lcd_reset();
1418 
1419     /* allocate frame buffer */
1420     par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1421     ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1422     par->vram_size = roundup(par->vram_size/8, ulcm);
1423     par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1424 
1425     par->vram_virt = dmam_alloc_coherent(par->dev,
1426                          par->vram_size,
1427                          &par->vram_phys,
1428                          GFP_KERNEL | GFP_DMA);
1429     if (!par->vram_virt) {
1430         dev_err(&device->dev,
1431             "GLCD: kmalloc for frame buffer failed\n");
1432         ret = -EINVAL;
1433         goto err_release_fb;
1434     }
1435 
1436     da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1437     da8xx_fb_fix.smem_start    = par->vram_phys;
1438     da8xx_fb_fix.smem_len      = par->vram_size;
1439     da8xx_fb_fix.line_length   = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1440 
1441     par->dma_start = par->vram_phys;
1442     par->dma_end   = par->dma_start + lcdc_info->yres *
1443         da8xx_fb_fix.line_length - 1;
1444 
1445     /* allocate palette buffer */
1446     par->v_palette_base = dmam_alloc_coherent(par->dev, PALETTE_SIZE,
1447                           &par->p_palette_base,
1448                           GFP_KERNEL | GFP_DMA);
1449     if (!par->v_palette_base) {
1450         dev_err(&device->dev,
1451             "GLCD: kmalloc for palette buffer failed\n");
1452         ret = -EINVAL;
1453         goto err_release_fb;
1454     }
1455 
1456     par->irq = platform_get_irq(device, 0);
1457     if (par->irq < 0) {
1458         ret = -ENOENT;
1459         goto err_release_fb;
1460     }
1461 
1462     da8xx_fb_var.grayscale =
1463         lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1464     da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1465 
1466     /* Initialize fbinfo */
1467     da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1468     da8xx_fb_info->fix = da8xx_fb_fix;
1469     da8xx_fb_info->var = da8xx_fb_var;
1470     da8xx_fb_info->fbops = &da8xx_fb_ops;
1471     da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1472     da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1473                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1474 
1475     ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1476     if (ret)
1477         goto err_release_fb;
1478     da8xx_fb_info->cmap.len = par->palette_sz;
1479 
1480     /* initialize var_screeninfo */
1481     da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1482     fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1483 
1484     platform_set_drvdata(device, da8xx_fb_info);
1485 
1486     /* initialize the vsync wait queue */
1487     init_waitqueue_head(&par->vsync_wait);
1488     par->vsync_timeout = HZ / 5;
1489     par->which_dma_channel_done = -1;
1490     spin_lock_init(&par->lock_for_chan_update);
1491 
1492     /* Register the Frame Buffer  */
1493     if (register_framebuffer(da8xx_fb_info) < 0) {
1494         dev_err(&device->dev,
1495             "GLCD: Frame Buffer Registration Failed!\n");
1496         ret = -EINVAL;
1497         goto err_dealloc_cmap;
1498     }
1499 
1500 #ifdef CONFIG_CPU_FREQ
1501     ret = lcd_da8xx_cpufreq_register(par);
1502     if (ret) {
1503         dev_err(&device->dev, "failed to register cpufreq\n");
1504         goto err_cpu_freq;
1505     }
1506 #endif
1507 
1508     if (lcd_revision == LCD_VERSION_1)
1509         lcdc_irq_handler = lcdc_irq_handler_rev01;
1510     else {
1511         init_waitqueue_head(&frame_done_wq);
1512         lcdc_irq_handler = lcdc_irq_handler_rev02;
1513     }
1514 
1515     ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1516                    DRIVER_NAME, par);
1517     if (ret)
1518         goto irq_freq;
1519     return 0;
1520 
1521 irq_freq:
1522 #ifdef CONFIG_CPU_FREQ
1523     lcd_da8xx_cpufreq_deregister(par);
1524 err_cpu_freq:
1525 #endif
1526     unregister_framebuffer(da8xx_fb_info);
1527 
1528 err_dealloc_cmap:
1529     fb_dealloc_cmap(&da8xx_fb_info->cmap);
1530 
1531 err_release_fb:
1532     framebuffer_release(da8xx_fb_info);
1533 
1534 err_pm_runtime_disable:
1535     pm_runtime_put_sync(&device->dev);
1536     pm_runtime_disable(&device->dev);
1537 
1538     return ret;
1539 }
1540 
1541 #ifdef CONFIG_PM_SLEEP
1542 static struct lcdc_context {
1543     u32 clk_enable;
1544     u32 ctrl;
1545     u32 dma_ctrl;
1546     u32 raster_timing_0;
1547     u32 raster_timing_1;
1548     u32 raster_timing_2;
1549     u32 int_enable_set;
1550     u32 dma_frm_buf_base_addr_0;
1551     u32 dma_frm_buf_ceiling_addr_0;
1552     u32 dma_frm_buf_base_addr_1;
1553     u32 dma_frm_buf_ceiling_addr_1;
1554     u32 raster_ctrl;
1555 } reg_context;
1556 
1557 static void lcd_context_save(void)
1558 {
1559     if (lcd_revision == LCD_VERSION_2) {
1560         reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1561         reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1562     }
1563 
1564     reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1565     reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1566     reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1567     reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1568     reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1569     reg_context.dma_frm_buf_base_addr_0 =
1570         lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1571     reg_context.dma_frm_buf_ceiling_addr_0 =
1572         lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1573     reg_context.dma_frm_buf_base_addr_1 =
1574         lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1575     reg_context.dma_frm_buf_ceiling_addr_1 =
1576         lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1577     reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1578     return;
1579 }
1580 
1581 static void lcd_context_restore(void)
1582 {
1583     if (lcd_revision == LCD_VERSION_2) {
1584         lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1585         lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1586     }
1587 
1588     lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1589     lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1590     lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1591     lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1592     lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1593     lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1594             LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1595     lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1596             LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1597     lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1598             LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1599     lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1600             LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1601     lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1602     return;
1603 }
1604 
1605 static int fb_suspend(struct device *dev)
1606 {
1607     struct fb_info *info = dev_get_drvdata(dev);
1608     struct da8xx_fb_par *par = info->par;
1609     int ret;
1610 
1611     console_lock();
1612     if (par->lcd_supply) {
1613         ret = regulator_disable(par->lcd_supply);
1614         if (ret)
1615             return ret;
1616     }
1617 
1618     fb_set_suspend(info, 1);
1619     lcd_disable_raster(DA8XX_FRAME_WAIT);
1620     lcd_context_save();
1621     pm_runtime_put_sync(dev);
1622     console_unlock();
1623 
1624     return 0;
1625 }
1626 static int fb_resume(struct device *dev)
1627 {
1628     struct fb_info *info = dev_get_drvdata(dev);
1629     struct da8xx_fb_par *par = info->par;
1630     int ret;
1631 
1632     console_lock();
1633     pm_runtime_get_sync(dev);
1634     lcd_context_restore();
1635     if (par->blank == FB_BLANK_UNBLANK) {
1636         lcd_enable_raster();
1637 
1638         if (par->lcd_supply) {
1639             ret = regulator_enable(par->lcd_supply);
1640             if (ret)
1641                 return ret;
1642         }
1643     }
1644 
1645     fb_set_suspend(info, 0);
1646     console_unlock();
1647 
1648     return 0;
1649 }
1650 #endif
1651 
1652 static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume);
1653 
1654 static struct platform_driver da8xx_fb_driver = {
1655     .probe = fb_probe,
1656     .remove = fb_remove,
1657     .driver = {
1658            .name = DRIVER_NAME,
1659            .pm  = &fb_pm_ops,
1660            },
1661 };
1662 module_platform_driver(da8xx_fb_driver);
1663 
1664 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1665 MODULE_AUTHOR("Texas Instruments");
1666 MODULE_LICENSE("GPL");
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