video/fbdev/chipsfb.c

0001 /*
0002  *  drivers/video/chipsfb.c -- frame buffer device for
0003  *  Chips & Technologies 65550 chip.
0004  *
0005  *  Copyright (C) 1998-2002 Paul Mackerras
0006  *
0007  *  This file is derived from the Powermac "chips" driver:
0008  *  Copyright (C) 1997 Fabio Riccardi.
0009  *  And from the frame buffer device for Open Firmware-initialized devices:
0010  *  Copyright (C) 1997 Geert Uytterhoeven.
0011  *
0012  *  This file is subject to the terms and conditions of the GNU General Public
0013  *  License. See the file COPYING in the main directory of this archive for
0014  *  more details.
0015  */
0016
0017 #include <linux/module.h>
0018 #include <linux/kernel.h>
0019 #include <linux/errno.h>
0020 #include <linux/string.h>
0021 #include <linux/mm.h>
0022 #include <linux/vmalloc.h>
0023 #include <linux/delay.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/fb.h>
0026 #include <linux/pm.h>
0027 #include <linux/init.h>
0028 #include <linux/pci.h>
0029 #include <linux/console.h>
0030
0031 #ifdef CONFIG_PMAC_BACKLIGHT
0032 #include <asm/backlight.h>
0033 #endif
0034
0035 /*
0036  * Since we access the display with inb/outb to fixed port numbers,
0037  * we can only handle one 6555x chip.  -- paulus
0038  */
0039 #define write_ind(num, val, ap, dp) do { \
0040     outb((num), (ap)); outb((val), (dp)); \
0041 } while (0)
0042 #define read_ind(num, var, ap, dp)  do { \
0043     outb((num), (ap)); var = inb((dp)); \
0044 } while (0)
0045
0046 /* extension registers */
0047 #define write_xr(num, val)  write_ind(num, val, 0x3d6, 0x3d7)
0048 #define read_xr(num, var)   read_ind(num, var, 0x3d6, 0x3d7)
0049 /* flat panel registers */
0050 #define write_fr(num, val)  write_ind(num, val, 0x3d0, 0x3d1)
0051 #define read_fr(num, var)   read_ind(num, var, 0x3d0, 0x3d1)
0052 /* CRTC registers */
0053 #define write_cr(num, val)  write_ind(num, val, 0x3d4, 0x3d5)
0054 #define read_cr(num, var)   read_ind(num, var, 0x3d4, 0x3d5)
0055 /* graphics registers */
0056 #define write_gr(num, val)  write_ind(num, val, 0x3ce, 0x3cf)
0057 #define read_gr(num, var)   read_ind(num, var, 0x3ce, 0x3cf)
0058 /* sequencer registers */
0059 #define write_sr(num, val)  write_ind(num, val, 0x3c4, 0x3c5)
0060 #define read_sr(num, var)   read_ind(num, var, 0x3c4, 0x3c5)
0061 /* attribute registers - slightly strange */
0062 #define write_ar(num, val)  do { \
0063     inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
0064 } while (0)
0065 #define read_ar(num, var)   do { \
0066     inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
0067 } while (0)
0068
0069 /*
0070  * Exported functions
0071  */
0072 int chips_init(void);
0073
0074 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
0075 static int chipsfb_check_var(struct fb_var_screeninfo *var,
0076                  struct fb_info *info);
0077 static int chipsfb_set_par(struct fb_info *info);
0078 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
0079                  u_int transp, struct fb_info *info);
0080 static int chipsfb_blank(int blank, struct fb_info *info);
0081
0082 static const struct fb_ops chipsfb_ops = {
0083     .owner      = THIS_MODULE,
0084     .fb_check_var   = chipsfb_check_var,
0085     .fb_set_par = chipsfb_set_par,
0086     .fb_setcolreg   = chipsfb_setcolreg,
0087     .fb_blank   = chipsfb_blank,
0088     .fb_fillrect    = cfb_fillrect,
0089     .fb_copyarea    = cfb_copyarea,
0090     .fb_imageblit   = cfb_imageblit,
0091 };
0092
0093 static int chipsfb_check_var(struct fb_var_screeninfo *var,
0094                  struct fb_info *info)
0095 {
0096     if (var->xres > 800 || var->yres > 600
0097         || var->xres_virtual > 800 || var->yres_virtual > 600
0098         || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
0099         || var->nonstd
0100         || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
0101         return -EINVAL;
0102
0103     var->xres = var->xres_virtual = 800;
0104     var->yres = var->yres_virtual = 600;
0105
0106     return 0;
0107 }
0108
0109 static int chipsfb_set_par(struct fb_info *info)
0110 {
0111     if (info->var.bits_per_pixel == 16) {
0112         write_cr(0x13, 200);        // Set line length (doublewords)
0113         write_xr(0x81, 0x14);       // 15 bit (555) color mode
0114         write_xr(0x82, 0x00);       // Disable palettes
0115         write_xr(0x20, 0x10);       // 16 bit blitter mode
0116
0117         info->fix.line_length = 800*2;
0118         info->fix.visual = FB_VISUAL_TRUECOLOR;
0119
0120         info->var.red.offset = 10;
0121         info->var.green.offset = 5;
0122         info->var.blue.offset = 0;
0123         info->var.red.length = info->var.green.length =
0124             info->var.blue.length = 5;
0125
0126     } else {
0127         /* p->var.bits_per_pixel == 8 */
0128         write_cr(0x13, 100);        // Set line length (doublewords)
0129         write_xr(0x81, 0x12);       // 8 bit color mode
0130         write_xr(0x82, 0x08);       // Graphics gamma enable
0131         write_xr(0x20, 0x00);       // 8 bit blitter mode
0132
0133         info->fix.line_length = 800;
0134         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
0135
0136         info->var.red.offset = info->var.green.offset =
0137             info->var.blue.offset = 0;
0138         info->var.red.length = info->var.green.length =
0139             info->var.blue.length = 8;
0140
0141     }
0142     return 0;
0143 }
0144
0145 static int chipsfb_blank(int blank, struct fb_info *info)
0146 {
0147     return 1;   /* get fb_blank to set the colormap to all black */
0148 }
0149
0150 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
0151                  u_int transp, struct fb_info *info)
0152 {
0153     if (regno > 255)
0154         return 1;
0155     red >>= 8;
0156     green >>= 8;
0157     blue >>= 8;
0158     outb(regno, 0x3c8);
0159     udelay(1);
0160     outb(red, 0x3c9);
0161     outb(green, 0x3c9);
0162     outb(blue, 0x3c9);
0163
0164     return 0;
0165 }
0166
0167 struct chips_init_reg {
0168     unsigned char addr;
0169     unsigned char data;
0170 };
0171
0172 static struct chips_init_reg chips_init_sr[] = {
0173     { 0x00, 0x03 },
0174     { 0x01, 0x01 },
0175     { 0x02, 0x0f },
0176     { 0x04, 0x0e }
0177 };
0178
0179 static struct chips_init_reg chips_init_gr[] = {
0180     { 0x05, 0x00 },
0181     { 0x06, 0x0d },
0182     { 0x08, 0xff }
0183 };
0184
0185 static struct chips_init_reg chips_init_ar[] = {
0186     { 0x10, 0x01 },
0187     { 0x12, 0x0f },
0188     { 0x13, 0x00 }
0189 };
0190
0191 static struct chips_init_reg chips_init_cr[] = {
0192     { 0x00, 0x7f },
0193     { 0x01, 0x63 },
0194     { 0x02, 0x63 },
0195     { 0x03, 0x83 },
0196     { 0x04, 0x66 },
0197     { 0x05, 0x10 },
0198     { 0x06, 0x72 },
0199     { 0x07, 0x3e },
0200     { 0x08, 0x00 },
0201     { 0x09, 0x40 },
0202     { 0x0c, 0x00 },
0203     { 0x0d, 0x00 },
0204     { 0x10, 0x59 },
0205     { 0x11, 0x0d },
0206     { 0x12, 0x57 },
0207     { 0x13, 0x64 },
0208     { 0x14, 0x00 },
0209     { 0x15, 0x57 },
0210     { 0x16, 0x73 },
0211     { 0x17, 0xe3 },
0212     { 0x18, 0xff },
0213     { 0x30, 0x02 },
0214     { 0x31, 0x02 },
0215     { 0x32, 0x02 },
0216     { 0x33, 0x02 },
0217     { 0x40, 0x00 },
0218     { 0x41, 0x00 },
0219     { 0x40, 0x80 }
0220 };
0221
0222 static struct chips_init_reg chips_init_fr[] = {
0223     { 0x01, 0x02 },
0224     { 0x03, 0x08 },
0225     { 0x04, 0x81 },
0226     { 0x05, 0x21 },
0227     { 0x08, 0x0c },
0228     { 0x0a, 0x74 },
0229     { 0x0b, 0x11 },
0230     { 0x10, 0x0c },
0231     { 0x11, 0xe0 },
0232     /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
0233     { 0x20, 0x63 },
0234     { 0x21, 0x68 },
0235     { 0x22, 0x19 },
0236     { 0x23, 0x7f },
0237     { 0x24, 0x68 },
0238     { 0x26, 0x00 },
0239     { 0x27, 0x0f },
0240     { 0x30, 0x57 },
0241     { 0x31, 0x58 },
0242     { 0x32, 0x0d },
0243     { 0x33, 0x72 },
0244     { 0x34, 0x02 },
0245     { 0x35, 0x22 },
0246     { 0x36, 0x02 },
0247     { 0x37, 0x00 }
0248 };
0249
0250 static struct chips_init_reg chips_init_xr[] = {
0251     { 0xce, 0x00 },     /* set default memory clock */
0252     { 0xcc, 0x43 },     /* memory clock ratio */
0253     { 0xcd, 0x18 },
0254     { 0xce, 0xa1 },
0255     { 0xc8, 0x84 },
0256     { 0xc9, 0x0a },
0257     { 0xca, 0x00 },
0258     { 0xcb, 0x20 },
0259     { 0xcf, 0x06 },
0260     { 0xd0, 0x0e },
0261     { 0x09, 0x01 },
0262     { 0x0a, 0x02 },
0263     { 0x0b, 0x01 },
0264     { 0x20, 0x00 },
0265     { 0x40, 0x03 },
0266     { 0x41, 0x01 },
0267     { 0x42, 0x00 },
0268     { 0x80, 0x82 },
0269     { 0x81, 0x12 },
0270     { 0x82, 0x08 },
0271     { 0xa0, 0x00 },
0272     { 0xa8, 0x00 }
0273 };
0274
0275 static void chips_hw_init(void)
0276 {
0277     int i;
0278
0279     for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
0280         write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
0281     outb(0x29, 0x3c2); /* set misc output reg */
0282     for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
0283         write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
0284     for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
0285         write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
0286     for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
0287         write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
0288     for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
0289         write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
0290     for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
0291         write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
0292 }
0293
0294 static const struct fb_fix_screeninfo chipsfb_fix = {
0295     .id =       "C&T 65550",
0296     .type =     FB_TYPE_PACKED_PIXELS,
0297     .visual =   FB_VISUAL_PSEUDOCOLOR,
0298     .accel =    FB_ACCEL_NONE,
0299     .line_length =  800,
0300
0301 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
0302 // * "3500" PowerBook G3 (the original PB G3) has 2MB.
0303 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
0304 //   Motherboard actually supports 2MB -- there are two blank locations
0305 //   for a second pair of DRAMs.  (Thanks, Apple!)
0306 // * 3400 has 1MB (I think).  Don't know if it's expandable.
0307 // -- Tim Seufert
0308     .smem_len = 0x100000,   /* 1MB */
0309 };
0310
0311 static const struct fb_var_screeninfo chipsfb_var = {
0312     .xres = 800,
0313     .yres = 600,
0314     .xres_virtual = 800,
0315     .yres_virtual = 600,
0316     .bits_per_pixel = 8,
0317     .red = { .length = 8 },
0318     .green = { .length = 8 },
0319     .blue = { .length = 8 },
0320     .height = -1,
0321     .width = -1,
0322     .vmode = FB_VMODE_NONINTERLACED,
0323     .pixclock = 10000,
0324     .left_margin = 16,
0325     .right_margin = 16,
0326     .upper_margin = 16,
0327     .lower_margin = 16,
0328     .hsync_len = 8,
0329     .vsync_len = 8,
0330 };
0331
0332 static void init_chips(struct fb_info *p, unsigned long addr)
0333 {
0334     fb_memset(p->screen_base, 0, 0x100000);
0335
0336     p->fix = chipsfb_fix;
0337     p->fix.smem_start = addr;
0338
0339     p->var = chipsfb_var;
0340
0341     p->fbops = &chipsfb_ops;
0342     p->flags = FBINFO_DEFAULT;
0343
0344     fb_alloc_cmap(&p->cmap, 256, 0);
0345
0346     chips_hw_init();
0347 }
0348
0349 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
0350 {
0351     struct fb_info *p;
0352     unsigned long addr;
0353     unsigned short cmd;
0354     int rc = -ENODEV;
0355
0356     if (pci_enable_device(dp) < 0) {
0357         dev_err(&dp->dev, "Cannot enable PCI device\n");
0358         goto err_out;
0359     }
0360
0361     if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
0362         goto err_disable;
0363     addr = pci_resource_start(dp, 0);
0364     if (addr == 0)
0365         goto err_disable;
0366
0367     p = framebuffer_alloc(0, &dp->dev);
0368     if (p == NULL) {
0369         rc = -ENOMEM;
0370         goto err_disable;
0371     }
0372
0373     if (pci_request_region(dp, 0, "chipsfb") != 0) {
0374         dev_err(&dp->dev, "Cannot request framebuffer\n");
0375         rc = -EBUSY;
0376         goto err_release_fb;
0377     }
0378
0379 #ifdef __BIG_ENDIAN
0380     addr += 0x800000;   // Use big-endian aperture
0381 #endif
0382
0383     /* we should use pci_enable_device here, but,
0384        the device doesn't declare its I/O ports in its BARs
0385        so pci_enable_device won't turn on I/O responses */
0386     pci_read_config_word(dp, PCI_COMMAND, &cmd);
0387     cmd |= 3;   /* enable memory and IO space */
0388     pci_write_config_word(dp, PCI_COMMAND, cmd);
0389
0390 #ifdef CONFIG_PMAC_BACKLIGHT
0391     /* turn on the backlight */
0392     mutex_lock(&pmac_backlight_mutex);
0393     if (pmac_backlight) {
0394         pmac_backlight->props.power = FB_BLANK_UNBLANK;
0395         backlight_update_status(pmac_backlight);
0396     }
0397     mutex_unlock(&pmac_backlight_mutex);
0398 #endif /* CONFIG_PMAC_BACKLIGHT */
0399
0400 #ifdef CONFIG_PPC
0401     p->screen_base = ioremap_wc(addr, 0x200000);
0402 #else
0403     p->screen_base = ioremap(addr, 0x200000);
0404 #endif
0405     if (p->screen_base == NULL) {
0406         dev_err(&dp->dev, "Cannot map framebuffer\n");
0407         rc = -ENOMEM;
0408         goto err_release_pci;
0409     }
0410
0411     pci_set_drvdata(dp, p);
0412
0413     init_chips(p, addr);
0414
0415     if (register_framebuffer(p) < 0) {
0416         dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
0417         goto err_unmap;
0418     }
0419
0420     dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
0421          " (%dK RAM detected)\n",
0422          p->node, p->fix.smem_len / 1024);
0423
0424     return 0;
0425
0426  err_unmap:
0427     iounmap(p->screen_base);
0428  err_release_pci:
0429     pci_release_region(dp, 0);
0430  err_release_fb:
0431     framebuffer_release(p);
0432  err_disable:
0433     pci_disable_device(dp);
0434  err_out:
0435     return rc;
0436 }
0437
0438 static void chipsfb_remove(struct pci_dev *dp)
0439 {
0440     struct fb_info *p = pci_get_drvdata(dp);
0441
0442     if (p->screen_base == NULL)
0443         return;
0444     unregister_framebuffer(p);
0445     iounmap(p->screen_base);
0446     p->screen_base = NULL;
0447     pci_release_region(dp, 0);
0448 }
0449
0450 #ifdef CONFIG_PM
0451 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
0452 {
0453         struct fb_info *p = pci_get_drvdata(pdev);
0454
0455     if (state.event == pdev->dev.power.power_state.event)
0456         return 0;
0457     if (!(state.event & PM_EVENT_SLEEP))
0458         goto done;
0459
0460     console_lock();
0461     chipsfb_blank(1, p);
0462     fb_set_suspend(p, 1);
0463     console_unlock();
0464  done:
0465     pdev->dev.power.power_state = state;
0466     return 0;
0467 }
0468
0469 static int chipsfb_pci_resume(struct pci_dev *pdev)
0470 {
0471         struct fb_info *p = pci_get_drvdata(pdev);
0472
0473     console_lock();
0474     fb_set_suspend(p, 0);
0475     chipsfb_blank(0, p);
0476     console_unlock();
0477
0478     pdev->dev.power.power_state = PMSG_ON;
0479     return 0;
0480 }
0481 #endif /* CONFIG_PM */
0482
0483
0484 static struct pci_device_id chipsfb_pci_tbl[] = {
0485     { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
0486     { 0 }
0487 };
0488
0489 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
0490
0491 static struct pci_driver chipsfb_driver = {
0492     .name =     "chipsfb",
0493     .id_table = chipsfb_pci_tbl,
0494     .probe =    chipsfb_pci_init,
0495     .remove =   chipsfb_remove,
0496 #ifdef CONFIG_PM
0497     .suspend =  chipsfb_pci_suspend,
0498     .resume =   chipsfb_pci_resume,
0499 #endif
0500 };
0501
0502 int __init chips_init(void)
0503 {
0504     if (fb_get_options("chipsfb", NULL))
0505         return -ENODEV;
0506
0507     return pci_register_driver(&chipsfb_driver);
0508 }
0509
0510 module_init(chips_init);
0511
0512 static void __exit chipsfb_exit(void)
0513 {
0514     pci_unregister_driver(&chipsfb_driver);
0515 }
0516
0517 MODULE_LICENSE("GPL");