video/fbdev/cg3.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* cg3.c: CGTHREE frame buffer driver
0003  *
0004  * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
0005  * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
0006  * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
0007  * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
0008  *
0009  * Driver layout based loosely on tgafb.c, see that file for credits.
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/kernel.h>
0014 #include <linux/errno.h>
0015 #include <linux/string.h>
0016 #include <linux/delay.h>
0017 #include <linux/init.h>
0018 #include <linux/fb.h>
0019 #include <linux/mm.h>
0020 #include <linux/of_device.h>
0021
0022 #include <asm/io.h>
0023 #include <asm/fbio.h>
0024
0025 #include "sbuslib.h"
0026
0027 /*
0028  * Local functions.
0029  */
0030
0031 static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
0032              unsigned, struct fb_info *);
0033 static int cg3_blank(int, struct fb_info *);
0034
0035 static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
0036 static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
0037
0038 /*
0039  *  Frame buffer operations
0040  */
0041
0042 static const struct fb_ops cg3_ops = {
0043     .owner          = THIS_MODULE,
0044     .fb_setcolreg       = cg3_setcolreg,
0045     .fb_blank       = cg3_blank,
0046     .fb_fillrect        = cfb_fillrect,
0047     .fb_copyarea        = cfb_copyarea,
0048     .fb_imageblit       = cfb_imageblit,
0049     .fb_mmap        = cg3_mmap,
0050     .fb_ioctl       = cg3_ioctl,
0051 #ifdef CONFIG_COMPAT
0052     .fb_compat_ioctl    = sbusfb_compat_ioctl,
0053 #endif
0054 };
0055
0056
0057 /* Control Register Constants */
0058 #define CG3_CR_ENABLE_INTS      0x80
0059 #define CG3_CR_ENABLE_VIDEO     0x40
0060 #define CG3_CR_ENABLE_TIMING    0x20
0061 #define CG3_CR_ENABLE_CURCMP    0x10
0062 #define CG3_CR_XTAL_MASK        0x0c
0063 #define CG3_CR_DIVISOR_MASK     0x03
0064
0065 /* Status Register Constants */
0066 #define CG3_SR_PENDING_INT      0x80
0067 #define CG3_SR_RES_MASK         0x70
0068 #define CG3_SR_1152_900_76_A    0x40
0069 #define CG3_SR_1152_900_76_B    0x60
0070 #define CG3_SR_ID_MASK          0x0f
0071 #define CG3_SR_ID_COLOR         0x01
0072 #define CG3_SR_ID_MONO          0x02
0073 #define CG3_SR_ID_MONO_ECL      0x03
0074
0075 enum cg3_type {
0076     CG3_AT_66HZ = 0,
0077     CG3_AT_76HZ,
0078     CG3_RDI
0079 };
0080
0081 struct bt_regs {
0082     u32 addr;
0083     u32 color_map;
0084     u32 control;
0085     u32 cursor;
0086 };
0087
0088 struct cg3_regs {
0089     struct bt_regs  cmap;
0090     u8  control;
0091     u8  status;
0092     u8  cursor_start;
0093     u8  cursor_end;
0094     u8  h_blank_start;
0095     u8  h_blank_end;
0096     u8  h_sync_start;
0097     u8  h_sync_end;
0098     u8  comp_sync_end;
0099     u8  v_blank_start_high;
0100     u8  v_blank_start_low;
0101     u8  v_blank_end;
0102     u8  v_sync_start;
0103     u8  v_sync_end;
0104     u8  xfer_holdoff_start;
0105     u8  xfer_holdoff_end;
0106 };
0107
0108 /* Offset of interesting structures in the OBIO space */
0109 #define CG3_REGS_OFFSET      0x400000UL
0110 #define CG3_RAM_OFFSET       0x800000UL
0111
0112 struct cg3_par {
0113     spinlock_t      lock;
0114     struct cg3_regs     __iomem *regs;
0115     u32         sw_cmap[((256 * 3) + 3) / 4];
0116
0117     u32         flags;
0118 #define CG3_FLAG_BLANKED    0x00000001
0119 #define CG3_FLAG_RDI        0x00000002
0120
0121     unsigned long       which_io;
0122 };
0123
0124 /**
0125  *      cg3_setcolreg - Optional function. Sets a color register.
0126  *      @regno: boolean, 0 copy local, 1 get_user() function
0127  *      @red: frame buffer colormap structure
0128  *      @green: The green value which can be up to 16 bits wide
0129  *      @blue:  The blue value which can be up to 16 bits wide.
0130  *      @transp: If supported the alpha value which can be up to 16 bits wide.
0131  *      @info: frame buffer info structure
0132  *
0133  * The cg3 palette is loaded with 4 color values at each time
0134  * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
0135  * We keep a sw copy of the hw cmap to assist us in this esoteric
0136  * loading procedure.
0137  */
0138 static int cg3_setcolreg(unsigned regno,
0139              unsigned red, unsigned green, unsigned blue,
0140              unsigned transp, struct fb_info *info)
0141 {
0142     struct cg3_par *par = (struct cg3_par *) info->par;
0143     struct bt_regs __iomem *bt = &par->regs->cmap;
0144     unsigned long flags;
0145     u32 *p32;
0146     u8 *p8;
0147     int count;
0148
0149     if (regno >= 256)
0150         return 1;
0151
0152     red >>= 8;
0153     green >>= 8;
0154     blue >>= 8;
0155
0156     spin_lock_irqsave(&par->lock, flags);
0157
0158     p8 = (u8 *)par->sw_cmap + (regno * 3);
0159     p8[0] = red;
0160     p8[1] = green;
0161     p8[2] = blue;
0162
0163 #define D4M3(x) ((((x)>>2)<<1) + ((x)>>2))      /* (x/4)*3 */
0164 #define D4M4(x) ((x)&~0x3)                      /* (x/4)*4 */
0165
0166     count = 3;
0167     p32 = &par->sw_cmap[D4M3(regno)];
0168     sbus_writel(D4M4(regno), &bt->addr);
0169     while (count--)
0170         sbus_writel(*p32++, &bt->color_map);
0171
0172 #undef D4M3
0173 #undef D4M4
0174
0175     spin_unlock_irqrestore(&par->lock, flags);
0176
0177     return 0;
0178 }
0179
0180 /**
0181  *      cg3_blank - Optional function.  Blanks the display.
0182  *      @blank: the blank mode we want.
0183  *      @info: frame buffer structure that represents a single frame buffer
0184  */
0185 static int cg3_blank(int blank, struct fb_info *info)
0186 {
0187     struct cg3_par *par = (struct cg3_par *) info->par;
0188     struct cg3_regs __iomem *regs = par->regs;
0189     unsigned long flags;
0190     u8 val;
0191
0192     spin_lock_irqsave(&par->lock, flags);
0193
0194     switch (blank) {
0195     case FB_BLANK_UNBLANK: /* Unblanking */
0196         val = sbus_readb(&regs->control);
0197         val |= CG3_CR_ENABLE_VIDEO;
0198         sbus_writeb(val, &regs->control);
0199         par->flags &= ~CG3_FLAG_BLANKED;
0200         break;
0201
0202     case FB_BLANK_NORMAL: /* Normal blanking */
0203     case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
0204     case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
0205     case FB_BLANK_POWERDOWN: /* Poweroff */
0206         val = sbus_readb(&regs->control);
0207         val &= ~CG3_CR_ENABLE_VIDEO;
0208         sbus_writeb(val, &regs->control);
0209         par->flags |= CG3_FLAG_BLANKED;
0210         break;
0211     }
0212
0213     spin_unlock_irqrestore(&par->lock, flags);
0214
0215     return 0;
0216 }
0217
0218 static struct sbus_mmap_map cg3_mmap_map[] = {
0219     {
0220         .voff   = CG3_MMAP_OFFSET,
0221         .poff   = CG3_RAM_OFFSET,
0222         .size   = SBUS_MMAP_FBSIZE(1)
0223     },
0224     { .size = 0 }
0225 };
0226
0227 static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
0228 {
0229     struct cg3_par *par = (struct cg3_par *)info->par;
0230
0231     return sbusfb_mmap_helper(cg3_mmap_map,
0232                   info->fix.smem_start, info->fix.smem_len,
0233                   par->which_io,
0234                   vma);
0235 }
0236
0237 static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
0238 {
0239     return sbusfb_ioctl_helper(cmd, arg, info,
0240                    FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
0241 }
0242
0243 /*
0244  *  Initialisation
0245  */
0246
0247 static void cg3_init_fix(struct fb_info *info, int linebytes,
0248              struct device_node *dp)
0249 {
0250     snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
0251
0252     info->fix.type = FB_TYPE_PACKED_PIXELS;
0253     info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
0254
0255     info->fix.line_length = linebytes;
0256
0257     info->fix.accel = FB_ACCEL_SUN_CGTHREE;
0258 }
0259
0260 static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
0261                     struct device_node *dp)
0262 {
0263     const char *params;
0264     char *p;
0265     int ww, hh;
0266
0267     params = of_get_property(dp, "params", NULL);
0268     if (params) {
0269         ww = simple_strtoul(params, &p, 10);
0270         if (ww && *p == 'x') {
0271             hh = simple_strtoul(p + 1, &p, 10);
0272             if (hh && *p == '-') {
0273                 if (var->xres != ww ||
0274                     var->yres != hh) {
0275                     var->xres = var->xres_virtual = ww;
0276                     var->yres = var->yres_virtual = hh;
0277                 }
0278             }
0279         }
0280     }
0281 }
0282
0283 static u8 cg3regvals_66hz[] = { /* 1152 x 900, 66 Hz */
0284     0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
0285     0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
0286     0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
0287     0x10, 0x20, 0
0288 };
0289
0290 static u8 cg3regvals_76hz[] = { /* 1152 x 900, 76 Hz */
0291     0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
0292     0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
0293     0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
0294     0x10, 0x24, 0
0295 };
0296
0297 static u8 cg3regvals_rdi[] = {  /* 640 x 480, cgRDI */
0298     0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
0299     0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
0300     0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
0301     0x10, 0x22, 0
0302 };
0303
0304 static u8 *cg3_regvals[] = {
0305     cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
0306 };
0307
0308 static u_char cg3_dacvals[] = {
0309     4, 0xff,    5, 0x00,    6, 0x70,    7, 0x00,    0
0310 };
0311
0312 static int cg3_do_default_mode(struct cg3_par *par)
0313 {
0314     enum cg3_type type;
0315     u8 *p;
0316
0317     if (par->flags & CG3_FLAG_RDI)
0318         type = CG3_RDI;
0319     else {
0320         u8 status = sbus_readb(&par->regs->status), mon;
0321         if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
0322             mon = status & CG3_SR_RES_MASK;
0323             if (mon == CG3_SR_1152_900_76_A ||
0324                 mon == CG3_SR_1152_900_76_B)
0325                 type = CG3_AT_76HZ;
0326             else
0327                 type = CG3_AT_66HZ;
0328         } else {
0329             printk(KERN_ERR "cgthree: can't handle SR %02x\n",
0330                    status);
0331             return -EINVAL;
0332         }
0333     }
0334
0335     for (p = cg3_regvals[type]; *p; p += 2) {
0336         u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
0337         sbus_writeb(p[1], regp);
0338     }
0339     for (p = cg3_dacvals; *p; p += 2) {
0340         u8 __iomem *regp;
0341
0342         regp = (u8 __iomem *)&par->regs->cmap.addr;
0343         sbus_writeb(p[0], regp);
0344         regp = (u8 __iomem *)&par->regs->cmap.control;
0345         sbus_writeb(p[1], regp);
0346     }
0347     return 0;
0348 }
0349
0350 static int cg3_probe(struct platform_device *op)
0351 {
0352     struct device_node *dp = op->dev.of_node;
0353     struct fb_info *info;
0354     struct cg3_par *par;
0355     int linebytes, err;
0356
0357     info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);
0358
0359     err = -ENOMEM;
0360     if (!info)
0361         goto out_err;
0362     par = info->par;
0363
0364     spin_lock_init(&par->lock);
0365
0366     info->fix.smem_start = op->resource[0].start;
0367     par->which_io = op->resource[0].flags & IORESOURCE_BITS;
0368
0369     sbusfb_fill_var(&info->var, dp, 8);
0370     info->var.red.length = 8;
0371     info->var.green.length = 8;
0372     info->var.blue.length = 8;
0373     if (of_node_name_eq(dp, "cgRDI"))
0374         par->flags |= CG3_FLAG_RDI;
0375     if (par->flags & CG3_FLAG_RDI)
0376         cg3_rdi_maybe_fixup_var(&info->var, dp);
0377
0378     linebytes = of_getintprop_default(dp, "linebytes",
0379                       info->var.xres);
0380     info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
0381
0382     par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
0383                    sizeof(struct cg3_regs), "cg3 regs");
0384     if (!par->regs)
0385         goto out_release_fb;
0386
0387     info->flags = FBINFO_DEFAULT;
0388     info->fbops = &cg3_ops;
0389     info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
0390                        info->fix.smem_len, "cg3 ram");
0391     if (!info->screen_base)
0392         goto out_unmap_regs;
0393
0394     cg3_blank(FB_BLANK_UNBLANK, info);
0395
0396     if (!of_find_property(dp, "width", NULL)) {
0397         err = cg3_do_default_mode(par);
0398         if (err)
0399             goto out_unmap_screen;
0400     }
0401
0402     err = fb_alloc_cmap(&info->cmap, 256, 0);
0403     if (err)
0404         goto out_unmap_screen;
0405
0406     fb_set_cmap(&info->cmap, info);
0407
0408     cg3_init_fix(info, linebytes, dp);
0409
0410     err = register_framebuffer(info);
0411     if (err < 0)
0412         goto out_dealloc_cmap;
0413
0414     dev_set_drvdata(&op->dev, info);
0415
0416     printk(KERN_INFO "%pOF: cg3 at %lx:%lx\n",
0417            dp, par->which_io, info->fix.smem_start);
0418
0419     return 0;
0420
0421 out_dealloc_cmap:
0422     fb_dealloc_cmap(&info->cmap);
0423
0424 out_unmap_screen:
0425     of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
0426
0427 out_unmap_regs:
0428     of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
0429
0430 out_release_fb:
0431     framebuffer_release(info);
0432
0433 out_err:
0434     return err;
0435 }
0436
0437 static int cg3_remove(struct platform_device *op)
0438 {
0439     struct fb_info *info = dev_get_drvdata(&op->dev);
0440     struct cg3_par *par = info->par;
0441
0442     unregister_framebuffer(info);
0443     fb_dealloc_cmap(&info->cmap);
0444
0445     of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
0446     of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
0447
0448     framebuffer_release(info);
0449
0450     return 0;
0451 }
0452
0453 static const struct of_device_id cg3_match[] = {
0454     {
0455         .name = "cgthree",
0456     },
0457     {
0458         .name = "cgRDI",
0459     },
0460     {},
0461 };
0462 MODULE_DEVICE_TABLE(of, cg3_match);
0463
0464 static struct platform_driver cg3_driver = {
0465     .driver = {
0466         .name = "cg3",
0467         .of_match_table = cg3_match,
0468     },
0469     .probe      = cg3_probe,
0470     .remove     = cg3_remove,
0471 };
0472
0473 static int __init cg3_init(void)
0474 {
0475     if (fb_get_options("cg3fb", NULL))
0476         return -ENODEV;
0477
0478     return platform_driver_register(&cg3_driver);
0479 }
0480
0481 static void __exit cg3_exit(void)
0482 {
0483     platform_driver_unregister(&cg3_driver);
0484 }
0485
0486 module_init(cg3_init);
0487 module_exit(cg3_exit);
0488
0489 MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
0490 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
0491 MODULE_VERSION("2.0");
0492 MODULE_LICENSE("GPL");