video/fbdev/carminefb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef CARMINE_CARMINE_H
0003 #define CARMINE_CARMINE_H
0004
0005 #define CARMINE_MEMORY_BAR  2
0006 #define CARMINE_CONFIG_BAR  3
0007
0008 #define MAX_DISPLAY 2
0009 #define CARMINE_DISPLAY_MEM (800 * 600 * 4)
0010 #define CARMINE_TOTAL_DIPLAY_MEM    (CARMINE_DISPLAY_MEM * MAX_DISPLAY)
0011
0012 #define CARMINE_USE_DISPLAY0    (1 << 0)
0013 #define CARMINE_USE_DISPLAY1    (1 << 1)
0014
0015 /*
0016  * This values work on the eval card. Custom boards may use different timings,
0017  * here an example :)
0018  */
0019
0020 /* DRAM initialization values */
0021 #ifdef CONFIG_FB_CARMINE_DRAM_EVAL
0022
0023 #define CARMINE_DFLT_IP_CLOCK_ENABLE        (0x03ff)
0024 #define CARMINE_DFLT_IP_DCTL_ADD        (0x05c3)
0025 #define CARMINE_DFLT_IP_DCTL_MODE       (0x0121)
0026 #define CARMINE_DFLT_IP_DCTL_EMODE      (0x8000)
0027 #define CARMINE_DFLT_IP_DCTL_SET_TIME1      (0x4749)
0028 #define CARMINE_DFLT_IP_DCTL_SET_TIME2      (0x2a22)
0029 #define CARMINE_DFLT_IP_DCTL_REFRESH        (0x0042)
0030 #define CARMINE_DFLT_IP_DCTL_STATES     (0x0003)
0031 #define CARMINE_DFLT_IP_DCTL_RESERVE0       (0x0020)
0032 #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH     (0x000f)
0033 #define CARMINE_DFLT_IP_DCTL_RESERVE2       (0x0000)
0034 #define CARMINE_DFLT_IP_DCTL_DDRIF1     (0x6646)
0035 #define CARMINE_DFLT_IP_DCTL_DDRIF2     (0x0055)
0036 #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST   (0x0021)
0037 #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002)
0038 #define CARMINE_DFLT_IP_DCTL_IO_CONT0       (0x0555)
0039 #define CARMINE_DFLT_IP_DCTL_IO_CONT1       (0x0555)
0040 #define CARMINE_DCTL_DLL_RESET          (1)
0041 #endif
0042
0043 #ifdef CONFIG_CARMINE_DRAM_CUSTOM
0044
0045 #define CARMINE_DFLT_IP_CLOCK_ENABLE        (0x03ff)
0046 #define CARMINE_DFLT_IP_DCTL_ADD        (0x03b2)
0047 #define CARMINE_DFLT_IP_DCTL_MODE       (0x0161)
0048 #define CARMINE_DFLT_IP_DCTL_EMODE      (0x8000)
0049 #define CARMINE_DFLT_IP_DCTL_SET_TIME1      (0x2628)
0050 #define CARMINE_DFLT_IP_DCTL_SET_TIME2      (0x1a09)
0051 #define CARMINE_DFLT_IP_DCTL_REFRESH        (0x00fe)
0052 #define CARMINE_DFLT_IP_DCTL_STATES     (0x0003)
0053 #define CARMINE_DFLT_IP_DCTL_RESERVE0       (0x0020)
0054 #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH     (0x000f)
0055 #define CARMINE_DFLT_IP_DCTL_RESERVE2       (0x0000)
0056 #define CARMINE_DFLT_IP_DCTL_DDRIF1     (0x0646)
0057 #define CARMINE_DFLT_IP_DCTL_DDRIF2     (0x55aa)
0058 #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST   (0x0061)
0059 #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002)
0060 #define CARMINE_DFLT_IP_DCTL_IO_CONT0       (0x0555)
0061 #define CARMINE_DFLT_IP_DCTL_IO_CONT1       (0x0555)
0062 #define CARMINE_DCTL_DLL_RESET          (1)
0063 #endif
0064
0065 #endif