video/fbdev/au1100fb.h

0001 /*
0002  * BRIEF MODULE DESCRIPTION
0003  *  Hardware definitions for the Au1100 LCD controller
0004  *
0005  * Copyright 2002 MontaVista Software
0006  * Copyright 2002 Alchemy Semiconductor
0007  * Author:  Alchemy Semiconductor, MontaVista Software
0008  *
0009  *  This program is free software; you can redistribute  it and/or modify it
0010  *  under  the terms of  the GNU General  Public License as published by the
0011  *  Free Software Foundation;  either version 2 of the  License, or (at your
0012  *  option) any later version.
0013  *
0014  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0015  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0016  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0017  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0018  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0019  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0020  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0021  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0022  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0023  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0024  *
0025  *  You should have received a copy of the  GNU General Public License along
0026  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0027  *  675 Mass Ave, Cambridge, MA 02139, USA.
0028  */
0029
0030 #ifndef _AU1100LCD_H
0031 #define _AU1100LCD_H
0032
0033 #include <asm/mach-au1x00/au1000.h>
0034
0035 #define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
0036 #define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
0037 #define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
0038
0039 #if DEBUG
0040 #define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
0041 #else
0042 #define print_dbg(f, arg...) do {} while (0)
0043 #endif
0044
0045 #if defined(__BIG_ENDIAN)
0046 #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
0047 #else
0048 #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
0049 #endif
0050 #define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
0051
0052 /********************************************************************/
0053
0054 /* LCD controller restrictions */
0055 #define AU1100_LCD_MAX_XRES 800
0056 #define AU1100_LCD_MAX_YRES 600
0057 #define AU1100_LCD_MAX_BPP  16
0058 #define AU1100_LCD_MAX_CLK  48000000
0059 #define AU1100_LCD_NBR_PALETTE_ENTRIES 256
0060
0061 /* Default number of visible screen buffer to allocate */
0062 #define AU1100FB_NBR_VIDEO_BUFFERS 4
0063
0064 /********************************************************************/
0065
0066 struct au1100fb_panel
0067 {
0068     const char name[25];        /* Full name <vendor>_<model> */
0069
0070     u32     control_base;       /* Mode-independent control values */
0071     u32 clkcontrol_base;    /* Panel pixclock preferences */
0072
0073     u32 horztiming;
0074     u32 verttiming;
0075
0076     u32 xres;       /* Maximum horizontal resolution */
0077     u32     yres;       /* Maximum vertical resolution */
0078     u32     bpp;        /* Maximum depth supported */
0079 };
0080
0081 struct au1100fb_regs
0082 {
0083     u32  lcd_control;
0084     u32  lcd_intstatus;
0085     u32  lcd_intenable;
0086     u32  lcd_horztiming;
0087     u32  lcd_verttiming;
0088     u32  lcd_clkcontrol;
0089     u32  lcd_dmaaddr0;
0090     u32  lcd_dmaaddr1;
0091     u32  lcd_words;
0092     u32  lcd_pwmdiv;
0093     u32  lcd_pwmhi;
0094     u32  reserved[(0x0400-0x002C)/4];
0095     u32  lcd_palettebase[256];
0096 };
0097
0098 struct au1100fb_device {
0099
0100     struct fb_info info;            /* FB driver info record */
0101
0102     struct au1100fb_panel   *panel;     /* Panel connected to this device */
0103
0104     struct au1100fb_regs*   regs;       /* Registers memory map */
0105     size_t              regs_len;
0106     unsigned int        regs_phys;
0107
0108     unsigned char*      fb_mem;     /* FrameBuffer memory map */
0109     size_t              fb_len;
0110     dma_addr_t          fb_phys;
0111     int         panel_idx;
0112     struct clk      *lcdclk;
0113     struct device       *dev;
0114 };
0115
0116 /********************************************************************/
0117
0118 #define LCD_CONTROL                (AU1100_LCD_BASE + 0x0)
0119   #define LCD_CONTROL_SBB_BIT      21
0120   #define LCD_CONTROL_SBB_MASK     (0x3 << LCD_CONTROL_SBB_BIT)
0121     #define LCD_CONTROL_SBB_1        (0 << LCD_CONTROL_SBB_BIT)
0122     #define LCD_CONTROL_SBB_2        (1 << LCD_CONTROL_SBB_BIT)
0123     #define LCD_CONTROL_SBB_3        (2 << LCD_CONTROL_SBB_BIT)
0124     #define LCD_CONTROL_SBB_4        (3 << LCD_CONTROL_SBB_BIT)
0125   #define LCD_CONTROL_SBPPF_BIT    18
0126   #define LCD_CONTROL_SBPPF_MASK   (0x7 << LCD_CONTROL_SBPPF_BIT)
0127     #define LCD_CONTROL_SBPPF_655    (0 << LCD_CONTROL_SBPPF_BIT)
0128     #define LCD_CONTROL_SBPPF_565    (1 << LCD_CONTROL_SBPPF_BIT)
0129     #define LCD_CONTROL_SBPPF_556    (2 << LCD_CONTROL_SBPPF_BIT)
0130     #define LCD_CONTROL_SBPPF_1555   (3 << LCD_CONTROL_SBPPF_BIT)
0131     #define LCD_CONTROL_SBPPF_5551   (4 << LCD_CONTROL_SBPPF_BIT)
0132   #define LCD_CONTROL_WP           (1<<17)
0133   #define LCD_CONTROL_WD           (1<<16)
0134   #define LCD_CONTROL_C            (1<<15)
0135   #define LCD_CONTROL_SM_BIT       13
0136   #define LCD_CONTROL_SM_MASK      (0x3 << LCD_CONTROL_SM_BIT)
0137     #define LCD_CONTROL_SM_0         (0 << LCD_CONTROL_SM_BIT)
0138     #define LCD_CONTROL_SM_90        (1 << LCD_CONTROL_SM_BIT)
0139     #define LCD_CONTROL_SM_180       (2 << LCD_CONTROL_SM_BIT)
0140     #define LCD_CONTROL_SM_270       (3 << LCD_CONTROL_SM_BIT)
0141   #define LCD_CONTROL_DB           (1<<12)
0142   #define LCD_CONTROL_CCO          (1<<11)
0143   #define LCD_CONTROL_DP           (1<<10)
0144   #define LCD_CONTROL_PO_BIT       8
0145   #define LCD_CONTROL_PO_MASK      (0x3 << LCD_CONTROL_PO_BIT)
0146     #define LCD_CONTROL_PO_00        (0 << LCD_CONTROL_PO_BIT)
0147     #define LCD_CONTROL_PO_01        (1 << LCD_CONTROL_PO_BIT)
0148     #define LCD_CONTROL_PO_10        (2 << LCD_CONTROL_PO_BIT)
0149     #define LCD_CONTROL_PO_11        (3 << LCD_CONTROL_PO_BIT)
0150   #define LCD_CONTROL_MPI          (1<<7)
0151   #define LCD_CONTROL_PT           (1<<6)
0152   #define LCD_CONTROL_PC           (1<<5)
0153   #define LCD_CONTROL_BPP_BIT      1
0154   #define LCD_CONTROL_BPP_MASK     (0x7 << LCD_CONTROL_BPP_BIT)
0155     #define LCD_CONTROL_BPP_1        (0 << LCD_CONTROL_BPP_BIT)
0156     #define LCD_CONTROL_BPP_2        (1 << LCD_CONTROL_BPP_BIT)
0157     #define LCD_CONTROL_BPP_4        (2 << LCD_CONTROL_BPP_BIT)
0158     #define LCD_CONTROL_BPP_8        (3 << LCD_CONTROL_BPP_BIT)
0159     #define LCD_CONTROL_BPP_12       (4 << LCD_CONTROL_BPP_BIT)
0160     #define LCD_CONTROL_BPP_16       (5 << LCD_CONTROL_BPP_BIT)
0161   #define LCD_CONTROL_GO           (1<<0)
0162
0163 #define LCD_INTSTATUS              (AU1100_LCD_BASE + 0x4)
0164 #define LCD_INTENABLE              (AU1100_LCD_BASE + 0x8)
0165   #define LCD_INT_SD               (1<<7)
0166   #define LCD_INT_OF               (1<<6)
0167   #define LCD_INT_UF               (1<<5)
0168   #define LCD_INT_SA               (1<<3)
0169   #define LCD_INT_SS               (1<<2)
0170   #define LCD_INT_S1               (1<<1)
0171   #define LCD_INT_S0               (1<<0)
0172
0173 #define LCD_HORZTIMING             (AU1100_LCD_BASE + 0xC)
0174   #define LCD_HORZTIMING_HN2_BIT   24
0175   #define LCD_HORZTIMING_HN2_MASK  (0xFF << LCD_HORZTIMING_HN2_BIT)
0176   #define LCD_HORZTIMING_HN2_N(N)  ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
0177   #define LCD_HORZTIMING_HN1_BIT   16
0178   #define LCD_HORZTIMING_HN1_MASK  (0xFF << LCD_HORZTIMING_HN1_BIT)
0179   #define LCD_HORZTIMING_HN1_N(N)  ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
0180   #define LCD_HORZTIMING_HPW_BIT   10
0181   #define LCD_HORZTIMING_HPW_MASK  (0x3F << LCD_HORZTIMING_HPW_BIT)
0182   #define LCD_HORZTIMING_HPW_N(N)  ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
0183   #define LCD_HORZTIMING_PPL_BIT   0
0184   #define LCD_HORZTIMING_PPL_MASK  (0x3FF << LCD_HORZTIMING_PPL_BIT)
0185   #define LCD_HORZTIMING_PPL_N(N)  ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
0186
0187 #define LCD_VERTTIMING             (AU1100_LCD_BASE + 0x10)
0188   #define LCD_VERTTIMING_VN2_BIT   24
0189   #define LCD_VERTTIMING_VN2_MASK  (0xFF << LCD_VERTTIMING_VN2_BIT)
0190   #define LCD_VERTTIMING_VN2_N(N)  ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
0191   #define LCD_VERTTIMING_VN1_BIT   16
0192   #define LCD_VERTTIMING_VN1_MASK  (0xFF << LCD_VERTTIMING_VN1_BIT)
0193   #define LCD_VERTTIMING_VN1_N(N)  ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
0194   #define LCD_VERTTIMING_VPW_BIT   10
0195   #define LCD_VERTTIMING_VPW_MASK  (0x3F << LCD_VERTTIMING_VPW_BIT)
0196   #define LCD_VERTTIMING_VPW_N(N)  ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
0197   #define LCD_VERTTIMING_LPP_BIT   0
0198   #define LCD_VERTTIMING_LPP_MASK  (0x3FF << LCD_VERTTIMING_LPP_BIT)
0199   #define LCD_VERTTIMING_LPP_N(N)  ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
0200
0201 #define LCD_CLKCONTROL             (AU1100_LCD_BASE + 0x14)
0202   #define LCD_CLKCONTROL_IB        (1<<18)
0203   #define LCD_CLKCONTROL_IC        (1<<17)
0204   #define LCD_CLKCONTROL_IH        (1<<16)
0205   #define LCD_CLKCONTROL_IV        (1<<15)
0206   #define LCD_CLKCONTROL_BF_BIT    10
0207   #define LCD_CLKCONTROL_BF_MASK   (0x1F << LCD_CLKCONTROL_BF_BIT)
0208   #define LCD_CLKCONTROL_BF_N(N)   ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
0209   #define LCD_CLKCONTROL_PCD_BIT   0
0210   #define LCD_CLKCONTROL_PCD_MASK  (0x3FF << LCD_CLKCONTROL_PCD_BIT)
0211   #define LCD_CLKCONTROL_PCD_N(N)  (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
0212
0213 #define LCD_DMAADDR0               (AU1100_LCD_BASE + 0x18)
0214 #define LCD_DMAADDR1               (AU1100_LCD_BASE + 0x1C)
0215   #define LCD_DMA_SA_BIT           5
0216   #define LCD_DMA_SA_MASK          (0x7FFFFFF << LCD_DMA_SA_BIT)
0217   #define LCD_DMA_SA_N(N)          ((N) & LCD_DMA_SA_MASK)
0218
0219 #define LCD_WORDS                  (AU1100_LCD_BASE + 0x20)
0220   #define LCD_WRD_WRDS_BIT         0
0221   #define LCD_WRD_WRDS_MASK        (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
0222   #define LCD_WRD_WRDS_N(N)        ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
0223
0224 #define LCD_PWMDIV                 (AU1100_LCD_BASE + 0x24)
0225   #define LCD_PWMDIV_EN            (1<<12)
0226   #define LCD_PWMDIV_PWMDIV_BIT    0
0227   #define LCD_PWMDIV_PWMDIV_MASK   (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
0228   #define LCD_PWMDIV_PWMDIV_N(N)   ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
0229
0230 #define LCD_PWMHI                  (AU1100_LCD_BASE + 0x28)
0231   #define LCD_PWMHI_PWMHI1_BIT     12
0232   #define LCD_PWMHI_PWMHI1_MASK    (0xFFF << LCD_PWMHI_PWMHI1_BIT)
0233   #define LCD_PWMHI_PWMHI1_N(N)    (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
0234   #define LCD_PWMHI_PWMHI0_BIT     0
0235   #define LCD_PWMHI_PWMHI0_MASK    (0xFFF << LCD_PWMHI_PWMHI0_BIT)
0236   #define LCD_PWMHI_PWMHI0_N(N)    (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
0237
0238 #define LCD_PALLETTEBASE                (AU1100_LCD_BASE + 0x400)
0239   #define LCD_PALLETTE_MONO_MI_BIT      0
0240   #define LCD_PALLETTE_MONO_MI_MASK     (0xF << LCD_PALLETTE_MONO_MI_BIT)
0241   #define LCD_PALLETTE_MONO_MI_N(N)     (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
0242
0243   #define LCD_PALLETTE_COLOR_RI_BIT     8
0244   #define LCD_PALLETTE_COLOR_RI_MASK    (0xF << LCD_PALLETTE_COLOR_RI_BIT)
0245   #define LCD_PALLETTE_COLOR_RI_N(N)    (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
0246   #define LCD_PALLETTE_COLOR_GI_BIT     4
0247   #define LCD_PALLETTE_COLOR_GI_MASK    (0xF << LCD_PALLETTE_COLOR_GI_BIT)
0248   #define LCD_PALLETTE_COLOR_GI_N(N)    (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
0249   #define LCD_PALLETTE_COLOR_BI_BIT     0
0250   #define LCD_PALLETTE_COLOR_BI_MASK    (0xF << LCD_PALLETTE_COLOR_BI_BIT)
0251   #define LCD_PALLETTE_COLOR_BI_N(N)    (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
0252
0253   #define LCD_PALLETTE_TFT_DC_BIT       0
0254   #define LCD_PALLETTE_TFT_DC_MASK      (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
0255   #define LCD_PALLETTE_TFT_DC_N(N)      (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
0256
0257 /********************************************************************/
0258
0259 /* List of panels known to work with the AU1100 LCD controller.
0260  * To add a new panel, enter the same specifications as the
0261  * Generic_TFT one, and MAKE SURE that it doesn't conflicts
0262  * with the controller restrictions. Restrictions are:
0263  *
0264  * STN color panels: max_bpp <= 12
0265  * STN mono panels: max_bpp <= 4
0266  * TFT panels: max_bpp <= 16
0267  * max_xres <= 800
0268  * max_yres <= 600
0269  */
0270 static struct au1100fb_panel known_lcd_panels[] =
0271 {
0272     /* 800x600x16bpp CRT */
0273     [0] = {
0274         .name = "CRT_800x600_16",
0275         .xres = 800,
0276         .yres = 600,
0277         .bpp = 16,
0278         .control_base = 0x0004886A |
0279             LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
0280             LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
0281         .clkcontrol_base = 0x00020000,
0282         .horztiming = 0x005aff1f,
0283         .verttiming = 0x16000e57,
0284     },
0285     /* just the standard LCD */
0286     [1] = {
0287         .name = "WWPC LCD",
0288         .xres = 240,
0289         .yres = 320,
0290         .bpp = 16,
0291         .control_base = 0x0006806A,
0292         .horztiming = 0x0A1010EF,
0293         .verttiming = 0x0301013F,
0294         .clkcontrol_base = 0x00018001,
0295     },
0296     /* Sharp 320x240 TFT panel */
0297     [2] = {
0298         .name = "Sharp_LQ038Q5DR01",
0299         .xres = 320,
0300         .yres = 240,
0301         .bpp = 16,
0302         .control_base =
0303         ( LCD_CONTROL_SBPPF_565
0304         | LCD_CONTROL_C
0305         | LCD_CONTROL_SM_0
0306             | LCD_CONTROL_DEFAULT_PO
0307         | LCD_CONTROL_PT
0308         | LCD_CONTROL_PC
0309         | LCD_CONTROL_BPP_16 ),
0310         .horztiming =
0311         ( LCD_HORZTIMING_HN2_N(8)
0312         | LCD_HORZTIMING_HN1_N(60)
0313         | LCD_HORZTIMING_HPW_N(12)
0314         | LCD_HORZTIMING_PPL_N(320) ),
0315         .verttiming =
0316         ( LCD_VERTTIMING_VN2_N(5)
0317         | LCD_VERTTIMING_VN1_N(17)
0318         | LCD_VERTTIMING_VPW_N(1)
0319         | LCD_VERTTIMING_LPP_N(240) ),
0320         .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
0321     },
0322
0323     /* Hitachi SP14Q005 and possibly others */
0324     [3] = {
0325         .name = "Hitachi_SP14Qxxx",
0326         .xres = 320,
0327         .yres = 240,
0328         .bpp = 4,
0329         .control_base =
0330             ( LCD_CONTROL_C
0331             | LCD_CONTROL_BPP_4 ),
0332         .horztiming =
0333             ( LCD_HORZTIMING_HN2_N(1)
0334             | LCD_HORZTIMING_HN1_N(1)
0335             | LCD_HORZTIMING_HPW_N(1)
0336             | LCD_HORZTIMING_PPL_N(320) ),
0337         .verttiming =
0338             ( LCD_VERTTIMING_VN2_N(1)
0339             | LCD_VERTTIMING_VN1_N(1)
0340             | LCD_VERTTIMING_VPW_N(1)
0341             | LCD_VERTTIMING_LPP_N(240) ),
0342         .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
0343     },
0344
0345     /* Generic 640x480 TFT panel */
0346     [4] = {
0347         .name = "TFT_640x480_16",
0348         .xres = 640,
0349         .yres = 480,
0350         .bpp = 16,
0351         .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
0352         .horztiming = 0x3434d67f,
0353         .verttiming = 0x0e0e39df,
0354         .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
0355     },
0356
0357      /* Pb1100 LCDB 640x480 PrimeView TFT panel */
0358     [5] = {
0359         .name = "PrimeView_640x480_16",
0360         .xres = 640,
0361         .yres = 480,
0362         .bpp = 16,
0363         .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
0364         .horztiming = 0x0e4bfe7f,
0365         .verttiming = 0x210805df,
0366         .clkcontrol_base = 0x00038001,
0367     },
0368 };
0369
0370 /********************************************************************/
0371
0372 /* Inline helpers */
0373
0374 #define panel_is_dual(panel)  (panel->control_base & LCD_CONTROL_DP)
0375 #define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
0376 #define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
0377 #define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
0378
0379 #endif /* _AU1100LCD_H */