fbdev/aty/radeonfb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __RADEONFB_H__
0003 #define __RADEONFB_H__
0004
0005 #ifdef CONFIG_FB_RADEON_DEBUG
0006 #define DEBUG       1
0007 #endif
0008
0009 #include <linux/module.h>
0010 #include <linux/kernel.h>
0011 #include <linux/sched.h>
0012 #include <linux/delay.h>
0013 #include <linux/pci.h>
0014 #include <linux/fb.h>
0015
0016
0017 #ifdef CONFIG_FB_RADEON_I2C
0018 #include <linux/i2c.h>
0019 #include <linux/i2c-algo-bit.h>
0020 #endif
0021
0022 #include <asm/io.h>
0023
0024 #ifdef CONFIG_SPARC
0025 #include <asm/prom.h>
0026 #endif
0027
0028 #include <video/radeon.h>
0029
0030 /***************************************************************
0031  * Most of the definitions here are adapted right from XFree86 *
0032  ***************************************************************/
0033
0034
0035 /*
0036  * Chip families. Must fit in the low 16 bits of a long word
0037  */
0038 enum radeon_family {
0039     CHIP_FAMILY_UNKNOW,
0040     CHIP_FAMILY_LEGACY,
0041     CHIP_FAMILY_RADEON,
0042     CHIP_FAMILY_RV100,
0043     CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
0044     CHIP_FAMILY_RV200,
0045     CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
0046                  RS250 (IGP 7000) */
0047     CHIP_FAMILY_R200,
0048     CHIP_FAMILY_RV250,
0049     CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
0050     CHIP_FAMILY_RV280,
0051     CHIP_FAMILY_R300,
0052     CHIP_FAMILY_R350,
0053     CHIP_FAMILY_RV350,
0054     CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
0055     CHIP_FAMILY_R420,     /* R420/R423/M18 */
0056     CHIP_FAMILY_RC410,
0057     CHIP_FAMILY_RS400,
0058     CHIP_FAMILY_RS480,
0059     CHIP_FAMILY_LAST,
0060 };
0061
0062 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
0063                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
0064                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
0065                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
0066                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
0067                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
0068                  ((rinfo)->family == CHIP_FAMILY_RS300))
0069
0070
0071 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
0072                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
0073                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
0074                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
0075                 ((rinfo)->family == CHIP_FAMILY_R420)  || \
0076                                ((rinfo)->family == CHIP_FAMILY_RC410) || \
0077                                ((rinfo)->family == CHIP_FAMILY_RS480))
0078
0079 /*
0080  * Chip flags
0081  */
0082 enum radeon_chip_flags {
0083     CHIP_FAMILY_MASK    = 0x0000ffffUL,
0084     CHIP_FLAGS_MASK     = 0xffff0000UL,
0085     CHIP_IS_MOBILITY    = 0x00010000UL,
0086     CHIP_IS_IGP     = 0x00020000UL,
0087     CHIP_HAS_CRTC2      = 0x00040000UL,
0088 };
0089
0090 /*
0091  * Errata workarounds
0092  */
0093 enum radeon_errata {
0094     CHIP_ERRATA_R300_CG     = 0x00000001,
0095     CHIP_ERRATA_PLL_DUMMYREADS  = 0x00000002,
0096     CHIP_ERRATA_PLL_DELAY       = 0x00000004,
0097 };
0098
0099
0100 /*
0101  * Monitor types
0102  */
0103 enum radeon_montype {
0104     MT_NONE = 0,
0105     MT_CRT,     /* CRT */
0106     MT_LCD,     /* LCD */
0107     MT_DFP,     /* DVI */
0108     MT_CTV,     /* composite TV */
0109     MT_STV      /* S-Video out */
0110 };
0111
0112 /*
0113  * DDC i2c ports
0114  */
0115 enum ddc_type {
0116     ddc_none,
0117     ddc_monid,
0118     ddc_dvi,
0119     ddc_vga,
0120     ddc_crt2,
0121 };
0122
0123 /*
0124  * Connector types
0125  */
0126 enum conn_type {
0127     conn_none,
0128     conn_proprietary,
0129     conn_crt,
0130     conn_DVI_I,
0131     conn_DVI_D,
0132 };
0133
0134
0135 /*
0136  * PLL infos
0137  */
0138 struct pll_info {
0139     int ppll_max;
0140     int ppll_min;
0141     int sclk, mclk;
0142     int ref_div;
0143     int ref_clk;
0144 };
0145
0146
0147 /*
0148  * This structure contains the various registers manipulated by this
0149  * driver for setting or restoring a mode. It's mostly copied from
0150  * XFree's RADEONSaveRec structure. A few chip settings might still be
0151  * tweaked without beeing reflected or saved in these registers though
0152  */
0153 struct radeon_regs {
0154     /* Common registers */
0155     u32     ovr_clr;
0156     u32     ovr_wid_left_right;
0157     u32     ovr_wid_top_bottom;
0158     u32     ov0_scale_cntl;
0159     u32     mpp_tb_config;
0160     u32     mpp_gp_config;
0161     u32     subpic_cntl;
0162     u32     viph_control;
0163     u32     i2c_cntl_1;
0164     u32     gen_int_cntl;
0165     u32     cap0_trig_cntl;
0166     u32     cap1_trig_cntl;
0167     u32     bus_cntl;
0168     u32     surface_cntl;
0169     u32     bios_5_scratch;
0170
0171     /* Other registers to save for VT switches or driver load/unload */
0172     u32     dp_datatype;
0173     u32     rbbm_soft_reset;
0174     u32     clock_cntl_index;
0175     u32     amcgpio_en_reg;
0176     u32     amcgpio_mask;
0177
0178     /* Surface/tiling registers */
0179     u32     surf_lower_bound[8];
0180     u32     surf_upper_bound[8];
0181     u32     surf_info[8];
0182
0183     /* CRTC registers */
0184     u32     crtc_gen_cntl;
0185     u32     crtc_ext_cntl;
0186     u32     dac_cntl;
0187     u32     crtc_h_total_disp;
0188     u32     crtc_h_sync_strt_wid;
0189     u32     crtc_v_total_disp;
0190     u32     crtc_v_sync_strt_wid;
0191     u32     crtc_offset;
0192     u32     crtc_offset_cntl;
0193     u32     crtc_pitch;
0194     u32     disp_merge_cntl;
0195     u32     grph_buffer_cntl;
0196     u32     crtc_more_cntl;
0197
0198     /* CRTC2 registers */
0199     u32     crtc2_gen_cntl;
0200     u32     dac2_cntl;
0201     u32     disp_output_cntl;
0202     u32     disp_hw_debug;
0203     u32     disp2_merge_cntl;
0204     u32     grph2_buffer_cntl;
0205     u32     crtc2_h_total_disp;
0206     u32     crtc2_h_sync_strt_wid;
0207     u32     crtc2_v_total_disp;
0208     u32     crtc2_v_sync_strt_wid;
0209     u32     crtc2_offset;
0210     u32     crtc2_offset_cntl;
0211     u32     crtc2_pitch;
0212
0213     /* Flat panel regs */
0214     u32         fp_crtc_h_total_disp;
0215     u32     fp_crtc_v_total_disp;
0216     u32     fp_gen_cntl;
0217     u32     fp2_gen_cntl;
0218     u32     fp_h_sync_strt_wid;
0219     u32     fp2_h_sync_strt_wid;
0220     u32     fp_horz_stretch;
0221     u32     fp_panel_cntl;
0222     u32     fp_v_sync_strt_wid;
0223     u32     fp2_v_sync_strt_wid;
0224     u32     fp_vert_stretch;
0225     u32     lvds_gen_cntl;
0226     u32     lvds_pll_cntl;
0227     u32     tmds_crc;
0228     u32     tmds_transmitter_cntl;
0229
0230     /* Computed values for PLL */
0231     u32     dot_clock_freq;
0232     int     feedback_div;
0233     int     post_div;
0234
0235     /* PLL registers */
0236     u32     ppll_div_3;
0237     u32     ppll_ref_div;
0238     u32     vclk_ecp_cntl;
0239     u32     clk_cntl_index;
0240
0241     /* Computed values for PLL2 */
0242     u32     dot_clock_freq_2;
0243     int     feedback_div_2;
0244     int     post_div_2;
0245
0246     /* PLL2 registers */
0247     u32     p2pll_ref_div;
0248     u32     p2pll_div_0;
0249     u32     htotal_cntl2;
0250
0251         /* Palette */
0252     int     palette_valid;
0253 };
0254
0255 struct panel_info {
0256     int xres, yres;
0257     int valid;
0258     int clock;
0259     int hOver_plus, hSync_width, hblank;
0260     int vOver_plus, vSync_width, vblank;
0261     int hAct_high, vAct_high, interlaced;
0262     int pwr_delay;
0263     int use_bios_dividers;
0264     int ref_divider;
0265     int post_divider;
0266     int fbk_divider;
0267 };
0268
0269 struct radeonfb_info;
0270
0271 #ifdef CONFIG_FB_RADEON_I2C
0272 struct radeon_i2c_chan {
0273     struct radeonfb_info        *rinfo;
0274     u32             ddc_reg;
0275     struct i2c_adapter      adapter;
0276     struct i2c_algo_bit_data    algo;
0277 };
0278 #endif
0279
0280 enum radeon_pm_mode {
0281     radeon_pm_none  = 0,        /* Nothing supported */
0282     radeon_pm_d2    = 0x00000001,   /* Can do D2 state */
0283     radeon_pm_off   = 0x00000002,   /* Can resume from D3 cold */
0284 };
0285
0286 typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
0287
0288 struct radeonfb_info {
0289     struct fb_info      *info;
0290
0291     struct radeon_regs  state;
0292     struct radeon_regs  init_state;
0293
0294     char            name[50];
0295
0296     unsigned long       mmio_base_phys;
0297     unsigned long       fb_base_phys;
0298
0299     void __iomem        *mmio_base;
0300     void __iomem        *fb_base;
0301
0302     unsigned long       fb_local_base;
0303
0304     struct pci_dev      *pdev;
0305 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
0306     struct device_node  *of_node;
0307 #endif
0308
0309     void __iomem        *bios_seg;
0310     int         fp_bios_start;
0311
0312     u32         pseudo_palette[16];
0313     struct { u8 red, green, blue, pad; }
0314                 palette[256];
0315
0316     int         chipset;
0317     u8          family;
0318     u8          rev;
0319     unsigned int        errata;
0320     unsigned long       video_ram;
0321     unsigned long       mapped_vram;
0322     int         vram_width;
0323     int         vram_ddr;
0324
0325     int         pitch, bpp, depth;
0326
0327     int         has_CRTC2;
0328     int         is_mobility;
0329     int         is_IGP;
0330     int         reversed_DAC;
0331     int         reversed_TMDS;
0332     struct panel_info   panel_info;
0333     int         mon1_type;
0334     u8          *mon1_EDID;
0335     struct fb_videomode *mon1_modedb;
0336     int         mon1_dbsize;
0337     int         mon2_type;
0338     u8              *mon2_EDID;
0339
0340     u32         dp_gui_master_cntl;
0341
0342     struct pll_info     pll;
0343
0344     int         wc_cookie;
0345
0346     u32         save_regs[100];
0347     int         asleep;
0348     int         lock_blank;
0349     int         dynclk;
0350     int         no_schedule;
0351     enum radeon_pm_mode pm_mode;
0352     reinit_function_ptr     reinit_func;
0353
0354     /* Lock on register access */
0355     spinlock_t      reg_lock;
0356
0357     /* Timer used for delayed LVDS operations */
0358     struct timer_list   lvds_timer;
0359     u32         pending_lvds_gen_cntl;
0360
0361 #ifdef CONFIG_FB_RADEON_I2C
0362     struct radeon_i2c_chan  i2c[4];
0363 #endif
0364 };
0365
0366
0367 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
0368
0369
0370 /*
0371  * IO macros
0372  */
0373
0374 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms);
0375
0376 #define INREG8(addr)        readb((rinfo->mmio_base)+addr)
0377 #define OUTREG8(addr,val)   writeb(val, (rinfo->mmio_base)+addr)
0378 #define INREG16(addr)       readw((rinfo->mmio_base)+addr)
0379 #define OUTREG16(addr,val)  writew(val, (rinfo->mmio_base)+addr)
0380 #define INREG(addr)     readl((rinfo->mmio_base)+addr)
0381 #define OUTREG(addr,val)    writel(val, (rinfo->mmio_base)+addr)
0382
0383 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask);
0384
0385 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
0386
0387 /*
0388  * Note about PLL register accesses:
0389  *
0390  * I have removed the spinlock on them on purpose. The driver now
0391  * expects that it will only manipulate the PLL registers in normal
0392  * task environment, where radeon_msleep() will be called, protected
0393  * by a semaphore (currently the console semaphore) so that no conflict
0394  * will happen on the PLL register index.
0395  *
0396  * With the latest changes to the VT layer, this is guaranteed for all
0397  * calls except the actual drawing/blits which aren't supposed to use
0398  * the PLL registers anyway
0399  *
0400  * This is very important for the workarounds to work properly. The only
0401  * possible exception to this rule is the call to unblank(), which may
0402  * be done at irq time if an oops is in progress.
0403  */
0404 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo);
0405 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
0406 {
0407     if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS)
0408         radeon_pll_errata_after_index_slow(rinfo);
0409 }
0410
0411 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo);
0412 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
0413 {
0414     if (rinfo->errata & (CHIP_ERRATA_PLL_DELAY|CHIP_ERRATA_R300_CG))
0415         radeon_pll_errata_after_data_slow(rinfo);
0416 }
0417
0418 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr);
0419 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val);
0420 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
0421                  u32 val, u32 mask);
0422
0423 #define INPLL(addr)         __INPLL(rinfo, addr)
0424 #define OUTPLL(index, val)      __OUTPLL(rinfo, index, val)
0425 #define OUTPLLP(index, val, mask)   __OUTPLLP(rinfo, index, val, mask)
0426
0427
0428 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
0429 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
0430               (readb(rinfo->bios_seg + (v) + 1) << 8))
0431 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
0432               (readb(rinfo->bios_seg + (v) + 1) << 8) | \
0433               (readb(rinfo->bios_seg + (v) + 2) << 16) | \
0434               (readb(rinfo->bios_seg + (v) + 3) << 24))
0435
0436 /*
0437  * Inline utilities
0438  */
0439 static inline int round_div(int num, int den)
0440 {
0441         return (num + (den / 2)) / den;
0442 }
0443
0444 static inline int var_to_depth(const struct fb_var_screeninfo *var)
0445 {
0446     if (var->bits_per_pixel != 16)
0447         return var->bits_per_pixel;
0448     return (var->green.length == 5) ? 15 : 16;
0449 }
0450
0451 static inline u32 radeon_get_dstbpp(u16 depth)
0452 {
0453     switch (depth) {
0454         case 8:
0455             return DST_8BPP;
0456         case 15:
0457             return DST_15BPP;
0458         case 16:
0459             return DST_16BPP;
0460         case 32:
0461             return DST_32BPP;
0462         default:
0463             return 0;
0464     }
0465 }
0466
0467 /*
0468  * 2D Engine helper routines
0469  */
0470
0471 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries);
0472 void radeon_engine_flush(struct radeonfb_info *rinfo);
0473 void _radeon_engine_idle(struct radeonfb_info *rinfo);
0474
0475 #define radeon_engine_idle()        _radeon_engine_idle(rinfo)
0476 #define radeon_fifo_wait(entries)   _radeon_fifo_wait(rinfo,entries)
0477 #define radeon_msleep(ms)       _radeon_msleep(rinfo,ms)
0478
0479
0480 /* I2C Functions */
0481 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
0482 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
0483 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
0484
0485 /* PM Functions */
0486 extern const struct dev_pm_ops radeonfb_pci_pm_ops;
0487 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
0488 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
0489
0490 /* Monitor probe functions */
0491 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
0492                  const char *monitor_layout, int ignore_edid);
0493 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
0494 extern int radeon_match_mode(struct radeonfb_info *rinfo,
0495                  struct fb_var_screeninfo *dest,
0496                  const struct fb_var_screeninfo *src);
0497
0498 /* Accel functions */
0499 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
0500 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
0501 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
0502 extern int radeonfb_sync(struct fb_info *info);
0503 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
0504 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
0505
0506 /* Other functions */
0507 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
0508 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
0509                    int reg_only);
0510
0511 /* Backlight functions */
0512 #ifdef CONFIG_FB_RADEON_BACKLIGHT
0513 extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
0514 extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
0515 #else
0516 static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
0517 static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
0518 #endif
0519
0520 #endif /* __RADEONFB_H__ */