fbdev/aty/radeon_base.c

0001 /*
0002  *  drivers/video/aty/radeon_base.c
0003  *
0004  *  framebuffer driver for ATI Radeon chipset video boards
0005  *
0006  *  Copyright 2003  Ben. Herrenschmidt <benh@kernel.crashing.org>
0007  *  Copyright 2000  Ani Joshi <ajoshi@kernel.crashing.org>
0008  *
0009  *  i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
0010  *
0011  *  Special thanks to ATI DevRel team for their hardware donations.
0012  *
0013  *  ...Insert GPL boilerplate here...
0014  *
0015  *  Significant portions of this driver apdated from XFree86 Radeon
0016  *  driver which has the following copyright notice:
0017  *
0018  *  Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
0019  *                     VA Linux Systems Inc., Fremont, California.
0020  *
0021  *  All Rights Reserved.
0022  *
0023  *  Permission is hereby granted, free of charge, to any person obtaining
0024  *  a copy of this software and associated documentation files (the
0025  *  "Software"), to deal in the Software without restriction, including
0026  *  without limitation on the rights to use, copy, modify, merge,
0027  *  publish, distribute, sublicense, and/or sell copies of the Software,
0028  *  and to permit persons to whom the Software is furnished to do so,
0029  *  subject to the following conditions:
0030  *
0031  *  The above copyright notice and this permission notice (including the
0032  *  next paragraph) shall be included in all copies or substantial
0033  *  portions of the Software.
0034  *
0035  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036  *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0037  *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038  *  NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
0039  *  THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040  *  WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0041  *  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0042  *  DEALINGS IN THE SOFTWARE.
0043  *
0044  *  XFree86 driver authors:
0045  *
0046  *     Kevin E. Martin <martin@xfree86.org>
0047  *     Rickard E. Faith <faith@valinux.com>
0048  *     Alan Hourihane <alanh@fairlite.demon.co.uk>
0049  *
0050  */
0051
0052
0053 #define RADEON_VERSION  "0.2.0"
0054
0055 #include "radeonfb.h"
0056
0057 #include <linux/module.h>
0058 #include <linux/moduleparam.h>
0059 #include <linux/kernel.h>
0060 #include <linux/errno.h>
0061 #include <linux/string.h>
0062 #include <linux/ctype.h>
0063 #include <linux/mm.h>
0064 #include <linux/slab.h>
0065 #include <linux/delay.h>
0066 #include <linux/time.h>
0067 #include <linux/fb.h>
0068 #include <linux/ioport.h>
0069 #include <linux/init.h>
0070 #include <linux/pci.h>
0071 #include <linux/vmalloc.h>
0072 #include <linux/device.h>
0073
0074 #include <asm/io.h>
0075 #include <linux/uaccess.h>
0076
0077 #ifdef CONFIG_PPC
0078
0079 #include "../macmodes.h"
0080
0081 #ifdef CONFIG_BOOTX_TEXT
0082 #include <asm/btext.h>
0083 #endif
0084
0085 #endif /* CONFIG_PPC */
0086
0087 #include <video/radeon.h>
0088 #include <linux/radeonfb.h>
0089
0090 #include "../edid.h" // MOVE THAT TO include/video
0091 #include "ati_ids.h"
0092
0093 #define MAX_MAPPED_VRAM (2048*2048*4)
0094 #define MIN_MAPPED_VRAM (1024*768*1)
0095
0096 #define CHIP_DEF(id, family, flags)                 \
0097     { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
0098
0099 static const struct pci_device_id radeonfb_pci_table[] = {
0100         /* Radeon Xpress 200m */
0101     CHIP_DEF(PCI_CHIP_RS480_5955,   RS480,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0102     CHIP_DEF(PCI_CHIP_RS482_5975,   RS480,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0103     /* Mobility M6 */
0104     CHIP_DEF(PCI_CHIP_RADEON_LY,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0105     CHIP_DEF(PCI_CHIP_RADEON_LZ,    RV100,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0106     /* Radeon VE/7000 */
0107     CHIP_DEF(PCI_CHIP_RV100_QY,     RV100,  CHIP_HAS_CRTC2),
0108     CHIP_DEF(PCI_CHIP_RV100_QZ,     RV100,  CHIP_HAS_CRTC2),
0109     CHIP_DEF(PCI_CHIP_RN50,     RV100,  CHIP_HAS_CRTC2),
0110     /* Radeon IGP320M (U1) */
0111     CHIP_DEF(PCI_CHIP_RS100_4336,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0112     /* Radeon IGP320 (A3) */
0113     CHIP_DEF(PCI_CHIP_RS100_4136,   RS100,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
0114     /* IGP330M/340M/350M (U2) */
0115     CHIP_DEF(PCI_CHIP_RS200_4337,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0116     /* IGP330/340/350 (A4) */
0117     CHIP_DEF(PCI_CHIP_RS200_4137,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
0118     /* Mobility 7000 IGP */
0119     CHIP_DEF(PCI_CHIP_RS250_4437,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0120     /* 7000 IGP (A4+) */
0121     CHIP_DEF(PCI_CHIP_RS250_4237,   RS200,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
0122     /* 8500 AIW */
0123     CHIP_DEF(PCI_CHIP_R200_BB,  R200,   CHIP_HAS_CRTC2),
0124     CHIP_DEF(PCI_CHIP_R200_BC,  R200,   CHIP_HAS_CRTC2),
0125     /* 8700/8800 */
0126     CHIP_DEF(PCI_CHIP_R200_QH,  R200,   CHIP_HAS_CRTC2),
0127     /* 8500 */
0128     CHIP_DEF(PCI_CHIP_R200_QL,  R200,   CHIP_HAS_CRTC2),
0129     /* 9100 */
0130     CHIP_DEF(PCI_CHIP_R200_QM,  R200,   CHIP_HAS_CRTC2),
0131     /* Mobility M7 */
0132     CHIP_DEF(PCI_CHIP_RADEON_LW,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0133     CHIP_DEF(PCI_CHIP_RADEON_LX,    RV200,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0134     /* 7500 */
0135     CHIP_DEF(PCI_CHIP_RV200_QW, RV200,  CHIP_HAS_CRTC2),
0136     CHIP_DEF(PCI_CHIP_RV200_QX, RV200,  CHIP_HAS_CRTC2),
0137     /* Mobility M9 */
0138     CHIP_DEF(PCI_CHIP_RV250_Ld, RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0139     CHIP_DEF(PCI_CHIP_RV250_Le, RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0140     CHIP_DEF(PCI_CHIP_RV250_Lf, RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0141     CHIP_DEF(PCI_CHIP_RV250_Lg, RV250,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0142     /* 9000/Pro */
0143     CHIP_DEF(PCI_CHIP_RV250_If, RV250,  CHIP_HAS_CRTC2),
0144     CHIP_DEF(PCI_CHIP_RV250_Ig, RV250,  CHIP_HAS_CRTC2),
0145
0146     CHIP_DEF(PCI_CHIP_RC410_5A62,   RC410,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0147     /* Mobility 9100 IGP (U3) */
0148     CHIP_DEF(PCI_CHIP_RS300_5835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0149     CHIP_DEF(PCI_CHIP_RS350_7835,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
0150     /* 9100 IGP (A5) */
0151     CHIP_DEF(PCI_CHIP_RS300_5834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
0152     CHIP_DEF(PCI_CHIP_RS350_7834,   RS300,  CHIP_HAS_CRTC2 | CHIP_IS_IGP),
0153     /* Mobility 9200 (M9+) */
0154     CHIP_DEF(PCI_CHIP_RV280_5C61,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0155     CHIP_DEF(PCI_CHIP_RV280_5C63,   RV280,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0156     /* 9200 */
0157     CHIP_DEF(PCI_CHIP_RV280_5960,   RV280,  CHIP_HAS_CRTC2),
0158     CHIP_DEF(PCI_CHIP_RV280_5961,   RV280,  CHIP_HAS_CRTC2),
0159     CHIP_DEF(PCI_CHIP_RV280_5962,   RV280,  CHIP_HAS_CRTC2),
0160     CHIP_DEF(PCI_CHIP_RV280_5964,   RV280,  CHIP_HAS_CRTC2),
0161     /* 9500 */
0162     CHIP_DEF(PCI_CHIP_R300_AD,  R300,   CHIP_HAS_CRTC2),
0163     CHIP_DEF(PCI_CHIP_R300_AE,  R300,   CHIP_HAS_CRTC2),
0164     /* 9600TX / FireGL Z1 */
0165     CHIP_DEF(PCI_CHIP_R300_AF,  R300,   CHIP_HAS_CRTC2),
0166     CHIP_DEF(PCI_CHIP_R300_AG,  R300,   CHIP_HAS_CRTC2),
0167     /* 9700/9500/Pro/FireGL X1 */
0168     CHIP_DEF(PCI_CHIP_R300_ND,  R300,   CHIP_HAS_CRTC2),
0169     CHIP_DEF(PCI_CHIP_R300_NE,  R300,   CHIP_HAS_CRTC2),
0170     CHIP_DEF(PCI_CHIP_R300_NF,  R300,   CHIP_HAS_CRTC2),
0171     CHIP_DEF(PCI_CHIP_R300_NG,  R300,   CHIP_HAS_CRTC2),
0172     /* Mobility M10/M11 */
0173     CHIP_DEF(PCI_CHIP_RV350_NP, RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0174     CHIP_DEF(PCI_CHIP_RV350_NQ, RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0175     CHIP_DEF(PCI_CHIP_RV350_NR, RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0176     CHIP_DEF(PCI_CHIP_RV350_NS, RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0177     CHIP_DEF(PCI_CHIP_RV350_NT, RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0178     CHIP_DEF(PCI_CHIP_RV350_NV, RV350,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0179     /* 9600/FireGL T2 */
0180     CHIP_DEF(PCI_CHIP_RV350_AP, RV350,  CHIP_HAS_CRTC2),
0181     CHIP_DEF(PCI_CHIP_RV350_AQ, RV350,  CHIP_HAS_CRTC2),
0182     CHIP_DEF(PCI_CHIP_RV360_AR, RV350,  CHIP_HAS_CRTC2),
0183     CHIP_DEF(PCI_CHIP_RV350_AS, RV350,  CHIP_HAS_CRTC2),
0184     CHIP_DEF(PCI_CHIP_RV350_AT, RV350,  CHIP_HAS_CRTC2),
0185     CHIP_DEF(PCI_CHIP_RV350_AV, RV350,  CHIP_HAS_CRTC2),
0186     /* 9800/Pro/FileGL X2 */
0187     CHIP_DEF(PCI_CHIP_R350_AH,  R350,   CHIP_HAS_CRTC2),
0188     CHIP_DEF(PCI_CHIP_R350_AI,  R350,   CHIP_HAS_CRTC2),
0189     CHIP_DEF(PCI_CHIP_R350_AJ,  R350,   CHIP_HAS_CRTC2),
0190     CHIP_DEF(PCI_CHIP_R350_AK,  R350,   CHIP_HAS_CRTC2),
0191     CHIP_DEF(PCI_CHIP_R350_NH,  R350,   CHIP_HAS_CRTC2),
0192     CHIP_DEF(PCI_CHIP_R350_NI,  R350,   CHIP_HAS_CRTC2),
0193     CHIP_DEF(PCI_CHIP_R360_NJ,  R350,   CHIP_HAS_CRTC2),
0194     CHIP_DEF(PCI_CHIP_R350_NK,  R350,   CHIP_HAS_CRTC2),
0195     /* Newer stuff */
0196     CHIP_DEF(PCI_CHIP_RV380_3E50,   RV380,  CHIP_HAS_CRTC2),
0197     CHIP_DEF(PCI_CHIP_RV380_3E54,   RV380,  CHIP_HAS_CRTC2),
0198     CHIP_DEF(PCI_CHIP_RV380_3150,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0199     CHIP_DEF(PCI_CHIP_RV380_3154,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0200     CHIP_DEF(PCI_CHIP_RV370_5B60,   RV380,  CHIP_HAS_CRTC2),
0201     CHIP_DEF(PCI_CHIP_RV370_5B62,   RV380,  CHIP_HAS_CRTC2),
0202     CHIP_DEF(PCI_CHIP_RV370_5B63,   RV380,  CHIP_HAS_CRTC2),
0203     CHIP_DEF(PCI_CHIP_RV370_5B64,   RV380,  CHIP_HAS_CRTC2),
0204     CHIP_DEF(PCI_CHIP_RV370_5B65,   RV380,  CHIP_HAS_CRTC2),
0205     CHIP_DEF(PCI_CHIP_RV370_5460,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0206     CHIP_DEF(PCI_CHIP_RV370_5464,   RV380,  CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0207     CHIP_DEF(PCI_CHIP_R420_JH,  R420,   CHIP_HAS_CRTC2),
0208     CHIP_DEF(PCI_CHIP_R420_JI,  R420,   CHIP_HAS_CRTC2),
0209     CHIP_DEF(PCI_CHIP_R420_JJ,  R420,   CHIP_HAS_CRTC2),
0210     CHIP_DEF(PCI_CHIP_R420_JK,  R420,   CHIP_HAS_CRTC2),
0211     CHIP_DEF(PCI_CHIP_R420_JL,  R420,   CHIP_HAS_CRTC2),
0212     CHIP_DEF(PCI_CHIP_R420_JM,  R420,   CHIP_HAS_CRTC2),
0213     CHIP_DEF(PCI_CHIP_R420_JN,  R420,   CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
0214     CHIP_DEF(PCI_CHIP_R420_JP,  R420,   CHIP_HAS_CRTC2),
0215     CHIP_DEF(PCI_CHIP_R423_UH,  R420,   CHIP_HAS_CRTC2),
0216     CHIP_DEF(PCI_CHIP_R423_UI,  R420,   CHIP_HAS_CRTC2),
0217     CHIP_DEF(PCI_CHIP_R423_UJ,  R420,   CHIP_HAS_CRTC2),
0218     CHIP_DEF(PCI_CHIP_R423_UK,  R420,   CHIP_HAS_CRTC2),
0219     CHIP_DEF(PCI_CHIP_R423_UQ,  R420,   CHIP_HAS_CRTC2),
0220     CHIP_DEF(PCI_CHIP_R423_UR,  R420,   CHIP_HAS_CRTC2),
0221     CHIP_DEF(PCI_CHIP_R423_UT,  R420,   CHIP_HAS_CRTC2),
0222     CHIP_DEF(PCI_CHIP_R423_5D57,    R420,   CHIP_HAS_CRTC2),
0223     /* Original Radeon/7200 */
0224     CHIP_DEF(PCI_CHIP_RADEON_QD,    RADEON, 0),
0225     CHIP_DEF(PCI_CHIP_RADEON_QE,    RADEON, 0),
0226     CHIP_DEF(PCI_CHIP_RADEON_QF,    RADEON, 0),
0227     CHIP_DEF(PCI_CHIP_RADEON_QG,    RADEON, 0),
0228     { 0, }
0229 };
0230 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
0231
0232
0233 typedef struct {
0234     u16 reg;
0235     u32 val;
0236 } reg_val;
0237
0238
0239 /* these common regs are cleared before mode setting so they do not
0240  * interfere with anything
0241  */
0242 static reg_val common_regs[] = {
0243     { OVR_CLR, 0 },
0244     { OVR_WID_LEFT_RIGHT, 0 },
0245     { OVR_WID_TOP_BOTTOM, 0 },
0246     { OV0_SCALE_CNTL, 0 },
0247     { SUBPIC_CNTL, 0 },
0248     { VIPH_CONTROL, 0 },
0249     { I2C_CNTL_1, 0 },
0250     { GEN_INT_CNTL, 0 },
0251     { CAP0_TRIG_CNTL, 0 },
0252     { CAP1_TRIG_CNTL, 0 },
0253 };
0254
0255 /*
0256  * globals
0257  */
0258
0259 static char *mode_option;
0260 static char *monitor_layout;
0261 static bool noaccel = 0;
0262 static int default_dynclk = -2;
0263 static bool nomodeset = 0;
0264 static bool ignore_edid = 0;
0265 static bool mirror = 0;
0266 static int panel_yres = 0;
0267 static bool force_dfp = 0;
0268 static bool force_measure_pll = 0;
0269 static bool nomtrr = 0;
0270 static bool force_sleep;
0271 static bool ignore_devlist;
0272 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
0273
0274 /* Note about this function: we have some rare cases where we must not schedule,
0275  * this typically happen with our special "wake up early" hook which allows us to
0276  * wake up the graphic chip (and thus get the console back) before everything else
0277  * on some machines that support that mechanism. At this point, interrupts are off
0278  * and scheduling is not permitted
0279  */
0280 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
0281 {
0282     if (rinfo->no_schedule || oops_in_progress)
0283         mdelay(ms);
0284     else
0285         msleep(ms);
0286 }
0287
0288 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
0289 {
0290     /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
0291     (void)INREG(CLOCK_CNTL_DATA);
0292     (void)INREG(CRTC_GEN_CNTL);
0293 }
0294
0295 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
0296 {
0297     if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
0298         /* we can't deal with posted writes here ... */
0299         _radeon_msleep(rinfo, 5);
0300     }
0301     if (rinfo->errata & CHIP_ERRATA_R300_CG) {
0302         u32 save, tmp;
0303         save = INREG(CLOCK_CNTL_INDEX);
0304         tmp = save & ~(0x3f | PLL_WR_EN);
0305         OUTREG(CLOCK_CNTL_INDEX, tmp);
0306         tmp = INREG(CLOCK_CNTL_DATA);
0307         OUTREG(CLOCK_CNTL_INDEX, save);
0308     }
0309 }
0310
0311 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
0312 {
0313     unsigned long flags;
0314     unsigned int tmp;
0315
0316     spin_lock_irqsave(&rinfo->reg_lock, flags);
0317     tmp = INREG(addr);
0318     tmp &= (mask);
0319     tmp |= (val);
0320     OUTREG(addr, tmp);
0321     spin_unlock_irqrestore(&rinfo->reg_lock, flags);
0322 }
0323
0324 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
0325 {
0326     u32 data;
0327
0328     OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
0329     radeon_pll_errata_after_index(rinfo);
0330     data = INREG(CLOCK_CNTL_DATA);
0331     radeon_pll_errata_after_data(rinfo);
0332     return data;
0333 }
0334
0335 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
0336 {
0337     OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
0338     radeon_pll_errata_after_index(rinfo);
0339     OUTREG(CLOCK_CNTL_DATA, val);
0340     radeon_pll_errata_after_data(rinfo);
0341 }
0342
0343 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
0344                  u32 val, u32 mask)
0345 {
0346     unsigned int tmp;
0347
0348     tmp  = __INPLL(rinfo, index);
0349     tmp &= (mask);
0350     tmp |= (val);
0351     __OUTPLL(rinfo, index, tmp);
0352 }
0353
0354 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
0355 {
0356     int i;
0357
0358     for (i=0; i<2000000; i++) {
0359         if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
0360             return;
0361         udelay(1);
0362     }
0363     printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
0364 }
0365
0366 void radeon_engine_flush(struct radeonfb_info *rinfo)
0367 {
0368     int i;
0369
0370     /* Initiate flush */
0371     OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
0372             ~RB2D_DC_FLUSH_ALL);
0373
0374     /* Ensure FIFO is empty, ie, make sure the flush commands
0375      * has reached the cache
0376      */
0377     _radeon_fifo_wait(rinfo, 64);
0378
0379     /* Wait for the flush to complete */
0380     for (i=0; i < 2000000; i++) {
0381         if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
0382             return;
0383         udelay(1);
0384     }
0385     printk(KERN_ERR "radeonfb: Flush Timeout !\n");
0386 }
0387
0388 void _radeon_engine_idle(struct radeonfb_info *rinfo)
0389 {
0390     int i;
0391
0392     /* ensure FIFO is empty before waiting for idle */
0393     _radeon_fifo_wait(rinfo, 64);
0394
0395     for (i=0; i<2000000; i++) {
0396         if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
0397             radeon_engine_flush(rinfo);
0398             return;
0399         }
0400         udelay(1);
0401     }
0402     printk(KERN_ERR "radeonfb: Idle Timeout !\n");
0403 }
0404
0405
0406
0407 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
0408 {
0409     if (!rinfo->bios_seg)
0410         return;
0411     pci_unmap_rom(dev, rinfo->bios_seg);
0412 }
0413
0414 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
0415 {
0416     void __iomem *rom;
0417     u16 dptr;
0418     u8 rom_type;
0419     size_t rom_size;
0420
0421     /* If this is a primary card, there is a shadow copy of the
0422      * ROM somewhere in the first meg. We will just ignore the copy
0423      * and use the ROM directly.
0424      */
0425
0426         /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
0427         unsigned int temp;
0428     temp = INREG(MPP_TB_CONFIG);
0429     temp &= 0x00ffffffu;
0430     temp |= 0x04 << 24;
0431     OUTREG(MPP_TB_CONFIG, temp);
0432     temp = INREG(MPP_TB_CONFIG);
0433
0434     rom = pci_map_rom(dev, &rom_size);
0435     if (!rom) {
0436         printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
0437                pci_name(rinfo->pdev));
0438         return -ENOMEM;
0439     }
0440
0441     rinfo->bios_seg = rom;
0442
0443     /* Very simple test to make sure it appeared */
0444     if (BIOS_IN16(0) != 0xaa55) {
0445         printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
0446             "should be 0xaa55\n",
0447             pci_name(rinfo->pdev), BIOS_IN16(0));
0448         goto failed;
0449     }
0450     /* Look for the PCI data to check the ROM type */
0451     dptr = BIOS_IN16(0x18);
0452
0453     /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
0454      * for now, until I've verified this works everywhere. The goal here is more
0455      * to phase out Open Firmware images.
0456      *
0457      * Currently, we only look at the first PCI data, we could iteratre and deal with
0458      * them all, and we should use fb_bios_start relative to start of image and not
0459      * relative start of ROM, but so far, I never found a dual-image ATI card
0460      *
0461      * typedef struct {
0462      *  u32 signature;  + 0x00
0463      *  u16 vendor;     + 0x04
0464      *  u16 device;     + 0x06
0465      *  u16 reserved_1; + 0x08
0466      *  u16 dlen;       + 0x0a
0467      *  u8  drevision;  + 0x0c
0468      *  u8  class_hi;   + 0x0d
0469      *  u16 class_lo;   + 0x0e
0470      *  u16 ilen;       + 0x10
0471      *  u16 irevision;  + 0x12
0472      *  u8  type;       + 0x14
0473      *  u8  indicator;  + 0x15
0474      *  u16 reserved_2; + 0x16
0475      * } pci_data_t;
0476      */
0477     if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
0478         printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
0479                "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
0480         goto anyway;
0481     }
0482     rom_type = BIOS_IN8(dptr + 0x14);
0483     switch(rom_type) {
0484     case 0:
0485         printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
0486         break;
0487     case 1:
0488         printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
0489         goto failed;
0490     case 2:
0491         printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
0492         goto failed;
0493     default:
0494         printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
0495         goto failed;
0496     }
0497  anyway:
0498     /* Locate the flat panel infos, do some sanity checking !!! */
0499     rinfo->fp_bios_start = BIOS_IN16(0x48);
0500     return 0;
0501
0502  failed:
0503     rinfo->bios_seg = NULL;
0504     radeon_unmap_ROM(rinfo, dev);
0505     return -ENXIO;
0506 }
0507
0508 #ifdef CONFIG_X86
0509 static int  radeon_find_mem_vbios(struct radeonfb_info *rinfo)
0510 {
0511     /* I simplified this code as we used to miss the signatures in
0512      * a lot of case. It's now closer to XFree, we just don't check
0513      * for signatures at all... Something better will have to be done
0514      * if we end up having conflicts
0515      */
0516         u32  segstart;
0517     void __iomem *rom_base = NULL;
0518
0519         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
0520                 rom_base = ioremap(segstart, 0x10000);
0521         if (rom_base == NULL)
0522             return -ENOMEM;
0523                 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
0524                     break;
0525                 iounmap(rom_base);
0526         rom_base = NULL;
0527         }
0528     if (rom_base == NULL)
0529         return -ENXIO;
0530
0531     /* Locate the flat panel infos, do some sanity checking !!! */
0532     rinfo->bios_seg = rom_base;
0533     rinfo->fp_bios_start = BIOS_IN16(0x48);
0534
0535     return 0;
0536 }
0537 #endif
0538
0539 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
0540 /*
0541  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
0542  * tree. Hopefully, ATI OF driver is kind enough to fill these
0543  */
0544 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
0545 {
0546     struct device_node *dp = rinfo->of_node;
0547     const u32 *val;
0548
0549     if (dp == NULL)
0550         return -ENODEV;
0551     val = of_get_property(dp, "ATY,RefCLK", NULL);
0552     if (!val || !*val) {
0553         printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
0554         return -EINVAL;
0555     }
0556
0557     rinfo->pll.ref_clk = (*val) / 10;
0558
0559     val = of_get_property(dp, "ATY,SCLK", NULL);
0560     if (val && *val)
0561         rinfo->pll.sclk = (*val) / 10;
0562
0563     val = of_get_property(dp, "ATY,MCLK", NULL);
0564     if (val && *val)
0565         rinfo->pll.mclk = (*val) / 10;
0566
0567         return 0;
0568 }
0569 #endif /* CONFIG_PPC || CONFIG_SPARC */
0570
0571 /*
0572  * Read PLL infos from chip registers
0573  */
0574 static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
0575 {
0576     unsigned char ppll_div_sel;
0577     unsigned Ns, Nm, M;
0578     unsigned sclk, mclk, tmp, ref_div;
0579     int hTotal, vTotal, num, denom, m, n;
0580     unsigned long long hz, vclk;
0581     long xtal;
0582     ktime_t start_time, stop_time;
0583     u64 total_usecs;
0584     int i;
0585
0586     /* Ugh, we cut interrupts, bad bad bad, but we want some precision
0587      * here, so... --BenH
0588      */
0589
0590     /* Flush PCI buffers ? */
0591     tmp = INREG16(DEVICE_ID);
0592
0593     local_irq_disable();
0594
0595     for(i=0; i<1000000; i++)
0596         if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
0597             break;
0598
0599     start_time = ktime_get();
0600
0601     for(i=0; i<1000000; i++)
0602         if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
0603             break;
0604
0605     for(i=0; i<1000000; i++)
0606         if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
0607             break;
0608
0609     stop_time = ktime_get();
0610
0611     local_irq_enable();
0612
0613     total_usecs = ktime_us_delta(stop_time, start_time);
0614     if (total_usecs >= 10 * USEC_PER_SEC || total_usecs == 0)
0615         return -1;
0616     hz = USEC_PER_SEC/(u32)total_usecs;
0617
0618     hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
0619     vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
0620     vclk = (long long)hTotal * (long long)vTotal * hz;
0621
0622     switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
0623     case 0:
0624     default:
0625         num = 1;
0626         denom = 1;
0627         break;
0628     case 1:
0629         n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
0630         m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
0631         num = 2*n;
0632         denom = 2*m;
0633         break;
0634     case 2:
0635         n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
0636         m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
0637         num = 2*n;
0638         denom = 2*m;
0639         break;
0640     }
0641
0642     ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
0643     radeon_pll_errata_after_index(rinfo);
0644
0645     n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
0646     m = (INPLL(PPLL_REF_DIV) & 0x3ff);
0647
0648     num *= n;
0649     denom *= m;
0650
0651     switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
0652     case 1:
0653         denom *= 2;
0654         break;
0655     case 2:
0656         denom *= 4;
0657         break;
0658     case 3:
0659         denom *= 8;
0660         break;
0661     case 4:
0662         denom *= 3;
0663         break;
0664     case 6:
0665         denom *= 6;
0666         break;
0667     case 7:
0668         denom *= 12;
0669         break;
0670     }
0671
0672     vclk *= denom;
0673     do_div(vclk, 1000 * num);
0674     xtal = vclk;
0675
0676     if ((xtal > 26900) && (xtal < 27100))
0677         xtal = 2700;
0678     else if ((xtal > 14200) && (xtal < 14400))
0679         xtal = 1432;
0680     else if ((xtal > 29400) && (xtal < 29600))
0681         xtal = 2950;
0682     else {
0683         printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
0684         return -1;
0685     }
0686
0687     tmp = INPLL(M_SPLL_REF_FB_DIV);
0688     ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
0689
0690     Ns = (tmp & 0xff0000) >> 16;
0691     Nm = (tmp & 0xff00) >> 8;
0692     M = (tmp & 0xff);
0693     sclk = round_div((2 * Ns * xtal), (2 * M));
0694     mclk = round_div((2 * Nm * xtal), (2 * M));
0695
0696     /* we're done, hopefully these are sane values */
0697     rinfo->pll.ref_clk = xtal;
0698     rinfo->pll.ref_div = ref_div;
0699     rinfo->pll.sclk = sclk;
0700     rinfo->pll.mclk = mclk;
0701
0702     return 0;
0703 }
0704
0705 /*
0706  * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
0707  */
0708 static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
0709 {
0710     /*
0711      * In the case nothing works, these are defaults; they are mostly
0712      * incomplete, however.  It does provide ppll_max and _min values
0713      * even for most other methods, however.
0714      */
0715     switch (rinfo->chipset) {
0716     case PCI_DEVICE_ID_ATI_RADEON_QW:
0717     case PCI_DEVICE_ID_ATI_RADEON_QX:
0718         rinfo->pll.ppll_max = 35000;
0719         rinfo->pll.ppll_min = 12000;
0720         rinfo->pll.mclk = 23000;
0721         rinfo->pll.sclk = 23000;
0722         rinfo->pll.ref_clk = 2700;
0723         break;
0724     case PCI_DEVICE_ID_ATI_RADEON_QL:
0725     case PCI_DEVICE_ID_ATI_RADEON_QN:
0726     case PCI_DEVICE_ID_ATI_RADEON_QO:
0727     case PCI_DEVICE_ID_ATI_RADEON_Ql:
0728     case PCI_DEVICE_ID_ATI_RADEON_BB:
0729         rinfo->pll.ppll_max = 35000;
0730         rinfo->pll.ppll_min = 12000;
0731         rinfo->pll.mclk = 27500;
0732         rinfo->pll.sclk = 27500;
0733         rinfo->pll.ref_clk = 2700;
0734         break;
0735     case PCI_DEVICE_ID_ATI_RADEON_Id:
0736     case PCI_DEVICE_ID_ATI_RADEON_Ie:
0737     case PCI_DEVICE_ID_ATI_RADEON_If:
0738     case PCI_DEVICE_ID_ATI_RADEON_Ig:
0739         rinfo->pll.ppll_max = 35000;
0740         rinfo->pll.ppll_min = 12000;
0741         rinfo->pll.mclk = 25000;
0742         rinfo->pll.sclk = 25000;
0743         rinfo->pll.ref_clk = 2700;
0744         break;
0745     case PCI_DEVICE_ID_ATI_RADEON_ND:
0746     case PCI_DEVICE_ID_ATI_RADEON_NE:
0747     case PCI_DEVICE_ID_ATI_RADEON_NF:
0748     case PCI_DEVICE_ID_ATI_RADEON_NG:
0749         rinfo->pll.ppll_max = 40000;
0750         rinfo->pll.ppll_min = 20000;
0751         rinfo->pll.mclk = 27000;
0752         rinfo->pll.sclk = 27000;
0753         rinfo->pll.ref_clk = 2700;
0754         break;
0755     case PCI_DEVICE_ID_ATI_RADEON_QD:
0756     case PCI_DEVICE_ID_ATI_RADEON_QE:
0757     case PCI_DEVICE_ID_ATI_RADEON_QF:
0758     case PCI_DEVICE_ID_ATI_RADEON_QG:
0759     default:
0760         rinfo->pll.ppll_max = 35000;
0761         rinfo->pll.ppll_min = 12000;
0762         rinfo->pll.mclk = 16600;
0763         rinfo->pll.sclk = 16600;
0764         rinfo->pll.ref_clk = 2700;
0765         break;
0766     }
0767     rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
0768
0769
0770 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
0771     /*
0772      * Retrieve PLL infos from Open Firmware first
0773      */
0774         if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
0775             printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
0776         goto found;
0777     }
0778 #endif /* CONFIG_PPC || CONFIG_SPARC */
0779
0780     /*
0781      * Check out if we have an X86 which gave us some PLL informations
0782      * and if yes, retrieve them
0783      */
0784     if (!force_measure_pll && rinfo->bios_seg) {
0785         u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
0786
0787         rinfo->pll.sclk     = BIOS_IN16(pll_info_block + 0x08);
0788         rinfo->pll.mclk     = BIOS_IN16(pll_info_block + 0x0a);
0789         rinfo->pll.ref_clk  = BIOS_IN16(pll_info_block + 0x0e);
0790         rinfo->pll.ref_div  = BIOS_IN16(pll_info_block + 0x10);
0791         rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
0792         rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
0793
0794         printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
0795         goto found;
0796     }
0797
0798     /*
0799      * We didn't get PLL parameters from either OF or BIOS, we try to
0800      * probe them
0801      */
0802     if (radeon_probe_pll_params(rinfo) == 0) {
0803         printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
0804         goto found;
0805     }
0806
0807     /*
0808      * Fall back to already-set defaults...
0809      */
0810         printk(KERN_INFO "radeonfb: Used default PLL infos\n");
0811
0812 found:
0813     /*
0814      * Some methods fail to retrieve SCLK and MCLK values, we apply default
0815      * settings in this case (200Mhz). If that really happens often, we
0816      * could fetch from registers instead...
0817      */
0818     if (rinfo->pll.mclk == 0)
0819         rinfo->pll.mclk = 20000;
0820     if (rinfo->pll.sclk == 0)
0821         rinfo->pll.sclk = 20000;
0822
0823     printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
0824            rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
0825            rinfo->pll.ref_div,
0826            rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
0827            rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
0828     printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
0829 }
0830
0831 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
0832 {
0833     struct radeonfb_info *rinfo = info->par;
0834         struct fb_var_screeninfo v;
0835         int nom, den;
0836     unsigned int pitch;
0837
0838     if (radeon_match_mode(rinfo, &v, var))
0839         return -EINVAL;
0840
0841         switch (v.bits_per_pixel) {
0842         case 0 ... 8:
0843             v.bits_per_pixel = 8;
0844             break;
0845         case 9 ... 16:
0846             v.bits_per_pixel = 16;
0847             break;
0848         case 25 ... 32:
0849             v.bits_per_pixel = 32;
0850             break;
0851         default:
0852             return -EINVAL;
0853     }
0854
0855     switch (var_to_depth(&v)) {
0856                 case 8:
0857                         nom = den = 1;
0858                         v.red.offset = v.green.offset = v.blue.offset = 0;
0859                         v.red.length = v.green.length = v.blue.length = 8;
0860                         v.transp.offset = v.transp.length = 0;
0861                         break;
0862         case 15:
0863             nom = 2;
0864             den = 1;
0865             v.red.offset = 10;
0866             v.green.offset = 5;
0867             v.blue.offset = 0;
0868             v.red.length = v.green.length = v.blue.length = 5;
0869             v.transp.offset = v.transp.length = 0;
0870             break;
0871                 case 16:
0872                         nom = 2;
0873                         den = 1;
0874                         v.red.offset = 11;
0875                         v.green.offset = 5;
0876                         v.blue.offset = 0;
0877                         v.red.length = 5;
0878                         v.green.length = 6;
0879                         v.blue.length = 5;
0880                         v.transp.offset = v.transp.length = 0;
0881                         break;
0882                 case 24:
0883                         nom = 4;
0884                         den = 1;
0885                         v.red.offset = 16;
0886                         v.green.offset = 8;
0887                         v.blue.offset = 0;
0888                         v.red.length = v.blue.length = v.green.length = 8;
0889                         v.transp.offset = v.transp.length = 0;
0890                         break;
0891                 case 32:
0892                         nom = 4;
0893                         den = 1;
0894                         v.red.offset = 16;
0895                         v.green.offset = 8;
0896                         v.blue.offset = 0;
0897                         v.red.length = v.blue.length = v.green.length = 8;
0898                         v.transp.offset = 24;
0899                         v.transp.length = 8;
0900                         break;
0901                 default:
0902                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
0903                                 var->xres, var->yres, var->bits_per_pixel);
0904                         return -EINVAL;
0905         }
0906
0907     if (v.yres_virtual < v.yres)
0908         v.yres_virtual = v.yres;
0909     if (v.xres_virtual < v.xres)
0910         v.xres_virtual = v.xres;
0911
0912
0913     /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
0914      * with some panels, though I don't quite like this solution
0915      */
0916     if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
0917         v.xres_virtual = v.xres_virtual & ~7ul;
0918     } else {
0919         pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
0920                 & ~(0x3f)) >> 6;
0921         v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
0922     }
0923
0924     if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
0925         return -EINVAL;
0926
0927     if (v.xres_virtual < v.xres)
0928         v.xres = v.xres_virtual;
0929
0930         if (v.xoffset > v.xres_virtual - v.xres)
0931                 v.xoffset = v.xres_virtual - v.xres - 1;
0932
0933         if (v.yoffset > v.yres_virtual - v.yres)
0934                 v.yoffset = v.yres_virtual - v.yres - 1;
0935
0936         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
0937                           v.transp.offset = v.transp.length =
0938                           v.transp.msb_right = 0;
0939
0940         memcpy(var, &v, sizeof(v));
0941
0942         return 0;
0943 }
0944
0945
0946 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
0947                                  struct fb_info *info)
0948 {
0949         struct radeonfb_info *rinfo = info->par;
0950
0951     if ((var->xoffset + info->var.xres > info->var.xres_virtual)
0952         || (var->yoffset + info->var.yres > info->var.yres_virtual))
0953         return -EINVAL;
0954
0955         if (rinfo->asleep)
0956             return 0;
0957
0958     radeon_fifo_wait(2);
0959     OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
0960                  var->xoffset * info->var.bits_per_pixel / 8) & ~7);
0961         return 0;
0962 }
0963
0964
0965 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
0966                            unsigned long arg)
0967 {
0968         struct radeonfb_info *rinfo = info->par;
0969     unsigned int tmp;
0970     u32 value = 0;
0971     int rc;
0972
0973     switch (cmd) {
0974         /*
0975          * TODO:  set mirror accordingly for non-Mobility chipsets with 2 CRTC's
0976          *        and do something better using 2nd CRTC instead of just hackish
0977          *        routing to second output
0978          */
0979         case FBIO_RADEON_SET_MIRROR:
0980             if (!rinfo->is_mobility)
0981                 return -EINVAL;
0982
0983             rc = get_user(value, (__u32 __user *)arg);
0984
0985             if (rc)
0986                 return rc;
0987
0988             radeon_fifo_wait(2);
0989             if (value & 0x01) {
0990                 tmp = INREG(LVDS_GEN_CNTL);
0991
0992                 tmp |= (LVDS_ON | LVDS_BLON);
0993             } else {
0994                 tmp = INREG(LVDS_GEN_CNTL);
0995
0996                 tmp &= ~(LVDS_ON | LVDS_BLON);
0997             }
0998
0999             OUTREG(LVDS_GEN_CNTL, tmp);
1000
1001             if (value & 0x02) {
1002                 tmp = INREG(CRTC_EXT_CNTL);
1003                 tmp |= CRTC_CRT_ON;
1004
1005                 mirror = 1;
1006             } else {
1007                 tmp = INREG(CRTC_EXT_CNTL);
1008                 tmp &= ~CRTC_CRT_ON;
1009
1010                 mirror = 0;
1011             }
1012
1013             OUTREG(CRTC_EXT_CNTL, tmp);
1014
1015             return 0;
1016         case FBIO_RADEON_GET_MIRROR:
1017             if (!rinfo->is_mobility)
1018                 return -EINVAL;
1019
1020             tmp = INREG(LVDS_GEN_CNTL);
1021             if ((LVDS_ON | LVDS_BLON) & tmp)
1022                 value |= 0x01;
1023
1024             tmp = INREG(CRTC_EXT_CNTL);
1025             if (CRTC_CRT_ON & tmp)
1026                 value |= 0x02;
1027
1028             return put_user(value, (__u32 __user *)arg);
1029         default:
1030             return -EINVAL;
1031     }
1032
1033     return -EINVAL;
1034 }
1035
1036
1037 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
1038 {
1039         u32 val;
1040     u32 tmp_pix_clks;
1041     int unblank = 0;
1042
1043     if (rinfo->lock_blank)
1044         return 0;
1045
1046     radeon_engine_idle();
1047
1048     val = INREG(CRTC_EXT_CNTL);
1049         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1050                  CRTC_VSYNC_DIS);
1051         switch (blank) {
1052     case FB_BLANK_VSYNC_SUSPEND:
1053         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1054         break;
1055     case FB_BLANK_HSYNC_SUSPEND:
1056         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1057         break;
1058     case FB_BLANK_POWERDOWN:
1059         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1060             CRTC_HSYNC_DIS);
1061         break;
1062     case FB_BLANK_NORMAL:
1063         val |= CRTC_DISPLAY_DIS;
1064         break;
1065     case FB_BLANK_UNBLANK:
1066     default:
1067         unblank = 1;
1068         }
1069     OUTREG(CRTC_EXT_CNTL, val);
1070
1071
1072     switch (rinfo->mon1_type) {
1073     case MT_DFP:
1074         if (unblank)
1075             OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
1076                 ~(FP_FPON | FP_TMDS_EN));
1077         else {
1078             if (mode_switch || blank == FB_BLANK_NORMAL)
1079                 break;
1080             OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
1081         }
1082         break;
1083     case MT_LCD:
1084         del_timer_sync(&rinfo->lvds_timer);
1085         val = INREG(LVDS_GEN_CNTL);
1086         if (unblank) {
1087             u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
1088                 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
1089                          & (LVDS_DIGON | LVDS_BL_MOD_EN));
1090             if ((val ^ target_val) == LVDS_DISPLAY_DIS)
1091                 OUTREG(LVDS_GEN_CNTL, target_val);
1092             else if ((val ^ target_val) != 0) {
1093                 OUTREG(LVDS_GEN_CNTL, target_val
1094                        & ~(LVDS_ON | LVDS_BL_MOD_EN));
1095                 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1096                 rinfo->init_state.lvds_gen_cntl |=
1097                     target_val & LVDS_STATE_MASK;
1098                 if (mode_switch) {
1099                     radeon_msleep(rinfo->panel_info.pwr_delay);
1100                     OUTREG(LVDS_GEN_CNTL, target_val);
1101                 }
1102                 else {
1103                     rinfo->pending_lvds_gen_cntl = target_val;
1104                     mod_timer(&rinfo->lvds_timer,
1105                        jiffies +
1106                        msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1107                 }
1108             }
1109         } else {
1110             val |= LVDS_DISPLAY_DIS;
1111             OUTREG(LVDS_GEN_CNTL, val);
1112
1113             /* We don't do a full switch-off on a simple mode switch */
1114             if (mode_switch || blank == FB_BLANK_NORMAL)
1115                 break;
1116
1117             /* Asic bug, when turning off LVDS_ON, we have to make sure
1118              * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1119              */
1120             tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1121             if (rinfo->is_mobility || rinfo->is_IGP)
1122                 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1123             val &= ~(LVDS_BL_MOD_EN);
1124             OUTREG(LVDS_GEN_CNTL, val);
1125             udelay(100);
1126             val &= ~(LVDS_ON | LVDS_EN);
1127             OUTREG(LVDS_GEN_CNTL, val);
1128             val &= ~LVDS_DIGON;
1129             rinfo->pending_lvds_gen_cntl = val;
1130             mod_timer(&rinfo->lvds_timer,
1131                   jiffies +
1132                   msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1133             rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1134             rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1135             if (rinfo->is_mobility || rinfo->is_IGP)
1136                 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1137         }
1138         break;
1139     case MT_CRT:
1140         // todo: powerdown DAC
1141     default:
1142         break;
1143     }
1144
1145     return 0;
1146 }
1147
1148 static int radeonfb_blank (int blank, struct fb_info *info)
1149 {
1150         struct radeonfb_info *rinfo = info->par;
1151
1152     if (rinfo->asleep)
1153         return 0;
1154
1155     return radeon_screen_blank(rinfo, blank, 0);
1156 }
1157
1158 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1159                              unsigned blue, unsigned transp,
1160                  struct radeonfb_info *rinfo)
1161 {
1162     u32 pindex;
1163     unsigned int i;
1164
1165
1166     if (regno > 255)
1167         return -EINVAL;
1168
1169     red >>= 8;
1170     green >>= 8;
1171     blue >>= 8;
1172     rinfo->palette[regno].red = red;
1173     rinfo->palette[regno].green = green;
1174     rinfo->palette[regno].blue = blue;
1175
1176         /* default */
1177         pindex = regno;
1178
1179         if (!rinfo->asleep) {
1180         radeon_fifo_wait(9);
1181
1182         if (rinfo->bpp == 16) {
1183             pindex = regno * 8;
1184
1185             if (rinfo->depth == 16 && regno > 63)
1186                 return -EINVAL;
1187             if (rinfo->depth == 15 && regno > 31)
1188                 return -EINVAL;
1189
1190             /* For 565, the green component is mixed one order
1191              * below
1192              */
1193             if (rinfo->depth == 16) {
1194                         OUTREG(PALETTE_INDEX, pindex>>1);
1195                         OUTREG(PALETTE_DATA,
1196                        (rinfo->palette[regno>>1].red << 16) |
1197                                 (green << 8) |
1198                        (rinfo->palette[regno>>1].blue));
1199                         green = rinfo->palette[regno<<1].green;
1200                 }
1201         }
1202
1203         if (rinfo->depth != 16 || regno < 32) {
1204             OUTREG(PALETTE_INDEX, pindex);
1205             OUTREG(PALETTE_DATA, (red << 16) |
1206                    (green << 8) | blue);
1207         }
1208     }
1209     if (regno < 16) {
1210         u32 *pal = rinfo->info->pseudo_palette;
1211             switch (rinfo->depth) {
1212         case 15:
1213             pal[regno] = (regno << 10) | (regno << 5) | regno;
1214             break;
1215         case 16:
1216             pal[regno] = (regno << 11) | (regno << 5) | regno;
1217             break;
1218         case 24:
1219             pal[regno] = (regno << 16) | (regno << 8) | regno;
1220             break;
1221         case 32:
1222             i = (regno << 8) | regno;
1223             pal[regno] = (i << 16) | i;
1224             break;
1225         }
1226         }
1227     return 0;
1228 }
1229
1230 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1231                    unsigned blue, unsigned transp,
1232                    struct fb_info *info)
1233 {
1234         struct radeonfb_info *rinfo = info->par;
1235     u32 dac_cntl2, vclk_cntl = 0;
1236     int rc;
1237
1238         if (!rinfo->asleep) {
1239         if (rinfo->is_mobility) {
1240             vclk_cntl = INPLL(VCLK_ECP_CNTL);
1241             OUTPLL(VCLK_ECP_CNTL,
1242                    vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1243         }
1244
1245         /* Make sure we are on first palette */
1246         if (rinfo->has_CRTC2) {
1247             dac_cntl2 = INREG(DAC_CNTL2);
1248             dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1249             OUTREG(DAC_CNTL2, dac_cntl2);
1250         }
1251     }
1252
1253     rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1254
1255     if (!rinfo->asleep && rinfo->is_mobility)
1256         OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1257
1258     return rc;
1259 }
1260
1261 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1262 {
1263         struct radeonfb_info *rinfo = info->par;
1264     u16 *red, *green, *blue, *transp;
1265     u32 dac_cntl2, vclk_cntl = 0;
1266     int i, start, rc = 0;
1267
1268         if (!rinfo->asleep) {
1269         if (rinfo->is_mobility) {
1270             vclk_cntl = INPLL(VCLK_ECP_CNTL);
1271             OUTPLL(VCLK_ECP_CNTL,
1272                    vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1273         }
1274
1275         /* Make sure we are on first palette */
1276         if (rinfo->has_CRTC2) {
1277             dac_cntl2 = INREG(DAC_CNTL2);
1278             dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1279             OUTREG(DAC_CNTL2, dac_cntl2);
1280         }
1281     }
1282
1283     red = cmap->red;
1284     green = cmap->green;
1285     blue = cmap->blue;
1286     transp = cmap->transp;
1287     start = cmap->start;
1288
1289     for (i = 0; i < cmap->len; i++) {
1290         u_int hred, hgreen, hblue, htransp = 0xffff;
1291
1292         hred = *red++;
1293         hgreen = *green++;
1294         hblue = *blue++;
1295         if (transp)
1296             htransp = *transp++;
1297         rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1298                        rinfo);
1299         if (rc)
1300             break;
1301     }
1302
1303     if (!rinfo->asleep && rinfo->is_mobility)
1304         OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1305
1306     return rc;
1307 }
1308
1309 static void radeon_save_state (struct radeonfb_info *rinfo,
1310                    struct radeon_regs *save)
1311 {
1312     /* CRTC regs */
1313     save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1314     save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1315     save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1316     save->dac_cntl = INREG(DAC_CNTL);
1317         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1318         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1319         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1320         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1321     save->crtc_pitch = INREG(CRTC_PITCH);
1322     save->surface_cntl = INREG(SURFACE_CNTL);
1323
1324     /* FP regs */
1325     save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1326     save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1327     save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1328     save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1329     save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1330     save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1331     save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1332     save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1333     save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1334     save->tmds_crc = INREG(TMDS_CRC);
1335     save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1336     save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1337
1338     /* PLL regs */
1339     save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1340     radeon_pll_errata_after_index(rinfo);
1341     save->ppll_div_3 = INPLL(PPLL_DIV_3);
1342     save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1343 }
1344
1345
1346 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1347 {
1348     int i;
1349
1350     radeon_fifo_wait(20);
1351
1352     /* Workaround from XFree */
1353     if (rinfo->is_mobility) {
1354             /* A temporal workaround for the occasional blanking on certain laptop
1355          * panels. This appears to related to the PLL divider registers
1356          * (fail to lock?). It occurs even when all dividers are the same
1357          * with their old settings. In this case we really don't need to
1358          * fiddle with PLL registers. By doing this we can avoid the blanking
1359          * problem with some panels.
1360              */
1361         if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1362             (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1363                       (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1364             /* We still have to force a switch to selected PPLL div thanks to
1365              * an XFree86 driver bug which will switch it away in some cases
1366              * even when using UseFDev */
1367             OUTREGP(CLOCK_CNTL_INDEX,
1368                 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1369                 ~PPLL_DIV_SEL_MASK);
1370             radeon_pll_errata_after_index(rinfo);
1371             radeon_pll_errata_after_data(rinfo);
1372                     return;
1373         }
1374     }
1375
1376     /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1377     OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1378
1379     /* Reset PPLL & enable atomic update */
1380     OUTPLLP(PPLL_CNTL,
1381         PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1382         ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1383
1384     /* Switch to selected PPLL divider */
1385     OUTREGP(CLOCK_CNTL_INDEX,
1386         mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1387         ~PPLL_DIV_SEL_MASK);
1388     radeon_pll_errata_after_index(rinfo);
1389     radeon_pll_errata_after_data(rinfo);
1390
1391     /* Set PPLL ref. div */
1392     if (IS_R300_VARIANT(rinfo) ||
1393         rinfo->family == CHIP_FAMILY_RS300 ||
1394         rinfo->family == CHIP_FAMILY_RS400 ||
1395         rinfo->family == CHIP_FAMILY_RS480) {
1396         if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1397             /* When restoring console mode, use saved PPLL_REF_DIV
1398              * setting.
1399              */
1400             OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1401         } else {
1402             /* R300 uses ref_div_acc field as real ref divider */
1403             OUTPLLP(PPLL_REF_DIV,
1404                 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1405                 ~R300_PPLL_REF_DIV_ACC_MASK);
1406         }
1407     } else
1408         OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1409
1410     /* Set PPLL divider 3 & post divider*/
1411     OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1412     OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1413
1414     /* Write update */
1415     while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1416         ;
1417     OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1418
1419     /* Wait read update complete */
1420     /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
1421        the cause yet, but this workaround will mask the problem for now.
1422        Other chips usually will pass at the very first test, so the
1423        workaround shouldn't have any effect on them. */
1424     for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1425         ;
1426
1427     OUTPLL(HTOTAL_CNTL, 0);
1428
1429     /* Clear reset & atomic update */
1430     OUTPLLP(PPLL_CNTL, 0,
1431         ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1432
1433     /* We may want some locking ... oh well */
1434         radeon_msleep(5);
1435
1436     /* Switch back VCLK source to PPLL */
1437     OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1438 }
1439
1440 /*
1441  * Timer function for delayed LVDS panel power up/down
1442  */
1443 static void radeon_lvds_timer_func(struct timer_list *t)
1444 {
1445     struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer);
1446
1447     radeon_engine_idle();
1448
1449     OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1450 }
1451
1452 /*
1453  * Apply a video mode. This will apply the whole register set, including
1454  * the PLL registers, to the card
1455  */
1456 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1457             int regs_only)
1458 {
1459     int i;
1460     int primary_mon = PRIMARY_MONITOR(rinfo);
1461
1462     if (nomodeset)
1463         return;
1464
1465     if (!regs_only)
1466         radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1467
1468     radeon_fifo_wait(31);
1469     for (i=0; i<10; i++)
1470         OUTREG(common_regs[i].reg, common_regs[i].val);
1471
1472     /* Apply surface registers */
1473     for (i=0; i<8; i++) {
1474         OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1475         OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1476         OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1477     }
1478
1479     OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1480     OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1481         ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1482     OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1483     OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1484     OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1485     OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1486     OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1487     OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1488     OUTREG(CRTC_OFFSET, 0);
1489     OUTREG(CRTC_OFFSET_CNTL, 0);
1490     OUTREG(CRTC_PITCH, mode->crtc_pitch);
1491     OUTREG(SURFACE_CNTL, mode->surface_cntl);
1492
1493     radeon_write_pll_regs(rinfo, mode);
1494
1495     if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1496         radeon_fifo_wait(10);
1497         OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1498         OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1499         OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1500         OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1501         OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1502         OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1503         OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1504         OUTREG(TMDS_CRC, mode->tmds_crc);
1505         OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1506     }
1507
1508     if (!regs_only)
1509         radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1510
1511     radeon_fifo_wait(2);
1512     OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1513
1514     return;
1515 }
1516
1517 /*
1518  * Calculate the PLL values for a given mode
1519  */
1520 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1521                  unsigned long freq)
1522 {
1523     static const struct {
1524         int divider;
1525         int bitvalue;
1526     } *post_div,
1527       post_divs[] = {
1528         { 1,  0 },
1529         { 2,  1 },
1530         { 4,  2 },
1531         { 8,  3 },
1532         { 3,  4 },
1533         { 16, 5 },
1534         { 6,  6 },
1535         { 12, 7 },
1536         { 0,  0 },
1537     };
1538     int fb_div, pll_output_freq = 0;
1539     int uses_dvo = 0;
1540
1541     /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1542      * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1543      * recent than an r(v)100...
1544      */
1545 #if 1
1546     /* XXX I had reports of flicker happening with the cinema display
1547      * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1548      * this case. This could just be a bandwidth calculation issue, I
1549      * haven't implemented the bandwidth code yet, but in the meantime,
1550      * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1551      * I haven't seen a case were were absolutely needed an odd PLL
1552      * divider. I'll find a better fix once I have more infos on the
1553      * real cause of the problem.
1554      */
1555     while (rinfo->has_CRTC2) {
1556         u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1557         u32 disp_output_cntl;
1558         int source;
1559
1560         /* FP2 path not enabled */
1561         if ((fp2_gen_cntl & FP2_ON) == 0)
1562             break;
1563         /* Not all chip revs have the same format for this register,
1564          * extract the source selection
1565          */
1566         if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1567             source = (fp2_gen_cntl >> 10) & 0x3;
1568             /* sourced from transform unit, check for transform unit
1569              * own source
1570              */
1571             if (source == 3) {
1572                 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1573                 source = (disp_output_cntl >> 12) & 0x3;
1574             }
1575         } else
1576             source = (fp2_gen_cntl >> 13) & 0x1;
1577         /* sourced from CRTC2 -> exit */
1578         if (source == 1)
1579             break;
1580
1581         /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1582         uses_dvo = 1;
1583         break;
1584     }
1585 #else
1586     uses_dvo = 1;
1587 #endif
1588     if (freq > rinfo->pll.ppll_max)
1589         freq = rinfo->pll.ppll_max;
1590     if (freq*12 < rinfo->pll.ppll_min)
1591         freq = rinfo->pll.ppll_min / 12;
1592     pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1593            freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1594
1595     for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1596         pll_output_freq = post_div->divider * freq;
1597         /* If we output to the DVO port (external TMDS), we don't allow an
1598          * odd PLL divider as those aren't supported on this path
1599          */
1600         if (uses_dvo && (post_div->divider & 1))
1601             continue;
1602         if (pll_output_freq >= rinfo->pll.ppll_min  &&
1603             pll_output_freq <= rinfo->pll.ppll_max)
1604             break;
1605     }
1606
1607     /* If we fall through the bottom, try the "default value"
1608        given by the terminal post_div->bitvalue */
1609     if ( !post_div->divider ) {
1610         post_div = &post_divs[post_div->bitvalue];
1611         pll_output_freq = post_div->divider * freq;
1612     }
1613     pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1614            rinfo->pll.ref_div, rinfo->pll.ref_clk,
1615            pll_output_freq);
1616
1617     /* If we fall through the bottom, try the "default value"
1618        given by the terminal post_div->bitvalue */
1619     if ( !post_div->divider ) {
1620         post_div = &post_divs[post_div->bitvalue];
1621         pll_output_freq = post_div->divider * freq;
1622     }
1623     pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1624            rinfo->pll.ref_div, rinfo->pll.ref_clk,
1625            pll_output_freq);
1626
1627     fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1628                   rinfo->pll.ref_clk);
1629     regs->ppll_ref_div = rinfo->pll.ref_div;
1630     regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1631
1632     pr_debug("post div = 0x%x\n", post_div->bitvalue);
1633     pr_debug("fb_div = 0x%x\n", fb_div);
1634     pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1635 }
1636
1637 static int radeonfb_set_par(struct fb_info *info)
1638 {
1639     struct radeonfb_info *rinfo = info->par;
1640     struct fb_var_screeninfo *mode = &info->var;
1641     struct radeon_regs *newmode;
1642     int hTotal, vTotal, hSyncStart, hSyncEnd,
1643         vSyncStart, vSyncEnd;
1644     u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1645     u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1646     u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1647     int i, freq;
1648     int format = 0;
1649     int nopllcalc = 0;
1650     int hsync_start, hsync_fudge, hsync_wid, vsync_wid;
1651     int primary_mon = PRIMARY_MONITOR(rinfo);
1652     int depth = var_to_depth(mode);
1653     int use_rmx = 0;
1654
1655     newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1656     if (!newmode)
1657         return -ENOMEM;
1658
1659     /* We always want engine to be idle on a mode switch, even
1660      * if we won't actually change the mode
1661      */
1662     radeon_engine_idle();
1663
1664     hSyncStart = mode->xres + mode->right_margin;
1665     hSyncEnd = hSyncStart + mode->hsync_len;
1666     hTotal = hSyncEnd + mode->left_margin;
1667
1668     vSyncStart = mode->yres + mode->lower_margin;
1669     vSyncEnd = vSyncStart + mode->vsync_len;
1670     vTotal = vSyncEnd + mode->upper_margin;
1671     pixClock = mode->pixclock;
1672
1673     sync = mode->sync;
1674     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1675     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1676
1677     if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1678         if (rinfo->panel_info.xres < mode->xres)
1679             mode->xres = rinfo->panel_info.xres;
1680         if (rinfo->panel_info.yres < mode->yres)
1681             mode->yres = rinfo->panel_info.yres;
1682
1683         hTotal = mode->xres + rinfo->panel_info.hblank;
1684         hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1685         hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1686
1687         vTotal = mode->yres + rinfo->panel_info.vblank;
1688         vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1689         vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1690
1691         h_sync_pol = !rinfo->panel_info.hAct_high;
1692         v_sync_pol = !rinfo->panel_info.vAct_high;
1693
1694         pixClock = 100000000 / rinfo->panel_info.clock;
1695
1696         if (rinfo->panel_info.use_bios_dividers) {
1697             nopllcalc = 1;
1698             newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1699                 (rinfo->panel_info.post_divider << 16);
1700             newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1701         }
1702     }
1703     dotClock = 1000000000 / pixClock;
1704     freq = dotClock / 10; /* x100 */
1705
1706     pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1707         hSyncStart, hSyncEnd, hTotal);
1708     pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1709         vSyncStart, vSyncEnd, vTotal);
1710
1711     hsync_wid = (hSyncEnd - hSyncStart) / 8;
1712     vsync_wid = vSyncEnd - vSyncStart;
1713     if (hsync_wid == 0)
1714         hsync_wid = 1;
1715     else if (hsync_wid > 0x3f)  /* max */
1716         hsync_wid = 0x3f;
1717
1718     if (vsync_wid == 0)
1719         vsync_wid = 1;
1720     else if (vsync_wid > 0x1f)  /* max */
1721         vsync_wid = 0x1f;
1722
1723     format = radeon_get_dstbpp(depth);
1724
1725     if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1726         hsync_fudge = hsync_fudge_fp[format-1];
1727     else
1728         hsync_fudge = hsync_adj_tab[format-1];
1729
1730     hsync_start = hSyncStart - 8 + hsync_fudge;
1731
1732     newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1733                 (format << 8);
1734
1735     /* Clear auto-center etc... */
1736     newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1737     newmode->crtc_more_cntl &= 0xfffffff0;
1738
1739     if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1740         newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1741         if (mirror)
1742             newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1743
1744         newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1745                        CRTC_INTERLACE_EN);
1746     } else {
1747         newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1748                     CRTC_CRT_ON;
1749     }
1750
1751     newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1752                DAC_8BIT_EN;
1753
1754     newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1755                      (((mode->xres / 8) - 1) << 16));
1756
1757     newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1758                     (hsync_wid << 16) | (h_sync_pol << 23));
1759
1760     newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1761                     ((mode->yres - 1) << 16);
1762
1763     newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1764                      (vsync_wid << 16) | (v_sync_pol  << 23));
1765
1766     if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1767         /* We first calculate the engine pitch */
1768         rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1769                 & ~(0x3f)) >> 6;
1770
1771         /* Then, re-multiply it to get the CRTC pitch */
1772         newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1773     } else
1774         newmode->crtc_pitch = (mode->xres_virtual >> 3);
1775
1776     newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1777
1778     /*
1779      * It looks like recent chips have a problem with SURFACE_CNTL,
1780      * setting SURF_TRANSLATION_DIS completely disables the
1781      * swapper as well, so we leave it unset now.
1782      */
1783     newmode->surface_cntl = 0;
1784
1785 #if defined(__BIG_ENDIAN)
1786
1787     /* Setup swapping on both apertures, though we currently
1788      * only use aperture 0, enabling swapper on aperture 1
1789      * won't harm
1790      */
1791     switch (mode->bits_per_pixel) {
1792         case 16:
1793             newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1794             newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1795             break;
1796         case 24:
1797         case 32:
1798             newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1799             newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1800             break;
1801     }
1802 #endif
1803
1804     /* Clear surface registers */
1805     for (i=0; i<8; i++) {
1806         newmode->surf_lower_bound[i] = 0;
1807         newmode->surf_upper_bound[i] = 0x1f;
1808         newmode->surf_info[i] = 0;
1809     }
1810
1811     pr_debug("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
1812         newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1813     pr_debug("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
1814         newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1815
1816     rinfo->bpp = mode->bits_per_pixel;
1817     rinfo->depth = depth;
1818
1819     pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1820     pr_debug("freq = %lu\n", (unsigned long)freq);
1821
1822     /* We use PPLL_DIV_3 */
1823     newmode->clk_cntl_index = 0x300;
1824
1825     /* Calculate PPLL value if necessary */
1826     if (!nopllcalc)
1827         radeon_calc_pll_regs(rinfo, newmode, freq);
1828
1829     newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1830
1831     if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1832         unsigned int hRatio, vRatio;
1833
1834         if (mode->xres > rinfo->panel_info.xres)
1835             mode->xres = rinfo->panel_info.xres;
1836         if (mode->yres > rinfo->panel_info.yres)
1837             mode->yres = rinfo->panel_info.yres;
1838
1839         newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1840                        << HORZ_PANEL_SHIFT);
1841         newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1842                        << VERT_PANEL_SHIFT);
1843
1844         if (mode->xres != rinfo->panel_info.xres) {
1845             hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1846                        rinfo->panel_info.xres);
1847             newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1848                            (newmode->fp_horz_stretch &
1849                             (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1850                              HORZ_AUTO_RATIO_INC)));
1851             newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1852                             HORZ_STRETCH_ENABLE);
1853             use_rmx = 1;
1854         }
1855         newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1856
1857         if (mode->yres != rinfo->panel_info.yres) {
1858             vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1859                        rinfo->panel_info.yres);
1860             newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1861                            (newmode->fp_vert_stretch &
1862                            (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1863             newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1864                             VERT_STRETCH_ENABLE);
1865             use_rmx = 1;
1866         }
1867         newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1868
1869         newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1870                        ~(FP_SEL_CRTC2 |
1871                      FP_RMX_HVSYNC_CONTROL_EN |
1872                      FP_DFP_SYNC_SEL |
1873                      FP_CRT_SYNC_SEL |
1874                      FP_CRTC_LOCK_8DOT |
1875                      FP_USE_SHADOW_EN |
1876                      FP_CRTC_USE_SHADOW_VEND |
1877                      FP_CRT_SYNC_ALT));
1878
1879         newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1880                     FP_CRTC_DONT_SHADOW_HEND |
1881                     FP_PANEL_FORMAT);
1882
1883         if (IS_R300_VARIANT(rinfo) ||
1884             (rinfo->family == CHIP_FAMILY_R200)) {
1885             newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1886             if (use_rmx)
1887                 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1888             else
1889                 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1890         } else
1891             newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1892
1893         newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1894         newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1895         newmode->tmds_crc = rinfo->init_state.tmds_crc;
1896         newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1897
1898         if (primary_mon == MT_LCD) {
1899             newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1900             newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1901         } else {
1902             /* DFP */
1903             newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1904             newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1905             /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1906             if (IS_R300_VARIANT(rinfo) ||
1907                 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1908                 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1909             else
1910                 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1911             newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1912         }
1913
1914         newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1915                 (((mode->xres / 8) - 1) << 16));
1916         newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1917                 ((mode->yres - 1) << 16);
1918         newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1919                 (hsync_wid << 16) | (h_sync_pol << 23));
1920         newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1921                 (vsync_wid << 16) | (v_sync_pol  << 23));
1922     }
1923
1924     /* do it! */
1925     if (!rinfo->asleep) {
1926         memcpy(&rinfo->state, newmode, sizeof(*newmode));
1927         radeon_write_mode (rinfo, newmode, 0);
1928         /* (re)initialize the engine */
1929         if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1930             radeonfb_engine_init (rinfo);
1931     }
1932     /* Update fix */
1933     if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1934             info->fix.line_length = rinfo->pitch*64;
1935         else
1936         info->fix.line_length = mode->xres_virtual
1937             * ((mode->bits_per_pixel + 1) / 8);
1938         info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1939         : FB_VISUAL_DIRECTCOLOR;
1940
1941 #ifdef CONFIG_BOOTX_TEXT
1942     /* Update debug text engine */
1943     btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1944                  rinfo->depth, info->fix.line_length);
1945 #endif
1946
1947     kfree(newmode);
1948     return 0;
1949 }
1950
1951
1952 static const struct fb_ops radeonfb_ops = {
1953     .owner          = THIS_MODULE,
1954     .fb_check_var       = radeonfb_check_var,
1955     .fb_set_par     = radeonfb_set_par,
1956     .fb_setcolreg       = radeonfb_setcolreg,
1957     .fb_setcmap     = radeonfb_setcmap,
1958     .fb_pan_display     = radeonfb_pan_display,
1959     .fb_blank       = radeonfb_blank,
1960     .fb_ioctl       = radeonfb_ioctl,
1961     .fb_sync        = radeonfb_sync,
1962     .fb_fillrect        = radeonfb_fillrect,
1963     .fb_copyarea        = radeonfb_copyarea,
1964     .fb_imageblit       = radeonfb_imageblit,
1965 };
1966
1967
1968 static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1969 {
1970     struct fb_info *info = rinfo->info;
1971
1972     info->par = rinfo;
1973     info->pseudo_palette = rinfo->pseudo_palette;
1974     info->flags = FBINFO_DEFAULT
1975             | FBINFO_HWACCEL_COPYAREA
1976             | FBINFO_HWACCEL_FILLRECT
1977             | FBINFO_HWACCEL_XPAN
1978             | FBINFO_HWACCEL_YPAN;
1979     info->fbops = &radeonfb_ops;
1980     info->screen_base = rinfo->fb_base;
1981     info->screen_size = rinfo->mapped_vram;
1982     /* Fill fix common fields */
1983     strscpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1984         info->fix.smem_start = rinfo->fb_base_phys;
1985         info->fix.smem_len = rinfo->video_ram;
1986         info->fix.type = FB_TYPE_PACKED_PIXELS;
1987         info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1988         info->fix.xpanstep = 8;
1989         info->fix.ypanstep = 1;
1990         info->fix.ywrapstep = 0;
1991         info->fix.type_aux = 0;
1992         info->fix.mmio_start = rinfo->mmio_base_phys;
1993         info->fix.mmio_len = RADEON_REGSIZE;
1994     info->fix.accel = FB_ACCEL_ATI_RADEON;
1995
1996     fb_alloc_cmap(&info->cmap, 256, 0);
1997
1998     if (noaccel)
1999         info->flags |= FBINFO_HWACCEL_DISABLED;
2000
2001         return 0;
2002 }
2003
2004 /*
2005  * This reconfigure the card's internal memory map. In theory, we'd like
2006  * to setup the card's memory at the same address as it's PCI bus address,
2007  * and the AGP aperture right after that so that system RAM on 32 bits
2008  * machines at least, is directly accessible. However, doing so would
2009  * conflict with the current XFree drivers...
2010  * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2011  * on the proper way to set this up and duplicate this here. In the meantime,
2012  * I put the card's memory at 0 in card space and AGP at some random high
2013  * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
2014  */
2015 #ifdef CONFIG_PPC
2016 #undef SET_MC_FB_FROM_APERTURE
2017 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2018 {
2019     u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
2020     u32 save_crtc_ext_cntl;
2021     u32 aper_base, aper_size;
2022     u32 agp_base;
2023
2024     /* First, we disable display to avoid interfering */
2025     if (rinfo->has_CRTC2) {
2026         save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
2027         OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
2028     }
2029     save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2030     save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2031
2032     OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
2033     OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
2034     mdelay(100);
2035
2036     aper_base = INREG(CNFG_APER_0_BASE);
2037     aper_size = INREG(CNFG_APER_SIZE);
2038
2039 #ifdef SET_MC_FB_FROM_APERTURE
2040     /* Set framebuffer to be at the same address as set in PCI BAR */
2041     OUTREG(MC_FB_LOCATION,
2042         ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
2043     rinfo->fb_local_base = aper_base;
2044 #else
2045     OUTREG(MC_FB_LOCATION, 0x7fff0000);
2046     rinfo->fb_local_base = 0;
2047 #endif
2048     agp_base = aper_base + aper_size;
2049     if (agp_base & 0xf0000000)
2050         agp_base = (aper_base | 0x0fffffff) + 1;
2051
2052     /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2053      * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2054      * always the case on PPCs afaik.
2055      */
2056 #ifdef SET_MC_FB_FROM_APERTURE
2057     OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2058 #else
2059     OUTREG(MC_AGP_LOCATION, 0xffffe000);
2060 #endif
2061
2062     /* Fixup the display base addresses & engine offsets while we
2063      * are at it as well
2064      */
2065 #ifdef SET_MC_FB_FROM_APERTURE
2066     OUTREG(DISPLAY_BASE_ADDR, aper_base);
2067     if (rinfo->has_CRTC2)
2068         OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2069     OUTREG(OV0_BASE_ADDR, aper_base);
2070 #else
2071     OUTREG(DISPLAY_BASE_ADDR, 0);
2072     if (rinfo->has_CRTC2)
2073         OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2074     OUTREG(OV0_BASE_ADDR, 0);
2075 #endif
2076     mdelay(100);
2077
2078     /* Restore display settings */
2079     OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2080     OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2081     if (rinfo->has_CRTC2)
2082         OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2083
2084     pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2085         aper_base,
2086         ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2087         0xffff0000 | (agp_base >> 16));
2088 }
2089 #endif /* CONFIG_PPC */
2090
2091
2092 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2093 {
2094     u32 tmp;
2095
2096     /* framebuffer size */
2097     if ((rinfo->family == CHIP_FAMILY_RS100) ||
2098             (rinfo->family == CHIP_FAMILY_RS200) ||
2099             (rinfo->family == CHIP_FAMILY_RS300) ||
2100             (rinfo->family == CHIP_FAMILY_RC410) ||
2101             (rinfo->family == CHIP_FAMILY_RS400) ||
2102         (rinfo->family == CHIP_FAMILY_RS480) ) {
2103         u32 tom = INREG(NB_TOM);
2104
2105         tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2106         radeon_fifo_wait(6);
2107         OUTREG(MC_FB_LOCATION, tom);
2108         OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2109         OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2110         OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2111
2112         /* This is supposed to fix the crtc2 noise problem. */
2113         OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2114
2115         if ((rinfo->family == CHIP_FAMILY_RS100) ||
2116             (rinfo->family == CHIP_FAMILY_RS200)) {
2117             /* This is to workaround the asic bug for RMX, some versions
2118              * of BIOS doesn't have this register initialized correctly.
2119              */
2120             OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2121                 ~CRTC_H_CUTOFF_ACTIVE_EN);
2122         }
2123     } else {
2124         tmp = INREG(CNFG_MEMSIZE);
2125         }
2126
2127     /* mem size is bits [28:0], mask off the rest */
2128     rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2129
2130     /*
2131      * Hack to get around some busted production M6's
2132      * reporting no ram
2133      */
2134     if (rinfo->video_ram == 0) {
2135         switch (rinfo->pdev->device) {
2136             case PCI_CHIP_RADEON_LY:
2137         case PCI_CHIP_RADEON_LZ:
2138                 rinfo->video_ram = 8192 * 1024;
2139                 break;
2140             default:
2141                 break;
2142         }
2143     }
2144
2145
2146     /*
2147      * Now try to identify VRAM type
2148      */
2149     if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2150         (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2151         rinfo->vram_ddr = 1;
2152     else
2153         rinfo->vram_ddr = 0;
2154
2155     tmp = INREG(MEM_CNTL);
2156     if (IS_R300_VARIANT(rinfo)) {
2157         tmp &=  R300_MEM_NUM_CHANNELS_MASK;
2158         switch (tmp) {
2159         case 0:  rinfo->vram_width = 64; break;
2160         case 1:  rinfo->vram_width = 128; break;
2161         case 2:  rinfo->vram_width = 256; break;
2162         default: rinfo->vram_width = 128; break;
2163         }
2164     } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2165            (rinfo->family == CHIP_FAMILY_RS100) ||
2166            (rinfo->family == CHIP_FAMILY_RS200)){
2167         if (tmp & RV100_MEM_HALF_MODE)
2168             rinfo->vram_width = 32;
2169         else
2170             rinfo->vram_width = 64;
2171     } else {
2172         if (tmp & MEM_NUM_CHANNELS_MASK)
2173             rinfo->vram_width = 128;
2174         else
2175             rinfo->vram_width = 64;
2176     }
2177
2178     /* This may not be correct, as some cards can have half of channel disabled
2179      * ToDo: identify these cases
2180      */
2181
2182     pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2183            pci_name(rinfo->pdev),
2184            rinfo->video_ram / 1024,
2185            rinfo->vram_ddr ? "DDR" : "SDRAM",
2186            rinfo->vram_width);
2187 }
2188
2189 /*
2190  * Sysfs
2191  */
2192
2193 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2194 {
2195     return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
2196 }
2197
2198
2199 static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
2200                  struct bin_attribute *bin_attr,
2201                  char *buf, loff_t off, size_t count)
2202 {
2203     struct device *dev = kobj_to_dev(kobj);
2204     struct fb_info *info = dev_get_drvdata(dev);
2205         struct radeonfb_info *rinfo = info->par;
2206
2207     return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2208 }
2209
2210
2211 static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
2212                  struct bin_attribute *bin_attr,
2213                  char *buf, loff_t off, size_t count)
2214 {
2215     struct device *dev = kobj_to_dev(kobj);
2216     struct fb_info *info = dev_get_drvdata(dev);
2217         struct radeonfb_info *rinfo = info->par;
2218
2219     return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2220 }
2221
2222 static const struct bin_attribute edid1_attr = {
2223     .attr   = {
2224         .name   = "edid1",
2225         .mode   = 0444,
2226     },
2227     .size   = EDID_LENGTH,
2228     .read   = radeon_show_edid1,
2229 };
2230
2231 static const struct bin_attribute edid2_attr = {
2232     .attr   = {
2233         .name   = "edid2",
2234         .mode   = 0444,
2235     },
2236     .size   = EDID_LENGTH,
2237     .read   = radeon_show_edid2,
2238 };
2239
2240 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
2241 {
2242     struct apertures_struct *ap;
2243
2244     ap = alloc_apertures(1);
2245     if (!ap)
2246         return -ENOMEM;
2247
2248     ap->ranges[0].base = pci_resource_start(pdev, 0);
2249     ap->ranges[0].size = pci_resource_len(pdev, 0);
2250
2251     remove_conflicting_framebuffers(ap, KBUILD_MODNAME, false);
2252
2253     kfree(ap);
2254
2255     return 0;
2256 }
2257
2258 static int radeonfb_pci_register(struct pci_dev *pdev,
2259                  const struct pci_device_id *ent)
2260 {
2261     struct fb_info *info;
2262     struct radeonfb_info *rinfo;
2263     int ret;
2264     unsigned char c1, c2;
2265     int err = 0;
2266
2267     pr_debug("radeonfb_pci_register BEGIN\n");
2268
2269     /* Enable device in PCI config */
2270     ret = pci_enable_device(pdev);
2271     if (ret < 0) {
2272         printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2273                pci_name(pdev));
2274         goto err_out;
2275     }
2276
2277     info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2278     if (!info) {
2279         ret = -ENOMEM;
2280         goto err_disable;
2281     }
2282     rinfo = info->par;
2283     rinfo->info = info;
2284     rinfo->pdev = pdev;
2285
2286     spin_lock_init(&rinfo->reg_lock);
2287     timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0);
2288
2289     c1 = ent->device >> 8;
2290     c2 = ent->device & 0xff;
2291     if (isprint(c1) && isprint(c2))
2292         snprintf(rinfo->name, sizeof(rinfo->name),
2293              "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2294     else
2295         snprintf(rinfo->name, sizeof(rinfo->name),
2296              "ATI Radeon %x", ent->device & 0xffff);
2297
2298     rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2299     rinfo->chipset = pdev->device;
2300     rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2301     rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2302     rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2303
2304     /* Set base addrs */
2305     rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2306     rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2307
2308     ret = radeon_kick_out_firmware_fb(pdev);
2309     if (ret)
2310         goto err_release_fb;
2311
2312     /* request the mem regions */
2313     ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2314     if (ret < 0) {
2315         printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2316             pci_name(rinfo->pdev));
2317         goto err_release_fb;
2318     }
2319
2320     ret = pci_request_region(pdev, 2, "radeonfb mmio");
2321     if (ret < 0) {
2322         printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2323             pci_name(rinfo->pdev));
2324         goto err_release_pci0;
2325     }
2326
2327     /* map the regions */
2328     rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2329     if (!rinfo->mmio_base) {
2330         printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2331                pci_name(rinfo->pdev));
2332         ret = -EIO;
2333         goto err_release_pci2;
2334     }
2335
2336     rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2337
2338     /*
2339      * Check for errata
2340      */
2341     rinfo->errata = 0;
2342     if (rinfo->family == CHIP_FAMILY_R300 &&
2343         (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
2344         == CFG_ATI_REV_A11)
2345         rinfo->errata |= CHIP_ERRATA_R300_CG;
2346
2347     if (rinfo->family == CHIP_FAMILY_RV200 ||
2348         rinfo->family == CHIP_FAMILY_RS200)
2349         rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2350
2351     if (rinfo->family == CHIP_FAMILY_RV100 ||
2352         rinfo->family == CHIP_FAMILY_RS100 ||
2353         rinfo->family == CHIP_FAMILY_RS200)
2354         rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2355
2356 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
2357     /* On PPC, we obtain the OF device-node pointer to the firmware
2358      * data for this chip
2359      */
2360     rinfo->of_node = pci_device_to_OF_node(pdev);
2361     if (rinfo->of_node == NULL)
2362         printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2363                pci_name(rinfo->pdev));
2364
2365 #endif /* CONFIG_PPC || CONFIG_SPARC */
2366 #ifdef CONFIG_PPC
2367     /* On PPC, the firmware sets up a memory mapping that tends
2368      * to cause lockups when enabling the engine. We reconfigure
2369      * the card internal memory mappings properly
2370      */
2371     fixup_memory_mappings(rinfo);
2372 #endif /* CONFIG_PPC */
2373
2374     /* Get VRAM size and type */
2375     radeon_identify_vram(rinfo);
2376
2377     rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2378
2379     do {
2380         rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
2381                         rinfo->mapped_vram);
2382     } while (rinfo->fb_base == NULL &&
2383          ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2384
2385     if (rinfo->fb_base == NULL) {
2386         printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2387             pci_name(rinfo->pdev));
2388         ret = -EIO;
2389         goto err_unmap_rom;
2390     }
2391
2392     pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2393            rinfo->mapped_vram/1024);
2394
2395     /*
2396      * Map the BIOS ROM if any and retrieve PLL parameters from
2397      * the BIOS. We skip that on mobility chips as the real panel
2398      * values we need aren't in the ROM but in the BIOS image in
2399      * memory. This is definitely not the best meacnism though,
2400      * we really need the arch code to tell us which is the "primary"
2401      * video adapter to use the memory image (or better, the arch
2402      * should provide us a copy of the BIOS image to shield us from
2403      * archs who would store that elsewhere and/or could initialize
2404      * more than one adapter during boot).
2405      */
2406     if (!rinfo->is_mobility)
2407         radeon_map_ROM(rinfo, pdev);
2408
2409     /*
2410      * On x86, the primary display on laptop may have it's BIOS
2411      * ROM elsewhere, try to locate it at the legacy memory hole.
2412      * We probably need to make sure this is the primary display,
2413      * but that is difficult without some arch support.
2414      */
2415 #ifdef CONFIG_X86
2416     if (rinfo->bios_seg == NULL)
2417         radeon_find_mem_vbios(rinfo);
2418 #endif
2419
2420     /* If both above failed, try the BIOS ROM again for mobility
2421      * chips
2422      */
2423     if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2424         radeon_map_ROM(rinfo, pdev);
2425
2426     /* Get informations about the board's PLL */
2427     radeon_get_pllinfo(rinfo);
2428
2429 #ifdef CONFIG_FB_RADEON_I2C
2430     /* Register I2C bus */
2431     radeon_create_i2c_busses(rinfo);
2432 #endif
2433
2434     /* set all the vital stuff */
2435     radeon_set_fbinfo (rinfo);
2436
2437     /* Probe screen types */
2438     radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2439
2440     /* Build mode list, check out panel native model */
2441     radeon_check_modes(rinfo, mode_option);
2442
2443     /* Register some sysfs stuff (should be done better) */
2444     if (rinfo->mon1_EDID)
2445         err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2446                         &edid1_attr);
2447     if (rinfo->mon2_EDID)
2448         err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2449                         &edid2_attr);
2450     if (err)
2451         pr_warn("%s() Creating sysfs files failed, continuing\n",
2452             __func__);
2453
2454     /* save current mode regs before we switch into the new one
2455      * so we can restore this upon __exit
2456      */
2457     radeon_save_state (rinfo, &rinfo->init_state);
2458     memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2459
2460     /* Setup Power Management capabilities */
2461     if (default_dynclk < -1) {
2462         /* -2 is special: means  ON on mobility chips and do not
2463          * change on others
2464          */
2465         radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2466     } else
2467         radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2468
2469     pci_set_drvdata(pdev, info);
2470
2471     /* Register with fbdev layer */
2472     ret = register_framebuffer(info);
2473     if (ret < 0) {
2474         printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2475             pci_name(rinfo->pdev));
2476         goto err_unmap_fb;
2477     }
2478
2479     if (!nomtrr)
2480         rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
2481                             rinfo->video_ram);
2482
2483     if (backlight)
2484         radeonfb_bl_init(rinfo);
2485
2486     printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2487
2488     if (rinfo->bios_seg)
2489         radeon_unmap_ROM(rinfo, pdev);
2490     pr_debug("radeonfb_pci_register END\n");
2491
2492     return 0;
2493 err_unmap_fb:
2494     iounmap(rinfo->fb_base);
2495 err_unmap_rom:
2496     kfree(rinfo->mon1_EDID);
2497     kfree(rinfo->mon2_EDID);
2498     if (rinfo->mon1_modedb)
2499         fb_destroy_modedb(rinfo->mon1_modedb);
2500     fb_dealloc_cmap(&info->cmap);
2501 #ifdef CONFIG_FB_RADEON_I2C
2502     radeon_delete_i2c_busses(rinfo);
2503 #endif
2504     if (rinfo->bios_seg)
2505         radeon_unmap_ROM(rinfo, pdev);
2506     iounmap(rinfo->mmio_base);
2507 err_release_pci2:
2508     pci_release_region(pdev, 2);
2509 err_release_pci0:
2510     pci_release_region(pdev, 0);
2511 err_release_fb:
2512         framebuffer_release(info);
2513 err_disable:
2514 err_out:
2515     return ret;
2516 }
2517
2518
2519
2520 static void radeonfb_pci_unregister(struct pci_dev *pdev)
2521 {
2522         struct fb_info *info = pci_get_drvdata(pdev);
2523         struct radeonfb_info *rinfo = info->par;
2524
2525         if (!rinfo)
2526                 return;
2527
2528     radeonfb_pm_exit(rinfo);
2529
2530     if (rinfo->mon1_EDID)
2531         sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2532     if (rinfo->mon2_EDID)
2533         sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2534
2535     del_timer_sync(&rinfo->lvds_timer);
2536     arch_phys_wc_del(rinfo->wc_cookie);
2537         unregister_framebuffer(info);
2538
2539         radeonfb_bl_exit(rinfo);
2540
2541         iounmap(rinfo->mmio_base);
2542         iounmap(rinfo->fb_base);
2543
2544     pci_release_region(pdev, 2);
2545     pci_release_region(pdev, 0);
2546
2547     kfree(rinfo->mon1_EDID);
2548     kfree(rinfo->mon2_EDID);
2549     if (rinfo->mon1_modedb)
2550         fb_destroy_modedb(rinfo->mon1_modedb);
2551 #ifdef CONFIG_FB_RADEON_I2C
2552     radeon_delete_i2c_busses(rinfo);
2553 #endif
2554     fb_dealloc_cmap(&info->cmap);
2555         framebuffer_release(info);
2556 }
2557
2558 #ifdef CONFIG_PM
2559 #define RADEONFB_PCI_PM_OPS (&radeonfb_pci_pm_ops)
2560 #else
2561 #define RADEONFB_PCI_PM_OPS NULL
2562 #endif
2563
2564 static struct pci_driver radeonfb_driver = {
2565     .name       = "radeonfb",
2566     .id_table   = radeonfb_pci_table,
2567     .probe      = radeonfb_pci_register,
2568     .remove     = radeonfb_pci_unregister,
2569     .driver.pm  = RADEONFB_PCI_PM_OPS,
2570 };
2571
2572 #ifndef MODULE
2573 static int __init radeonfb_setup (char *options)
2574 {
2575     char *this_opt;
2576
2577     if (!options || !*options)
2578         return 0;
2579
2580     while ((this_opt = strsep (&options, ",")) != NULL) {
2581         if (!*this_opt)
2582             continue;
2583
2584         if (!strncmp(this_opt, "noaccel", 7)) {
2585             noaccel = 1;
2586         } else if (!strncmp(this_opt, "mirror", 6)) {
2587             mirror = 1;
2588         } else if (!strncmp(this_opt, "force_dfp", 9)) {
2589             force_dfp = 1;
2590         } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2591             panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2592         } else if (!strncmp(this_opt, "backlight:", 10)) {
2593             backlight = simple_strtoul(this_opt+10, NULL, 0);
2594         } else if (!strncmp(this_opt, "nomtrr", 6)) {
2595             nomtrr = 1;
2596         } else if (!strncmp(this_opt, "nomodeset", 9)) {
2597             nomodeset = 1;
2598         } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2599             force_measure_pll = 1;
2600         } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2601             ignore_edid = 1;
2602 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2603         } else if (!strncmp(this_opt, "force_sleep", 11)) {
2604             force_sleep = 1;
2605         } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2606             ignore_devlist = 1;
2607 #endif
2608         } else
2609             mode_option = this_opt;
2610     }
2611     return 0;
2612 }
2613 #endif  /*  MODULE  */
2614
2615 static int __init radeonfb_init (void)
2616 {
2617 #ifndef MODULE
2618     char *option = NULL;
2619
2620     if (fb_get_options("radeonfb", &option))
2621         return -ENODEV;
2622     radeonfb_setup(option);
2623 #endif
2624     return pci_register_driver (&radeonfb_driver);
2625 }
2626
2627
2628 static void __exit radeonfb_exit (void)
2629 {
2630     pci_unregister_driver (&radeonfb_driver);
2631 }
2632
2633 module_init(radeonfb_init);
2634 module_exit(radeonfb_exit);
2635
2636 MODULE_AUTHOR("Ani Joshi");
2637 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2638 MODULE_LICENSE("GPL");
2639 module_param(noaccel, bool, 0);
2640 module_param(default_dynclk, int, 0);
2641 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2642 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2643 module_param(nomodeset, bool, 0);
2644 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2645 module_param(mirror, bool, 0);
2646 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2647 module_param(force_dfp, bool, 0);
2648 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2649 module_param(ignore_edid, bool, 0);
2650 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2651 module_param(monitor_layout, charp, 0);
2652 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2653 module_param(force_measure_pll, bool, 0);
2654 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2655 module_param(nomtrr, bool, 0);
2656 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2657 module_param(panel_yres, int, 0);
2658 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2659 module_param(mode_option, charp, 0);
2660 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2661 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2662 module_param(force_sleep, bool, 0);
2663 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2664 module_param(ignore_devlist, bool, 0);
2665 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2666 #endif