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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
0003  *  linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
0004  *
0005  *  Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
0006  *  Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
0007  *
0008  *                Ani Joshi / Jeff Garzik
0009  *                      - Code cleanup
0010  *
0011  *                Michel Danzer <michdaen@iiic.ethz.ch>
0012  *                      - 15/16 bit cleanup
0013  *                      - fix panning
0014  *
0015  *                Benjamin Herrenschmidt
0016  *                      - pmac-specific PM stuff
0017  *          - various fixes & cleanups
0018  *
0019  *                Andreas Hundt <andi@convergence.de>
0020  *                      - FB_ACTIVATE fixes
0021  *
0022  *        Paul Mackerras <paulus@samba.org>
0023  *          - Convert to new framebuffer API,
0024  *            fix colormap setting at 16 bits/pixel (565)
0025  *
0026  *        Paul Mundt 
0027  *          - PCI hotplug
0028  *
0029  *        Jon Smirl <jonsmirl@yahoo.com>
0030  *          - PCI ID update
0031  *          - replace ROM BIOS search
0032  *
0033  *  Based off of Geert's atyfb.c and vfb.c.
0034  *
0035  *  TODO:
0036  *      - monitor sensing (DDC)
0037  *              - virtual display
0038  *      - other platform support (only ppc/x86 supported)
0039  *      - hardware cursor support
0040  *
0041  *    Please cc: your patches to brad@neruo.com.
0042  */
0043 
0044 /*
0045  * A special note of gratitude to ATI's devrel for providing documentation,
0046  * example code and hardware. Thanks Nitya. -atong and brad
0047  */
0048 
0049 
0050 #include <linux/module.h>
0051 #include <linux/moduleparam.h>
0052 #include <linux/kernel.h>
0053 #include <linux/errno.h>
0054 #include <linux/string.h>
0055 #include <linux/mm.h>
0056 #include <linux/vmalloc.h>
0057 #include <linux/delay.h>
0058 #include <linux/interrupt.h>
0059 #include <linux/uaccess.h>
0060 #include <linux/fb.h>
0061 #include <linux/init.h>
0062 #include <linux/pci.h>
0063 #include <linux/ioport.h>
0064 #include <linux/console.h>
0065 #include <linux/backlight.h>
0066 #include <asm/io.h>
0067 
0068 #ifdef CONFIG_PPC_PMAC
0069 #include <asm/machdep.h>
0070 #include <asm/pmac_feature.h>
0071 #include "../macmodes.h"
0072 #endif
0073 
0074 #ifdef CONFIG_PMAC_BACKLIGHT
0075 #include <asm/backlight.h>
0076 #endif
0077 
0078 #ifdef CONFIG_BOOTX_TEXT
0079 #include <asm/btext.h>
0080 #endif /* CONFIG_BOOTX_TEXT */
0081 
0082 #include <video/aty128.h>
0083 
0084 /* Debug flag */
0085 #undef DEBUG
0086 
0087 #ifdef DEBUG
0088 #define DBG(fmt, args...) \
0089     printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
0090 #else
0091 #define DBG(fmt, args...)
0092 #endif
0093 
0094 #ifndef CONFIG_PPC_PMAC
0095 /* default mode */
0096 static const struct fb_var_screeninfo default_var = {
0097     /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
0098     640, 480, 640, 480, 0, 0, 8, 0,
0099     {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
0100     0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
0101     0, FB_VMODE_NONINTERLACED
0102 };
0103 
0104 #else /* CONFIG_PPC_PMAC */
0105 /* default to 1024x768 at 75Hz on PPC - this will work
0106  * on the iMac, the usual 640x480 @ 60Hz doesn't. */
0107 static const struct fb_var_screeninfo default_var = {
0108     /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
0109     1024, 768, 1024, 768, 0, 0, 8, 0,
0110     {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
0111     0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
0112     FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
0113     FB_VMODE_NONINTERLACED
0114 };
0115 #endif /* CONFIG_PPC_PMAC */
0116 
0117 /* default modedb mode */
0118 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
0119 static const struct fb_videomode defaultmode = {
0120     .refresh =  60,
0121     .xres =     640,
0122     .yres =     480,
0123     .pixclock = 39722,
0124     .left_margin =  48,
0125     .right_margin = 16,
0126     .upper_margin = 33,
0127     .lower_margin = 10,
0128     .hsync_len =    96,
0129     .vsync_len =    2,
0130     .sync =     0,
0131     .vmode =    FB_VMODE_NONINTERLACED
0132 };
0133 
0134 /* Chip generations */
0135 enum {
0136     rage_128,
0137     rage_128_pci,
0138     rage_128_pro,
0139     rage_128_pro_pci,
0140     rage_M3,
0141     rage_M3_pci,
0142     rage_M4,
0143     rage_128_ultra,
0144 };
0145 
0146 /* Must match above enum */
0147 static char * const r128_family[] = {
0148     "AGP",
0149     "PCI",
0150     "PRO AGP",
0151     "PRO PCI",
0152     "M3 AGP",
0153     "M3 PCI",
0154     "M4 AGP",
0155     "Ultra AGP",
0156 };
0157 
0158 /*
0159  * PCI driver prototypes
0160  */
0161 static int aty128_probe(struct pci_dev *pdev,
0162                                const struct pci_device_id *ent);
0163 static void aty128_remove(struct pci_dev *pdev);
0164 static int aty128_pci_suspend_late(struct device *dev, pm_message_t state);
0165 static int __maybe_unused aty128_pci_suspend(struct device *dev);
0166 static int __maybe_unused aty128_pci_hibernate(struct device *dev);
0167 static int __maybe_unused aty128_pci_freeze(struct device *dev);
0168 static int __maybe_unused aty128_pci_resume(struct device *dev);
0169 static int aty128_do_resume(struct pci_dev *pdev);
0170 
0171 static const struct dev_pm_ops aty128_pci_pm_ops = {
0172     .suspend    = aty128_pci_suspend,
0173     .resume     = aty128_pci_resume,
0174     .freeze     = aty128_pci_freeze,
0175     .thaw       = aty128_pci_resume,
0176     .poweroff   = aty128_pci_hibernate,
0177     .restore    = aty128_pci_resume,
0178 };
0179 
0180 /* supported Rage128 chipsets */
0181 static const struct pci_device_id aty128_pci_tbl[] = {
0182     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
0183       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
0184     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
0185       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
0186     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
0187       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
0188     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
0189       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
0190     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
0191       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0192     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
0193       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0194     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
0195       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0196     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
0197       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
0198     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
0199       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0200     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
0201       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0202     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
0203       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0204     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
0205       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0206     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
0207       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0208     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
0209       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0210     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
0211       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0212     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
0213       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0214     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
0215       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0216     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
0217       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0218     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
0219       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0220     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
0221       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
0222     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
0223       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0224     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
0225       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
0226     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
0227       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0228     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
0229       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0230     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
0231       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0232     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
0233       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0234     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
0235       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0236     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
0237       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
0238     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
0239       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
0240     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
0241       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0242     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
0243       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0244     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
0245       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
0246     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
0247       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0248     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
0249       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0250     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
0251       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
0252     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
0253       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0254     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
0255       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0256     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
0257       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0258     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
0259       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0260     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
0261       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0262     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
0263       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
0264     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
0265       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
0266     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
0267       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
0268     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
0269       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
0270     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
0271       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
0272     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
0273       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
0274     { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
0275       PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
0276     { 0, }
0277 };
0278 
0279 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
0280 
0281 static struct pci_driver aty128fb_driver = {
0282     .name       = "aty128fb",
0283     .id_table   = aty128_pci_tbl,
0284     .probe      = aty128_probe,
0285     .remove     = aty128_remove,
0286     .driver.pm  = &aty128_pci_pm_ops,
0287 };
0288 
0289 /* packed BIOS settings */
0290 #ifndef CONFIG_PPC
0291 typedef struct {
0292     u8 clock_chip_type;
0293     u8 struct_size;
0294     u8 accelerator_entry;
0295     u8 VGA_entry;
0296     u16 VGA_table_offset;
0297     u16 POST_table_offset;
0298     u16 XCLK;
0299     u16 MCLK;
0300     u8 num_PLL_blocks;
0301     u8 size_PLL_blocks;
0302     u16 PCLK_ref_freq;
0303     u16 PCLK_ref_divider;
0304     u32 PCLK_min_freq;
0305     u32 PCLK_max_freq;
0306     u16 MCLK_ref_freq;
0307     u16 MCLK_ref_divider;
0308     u32 MCLK_min_freq;
0309     u32 MCLK_max_freq;
0310     u16 XCLK_ref_freq;
0311     u16 XCLK_ref_divider;
0312     u32 XCLK_min_freq;
0313     u32 XCLK_max_freq;
0314 } __attribute__ ((packed)) PLL_BLOCK;
0315 #endif /* !CONFIG_PPC */
0316 
0317 /* onboard memory information */
0318 struct aty128_meminfo {
0319     u8 ML;
0320     u8 MB;
0321     u8 Trcd;
0322     u8 Trp;
0323     u8 Twr;
0324     u8 CL;
0325     u8 Tr2w;
0326     u8 LoopLatency;
0327     u8 DspOn;
0328     u8 Rloop;
0329     const char *name;
0330 };
0331 
0332 /* various memory configurations */
0333 static const struct aty128_meminfo sdr_128 = {
0334     .ML = 4,
0335     .MB = 4,
0336     .Trcd = 3,
0337     .Trp = 3,
0338     .Twr = 1,
0339     .CL = 3,
0340     .Tr2w = 1,
0341     .LoopLatency = 16,
0342     .DspOn = 30,
0343     .Rloop = 16,
0344     .name = "128-bit SDR SGRAM (1:1)",
0345 };
0346 
0347 static const struct aty128_meminfo sdr_sgram = {
0348     .ML = 4,
0349     .MB = 4,
0350     .Trcd = 1,
0351     .Trp = 2,
0352     .Twr = 1,
0353     .CL = 2,
0354     .Tr2w = 1,
0355     .LoopLatency = 16,
0356     .DspOn = 24,
0357     .Rloop = 16,
0358     .name = "64-bit SDR SGRAM (2:1)",
0359 };
0360 
0361 static const struct aty128_meminfo ddr_sgram = {
0362     .ML = 4,
0363     .MB = 4,
0364     .Trcd = 3,
0365     .Trp = 3,
0366     .Twr = 2,
0367     .CL = 3,
0368     .Tr2w = 1,
0369     .LoopLatency = 16,
0370     .DspOn = 31,
0371     .Rloop = 16,
0372     .name = "64-bit DDR SGRAM",
0373 };
0374 
0375 static const struct fb_fix_screeninfo aty128fb_fix = {
0376     .id     = "ATY Rage128",
0377     .type       = FB_TYPE_PACKED_PIXELS,
0378     .visual     = FB_VISUAL_PSEUDOCOLOR,
0379     .xpanstep   = 8,
0380     .ypanstep   = 1,
0381     .mmio_len   = 0x2000,
0382     .accel      = FB_ACCEL_ATI_RAGE128,
0383 };
0384 
0385 static char *mode_option = NULL;
0386 
0387 #ifdef CONFIG_PPC_PMAC
0388 static int default_vmode = VMODE_1024_768_60;
0389 static int default_cmode = CMODE_8;
0390 #endif
0391 
0392 static int default_crt_on = 0;
0393 static int default_lcd_on = 1;
0394 static bool mtrr = true;
0395 
0396 #ifdef CONFIG_FB_ATY128_BACKLIGHT
0397 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
0398 #endif
0399 
0400 /* PLL constants */
0401 struct aty128_constants {
0402     u32 ref_clk;
0403     u32 ppll_min;
0404     u32 ppll_max;
0405     u32 ref_divider;
0406     u32 xclk;
0407     u32 fifo_width;
0408     u32 fifo_depth;
0409 };
0410 
0411 struct aty128_crtc {
0412     u32 gen_cntl;
0413     u32 h_total, h_sync_strt_wid;
0414     u32 v_total, v_sync_strt_wid;
0415     u32 pitch;
0416     u32 offset, offset_cntl;
0417     u32 xoffset, yoffset;
0418     u32 vxres, vyres;
0419     u32 depth, bpp;
0420 };
0421 
0422 struct aty128_pll {
0423     u32 post_divider;
0424     u32 feedback_divider;
0425     u32 vclk;
0426 };
0427 
0428 struct aty128_ddafifo {
0429     u32 dda_config;
0430     u32 dda_on_off;
0431 };
0432 
0433 /* register values for a specific mode */
0434 struct aty128fb_par {
0435     struct aty128_crtc crtc;
0436     struct aty128_pll pll;
0437     struct aty128_ddafifo fifo_reg;
0438     u32 accel_flags;
0439     struct aty128_constants constants;  /* PLL and others      */
0440     void __iomem *regbase;              /* remapped mmio       */
0441     u32 vram_size;                      /* onboard video ram   */
0442     int chip_gen;
0443     const struct aty128_meminfo *mem;   /* onboard mem info    */
0444     int wc_cookie;
0445     int blitter_may_be_busy;
0446     int fifo_slots;                 /* free slots in FIFO (64 max) */
0447 
0448     int crt_on, lcd_on;
0449     struct pci_dev *pdev;
0450     struct fb_info *next;
0451     int asleep;
0452     int lock_blank;
0453 
0454     u8  red[32];        /* see aty128fb_setcolreg */
0455     u8  green[64];
0456     u8  blue[32];
0457     u32 pseudo_palette[16]; /* used for TRUECOLOR */
0458 };
0459 
0460 
0461 #define round_div(n, d) ((n+(d/2))/d)
0462 
0463 static int aty128fb_check_var(struct fb_var_screeninfo *var,
0464                   struct fb_info *info);
0465 static int aty128fb_set_par(struct fb_info *info);
0466 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
0467                   u_int transp, struct fb_info *info);
0468 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
0469                struct fb_info *fb);
0470 static int aty128fb_blank(int blank, struct fb_info *fb);
0471 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
0472 static int aty128fb_sync(struct fb_info *info);
0473 
0474     /*
0475      *  Internal routines
0476      */
0477 
0478 static int aty128_encode_var(struct fb_var_screeninfo *var,
0479                              const struct aty128fb_par *par);
0480 static int aty128_decode_var(struct fb_var_screeninfo *var,
0481                              struct aty128fb_par *par);
0482 static void aty128_timings(struct aty128fb_par *par);
0483 static void aty128_init_engine(struct aty128fb_par *par);
0484 static void aty128_reset_engine(const struct aty128fb_par *par);
0485 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
0486 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
0487 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
0488 static void wait_for_idle(struct aty128fb_par *par);
0489 static u32 depth_to_dst(u32 depth);
0490 
0491 #ifdef CONFIG_FB_ATY128_BACKLIGHT
0492 static void aty128_bl_set_power(struct fb_info *info, int power);
0493 #endif
0494 
0495 #define BIOS_IN8(v)     (readb(bios + (v)))
0496 #define BIOS_IN16(v)    (readb(bios + (v)) | \
0497               (readb(bios + (v) + 1) << 8))
0498 #define BIOS_IN32(v)    (readb(bios + (v)) | \
0499               (readb(bios + (v) + 1) << 8) | \
0500               (readb(bios + (v) + 2) << 16) | \
0501               (readb(bios + (v) + 3) << 24))
0502 
0503 
0504 static const struct fb_ops aty128fb_ops = {
0505     .owner      = THIS_MODULE,
0506     .fb_check_var   = aty128fb_check_var,
0507     .fb_set_par = aty128fb_set_par,
0508     .fb_setcolreg   = aty128fb_setcolreg,
0509     .fb_pan_display = aty128fb_pan_display,
0510     .fb_blank   = aty128fb_blank,
0511     .fb_ioctl   = aty128fb_ioctl,
0512     .fb_sync    = aty128fb_sync,
0513     .fb_fillrect    = cfb_fillrect,
0514     .fb_copyarea    = cfb_copyarea,
0515     .fb_imageblit   = cfb_imageblit,
0516 };
0517 
0518     /*
0519      * Functions to read from/write to the mmio registers
0520      *  - endian conversions may possibly be avoided by
0521      *    using the other register aperture. TODO.
0522      */
0523 static inline u32 _aty_ld_le32(volatile unsigned int regindex, 
0524                    const struct aty128fb_par *par)
0525 {
0526     return readl (par->regbase + regindex);
0527 }
0528 
0529 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 
0530                 const struct aty128fb_par *par)
0531 {
0532     writel (val, par->regbase + regindex);
0533 }
0534 
0535 static inline u8 _aty_ld_8(unsigned int regindex,
0536                const struct aty128fb_par *par)
0537 {
0538     return readb (par->regbase + regindex);
0539 }
0540 
0541 static inline void _aty_st_8(unsigned int regindex, u8 val,
0542                  const struct aty128fb_par *par)
0543 {
0544     writeb (val, par->regbase + regindex);
0545 }
0546 
0547 #define aty_ld_le32(regindex)       _aty_ld_le32(regindex, par)
0548 #define aty_st_le32(regindex, val)  _aty_st_le32(regindex, val, par)
0549 #define aty_ld_8(regindex)      _aty_ld_8(regindex, par)
0550 #define aty_st_8(regindex, val)     _aty_st_8(regindex, val, par)
0551 
0552     /*
0553      * Functions to read from/write to the pll registers
0554      */
0555 
0556 #define aty_ld_pll(pll_index)       _aty_ld_pll(pll_index, par)
0557 #define aty_st_pll(pll_index, val)  _aty_st_pll(pll_index, val, par)
0558 
0559 
0560 static u32 _aty_ld_pll(unsigned int pll_index,
0561                const struct aty128fb_par *par)
0562 {       
0563     aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
0564     return aty_ld_le32(CLOCK_CNTL_DATA);
0565 }
0566 
0567     
0568 static void _aty_st_pll(unsigned int pll_index, u32 val,
0569             const struct aty128fb_par *par)
0570 {
0571     aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
0572     aty_st_le32(CLOCK_CNTL_DATA, val);
0573 }
0574 
0575 
0576 /* return true when the PLL has completed an atomic update */
0577 static int aty_pll_readupdate(const struct aty128fb_par *par)
0578 {
0579     return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
0580 }
0581 
0582 
0583 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
0584 {
0585     unsigned long timeout = jiffies + HZ/100; // should be more than enough
0586     int reset = 1;
0587 
0588     while (time_before(jiffies, timeout))
0589         if (aty_pll_readupdate(par)) {
0590             reset = 0;
0591             break;
0592         }
0593 
0594     if (reset)  /* reset engine?? */
0595         printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
0596 }
0597 
0598 
0599 /* tell PLL to update */
0600 static void aty_pll_writeupdate(const struct aty128fb_par *par)
0601 {
0602     aty_pll_wait_readupdate(par);
0603 
0604     aty_st_pll(PPLL_REF_DIV,
0605            aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
0606 }
0607 
0608 
0609 /* write to the scratch register to test r/w functionality */
0610 static int register_test(const struct aty128fb_par *par)
0611 {
0612     u32 val;
0613     int flag = 0;
0614 
0615     val = aty_ld_le32(BIOS_0_SCRATCH);
0616 
0617     aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
0618     if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
0619         aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
0620 
0621         if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
0622             flag = 1; 
0623     }
0624 
0625     aty_st_le32(BIOS_0_SCRATCH, val);   // restore value
0626     return flag;
0627 }
0628 
0629 
0630 /*
0631  * Accelerator engine functions
0632  */
0633 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
0634 {
0635     int i;
0636 
0637     for (;;) {
0638         for (i = 0; i < 2000000; i++) {
0639             par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
0640             if (par->fifo_slots >= entries)
0641                 return;
0642         }
0643         aty128_reset_engine(par);
0644     }
0645 }
0646 
0647 
0648 static void wait_for_idle(struct aty128fb_par *par)
0649 {
0650     int i;
0651 
0652     do_wait_for_fifo(64, par);
0653 
0654     for (;;) {
0655         for (i = 0; i < 2000000; i++) {
0656             if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
0657                 aty128_flush_pixel_cache(par);
0658                 par->blitter_may_be_busy = 0;
0659                 return;
0660             }
0661         }
0662         aty128_reset_engine(par);
0663     }
0664 }
0665 
0666 
0667 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
0668 {
0669     if (par->fifo_slots < entries)
0670         do_wait_for_fifo(64, par);
0671     par->fifo_slots -= entries;
0672 }
0673 
0674 
0675 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
0676 {
0677     int i;
0678     u32 tmp;
0679 
0680     tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
0681     tmp &= ~(0x00ff);
0682     tmp |= 0x00ff;
0683     aty_st_le32(PC_NGUI_CTLSTAT, tmp);
0684 
0685     for (i = 0; i < 2000000; i++)
0686         if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
0687             break;
0688 }
0689 
0690 
0691 static void aty128_reset_engine(const struct aty128fb_par *par)
0692 {
0693     u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
0694 
0695     aty128_flush_pixel_cache(par);
0696 
0697     clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
0698     mclk_cntl = aty_ld_pll(MCLK_CNTL);
0699 
0700     aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
0701 
0702     gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
0703     aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
0704     aty_ld_le32(GEN_RESET_CNTL);
0705     aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
0706     aty_ld_le32(GEN_RESET_CNTL);
0707 
0708     aty_st_pll(MCLK_CNTL, mclk_cntl);
0709     aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
0710     aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
0711 
0712     /* use old pio mode */
0713     aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
0714 
0715     DBG("engine reset");
0716 }
0717 
0718 
0719 static void aty128_init_engine(struct aty128fb_par *par)
0720 {
0721     u32 pitch_value;
0722 
0723     wait_for_idle(par);
0724 
0725     /* 3D scaler not spoken here */
0726     wait_for_fifo(1, par);
0727     aty_st_le32(SCALE_3D_CNTL, 0x00000000);
0728 
0729     aty128_reset_engine(par);
0730 
0731     pitch_value = par->crtc.pitch;
0732     if (par->crtc.bpp == 24) {
0733         pitch_value = pitch_value * 3;
0734     }
0735 
0736     wait_for_fifo(4, par);
0737     /* setup engine offset registers */
0738     aty_st_le32(DEFAULT_OFFSET, 0x00000000);
0739 
0740     /* setup engine pitch registers */
0741     aty_st_le32(DEFAULT_PITCH, pitch_value);
0742 
0743     /* set the default scissor register to max dimensions */
0744     aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
0745 
0746     /* set the drawing controls registers */
0747     aty_st_le32(DP_GUI_MASTER_CNTL,
0748             GMC_SRC_PITCH_OFFSET_DEFAULT        |
0749             GMC_DST_PITCH_OFFSET_DEFAULT        |
0750             GMC_SRC_CLIP_DEFAULT            |
0751             GMC_DST_CLIP_DEFAULT            |
0752             GMC_BRUSH_SOLIDCOLOR            |
0753             (depth_to_dst(par->crtc.depth) << 8)    |
0754             GMC_SRC_DSTCOLOR            |
0755             GMC_BYTE_ORDER_MSB_TO_LSB       |
0756             GMC_DP_CONVERSION_TEMP_6500     |
0757             ROP3_PATCOPY                |
0758             GMC_DP_SRC_RECT             |
0759             GMC_3D_FCN_EN_CLR           |
0760             GMC_DST_CLR_CMP_FCN_CLEAR       |
0761             GMC_AUX_CLIP_CLEAR          |
0762             GMC_WRITE_MASK_SET);
0763 
0764     wait_for_fifo(8, par);
0765     /* clear the line drawing registers */
0766     aty_st_le32(DST_BRES_ERR, 0);
0767     aty_st_le32(DST_BRES_INC, 0);
0768     aty_st_le32(DST_BRES_DEC, 0);
0769 
0770     /* set brush color registers */
0771     aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
0772     aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
0773 
0774     /* set source color registers */
0775     aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF);   /* white */
0776     aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000);   /* black */
0777 
0778     /* default write mask */
0779     aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
0780 
0781     /* Wait for all the writes to be completed before returning */
0782     wait_for_idle(par);
0783 }
0784 
0785 
0786 /* convert depth values to their register representation */
0787 static u32 depth_to_dst(u32 depth)
0788 {
0789     if (depth <= 8)
0790         return DST_8BPP;
0791     else if (depth <= 15)
0792         return DST_15BPP;
0793     else if (depth == 16)
0794         return DST_16BPP;
0795     else if (depth <= 24)
0796         return DST_24BPP;
0797     else if (depth <= 32)
0798         return DST_32BPP;
0799 
0800     return -EINVAL;
0801 }
0802 
0803 /*
0804  * PLL informations retreival
0805  */
0806 
0807 
0808 #ifndef __sparc__
0809 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
0810                     struct pci_dev *dev)
0811 {
0812     u16 dptr;
0813     u8 rom_type;
0814     void __iomem *bios;
0815     size_t rom_size;
0816 
0817         /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
0818         unsigned int temp;
0819     temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
0820     temp &= 0x00ffffffu;
0821     temp |= 0x04 << 24;
0822     aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
0823     temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
0824 
0825     bios = pci_map_rom(dev, &rom_size);
0826 
0827     if (!bios) {
0828         printk(KERN_ERR "aty128fb: ROM failed to map\n");
0829         return NULL;
0830     }
0831 
0832     /* Very simple test to make sure it appeared */
0833     if (BIOS_IN16(0) != 0xaa55) {
0834         printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
0835             " be 0xaa55\n", BIOS_IN16(0));
0836         goto failed;
0837     }
0838 
0839     /* Look for the PCI data to check the ROM type */
0840     dptr = BIOS_IN16(0x18);
0841 
0842     /* Check the PCI data signature. If it's wrong, we still assume a normal
0843      * x86 ROM for now, until I've verified this works everywhere.
0844      * The goal here is more to phase out Open Firmware images.
0845      *
0846      * Currently, we only look at the first PCI data, we could iteratre and
0847      * deal with them all, and we should use fb_bios_start relative to start
0848      * of image and not relative start of ROM, but so far, I never found a
0849      * dual-image ATI card.
0850      *
0851      * typedef struct {
0852      *  u32 signature;  + 0x00
0853      *  u16 vendor;     + 0x04
0854      *  u16 device;     + 0x06
0855      *  u16 reserved_1; + 0x08
0856      *  u16 dlen;       + 0x0a
0857      *  u8  drevision;  + 0x0c
0858      *  u8  class_hi;   + 0x0d
0859      *  u16 class_lo;   + 0x0e
0860      *  u16 ilen;       + 0x10
0861      *  u16 irevision;  + 0x12
0862      *  u8  type;       + 0x14
0863      *  u8  indicator;  + 0x15
0864      *  u16 reserved_2; + 0x16
0865      * } pci_data_t;
0866      */
0867     if (BIOS_IN32(dptr) !=  (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
0868         printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
0869                BIOS_IN32(dptr));
0870         goto anyway;
0871     }
0872     rom_type = BIOS_IN8(dptr + 0x14);
0873     switch(rom_type) {
0874     case 0:
0875         printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
0876         break;
0877     case 1:
0878         printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
0879         goto failed;
0880     case 2:
0881         printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
0882         goto failed;
0883     default:
0884         printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
0885                rom_type);
0886         goto failed;
0887     }
0888  anyway:
0889     return bios;
0890 
0891  failed:
0892     pci_unmap_rom(dev, bios);
0893     return NULL;
0894 }
0895 
0896 static void aty128_get_pllinfo(struct aty128fb_par *par,
0897                    unsigned char __iomem *bios)
0898 {
0899     unsigned int bios_hdr;
0900     unsigned int bios_pll;
0901 
0902     bios_hdr = BIOS_IN16(0x48);
0903     bios_pll = BIOS_IN16(bios_hdr + 0x30);
0904     
0905     par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
0906     par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
0907     par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
0908     par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
0909     par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
0910 
0911     DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
0912             par->constants.ppll_max, par->constants.ppll_min,
0913             par->constants.xclk, par->constants.ref_divider,
0914             par->constants.ref_clk);
0915 
0916 }           
0917 
0918 #ifdef CONFIG_X86
0919 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
0920 {
0921     /* I simplified this code as we used to miss the signatures in
0922      * a lot of case. It's now closer to XFree, we just don't check
0923      * for signatures at all... Something better will have to be done
0924      * if we end up having conflicts
0925      */
0926         u32  segstart;
0927         unsigned char __iomem *rom_base = NULL;
0928                                                 
0929         for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
0930                 rom_base = ioremap(segstart, 0x10000);
0931         if (rom_base == NULL)
0932             return NULL;
0933         if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
0934                     break;
0935                 iounmap(rom_base);
0936         rom_base = NULL;
0937         }
0938     return rom_base;
0939 }
0940 #endif
0941 #endif /* ndef(__sparc__) */
0942 
0943 /* fill in known card constants if pll_block is not available */
0944 static void aty128_timings(struct aty128fb_par *par)
0945 {
0946 #ifdef CONFIG_PPC
0947     /* instead of a table lookup, assume OF has properly
0948      * setup the PLL registers and use their values
0949      * to set the XCLK values and reference divider values */
0950 
0951     u32 x_mpll_ref_fb_div;
0952     u32 xclk_cntl;
0953     u32 Nx, M;
0954     static const unsigned int PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
0955 #endif
0956 
0957     if (!par->constants.ref_clk)
0958         par->constants.ref_clk = 2950;
0959 
0960 #ifdef CONFIG_PPC
0961     x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
0962     xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
0963     Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
0964     M  = x_mpll_ref_fb_div & 0x0000ff;
0965 
0966     par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
0967                     (M * PostDivSet[xclk_cntl]));
0968 
0969     par->constants.ref_divider =
0970         aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
0971 #endif
0972 
0973     if (!par->constants.ref_divider) {
0974         par->constants.ref_divider = 0x3b;
0975 
0976         aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
0977         aty_pll_writeupdate(par);
0978     }
0979     aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
0980     aty_pll_writeupdate(par);
0981 
0982     /* from documentation */
0983     if (!par->constants.ppll_min)
0984         par->constants.ppll_min = 12500;
0985     if (!par->constants.ppll_max)
0986         par->constants.ppll_max = 25000;    /* 23000 on some cards? */
0987     if (!par->constants.xclk)
0988         par->constants.xclk = 0x1d4d;        /* same as mclk */
0989 
0990     par->constants.fifo_width = 128;
0991     par->constants.fifo_depth = 32;
0992 
0993     switch (aty_ld_le32(MEM_CNTL) & 0x3) {
0994     case 0:
0995         par->mem = &sdr_128;
0996         break;
0997     case 1:
0998         par->mem = &sdr_sgram;
0999         break;
1000     case 2:
1001         par->mem = &ddr_sgram;
1002         break;
1003     default:
1004         par->mem = &sdr_sgram;
1005     }
1006 }
1007 
1008 
1009 
1010 /*
1011  * CRTC programming
1012  */
1013 
1014 /* Program the CRTC registers */
1015 static void aty128_set_crtc(const struct aty128_crtc *crtc,
1016                 const struct aty128fb_par *par)
1017 {
1018     aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
1019     aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
1020     aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
1021     aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
1022     aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
1023     aty_st_le32(CRTC_PITCH, crtc->pitch);
1024     aty_st_le32(CRTC_OFFSET, crtc->offset);
1025     aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1026     /* Disable ATOMIC updating.  Is this the right place? */
1027     aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1028 }
1029 
1030 
1031 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1032                   struct aty128_crtc *crtc,
1033                   const struct aty128fb_par *par)
1034 {
1035     u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1036     u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1037     u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1038     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1039     u32 depth, bytpp;
1040     u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1041 
1042     /* input */
1043     xres = var->xres;
1044     yres = var->yres;
1045     vxres   = var->xres_virtual;
1046     vyres   = var->yres_virtual;
1047     xoffset = var->xoffset;
1048     yoffset = var->yoffset;
1049     bpp   = var->bits_per_pixel;
1050     left  = var->left_margin;
1051     right = var->right_margin;
1052     upper = var->upper_margin;
1053     lower = var->lower_margin;
1054     hslen = var->hsync_len;
1055     vslen = var->vsync_len;
1056     sync  = var->sync;
1057     vmode = var->vmode;
1058 
1059     if (bpp != 16)
1060         depth = bpp;
1061     else
1062         depth = (var->green.length == 6) ? 16 : 15;
1063 
1064     /* check for mode eligibility
1065      * accept only non interlaced modes */
1066     if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1067         return -EINVAL;
1068 
1069     /* convert (and round up) and validate */
1070     xres = (xres + 7) & ~7;
1071     xoffset = (xoffset + 7) & ~7;
1072 
1073     if (vxres < xres + xoffset)
1074         vxres = xres + xoffset;
1075 
1076     if (vyres < yres + yoffset)
1077         vyres = yres + yoffset;
1078 
1079     /* convert depth into ATI register depth */
1080     dst = depth_to_dst(depth);
1081 
1082     if (dst == -EINVAL) {
1083         printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1084         return -EINVAL;
1085     }
1086 
1087     /* convert register depth to bytes per pixel */
1088     bytpp = mode_bytpp[dst];
1089 
1090     /* make sure there is enough video ram for the mode */
1091     if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1092         printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1093         return -EINVAL;
1094     }
1095 
1096     h_disp = (xres >> 3) - 1;
1097     h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1098 
1099     v_disp = yres - 1;
1100     v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1101 
1102     /* check to make sure h_total and v_total are in range */
1103     if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1104         printk(KERN_ERR "aty128fb: invalid width ranges\n");
1105         return -EINVAL;
1106     }
1107 
1108     h_sync_wid = (hslen + 7) >> 3;
1109     if (h_sync_wid == 0)
1110         h_sync_wid = 1;
1111     else if (h_sync_wid > 0x3f)        /* 0x3f = max hwidth */
1112         h_sync_wid = 0x3f;
1113 
1114     h_sync_strt = (h_disp << 3) + right;
1115 
1116     v_sync_wid = vslen;
1117     if (v_sync_wid == 0)
1118         v_sync_wid = 1;
1119     else if (v_sync_wid > 0x1f)        /* 0x1f = max vwidth */
1120         v_sync_wid = 0x1f;
1121     
1122     v_sync_strt = v_disp + lower;
1123 
1124     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1125     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1126     
1127     c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1128 
1129     crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1130 
1131     crtc->h_total = h_total | (h_disp << 16);
1132     crtc->v_total = v_total | (v_disp << 16);
1133 
1134     crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1135             (h_sync_pol << 23);
1136     crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1137                 (v_sync_pol << 23);
1138 
1139     crtc->pitch = vxres >> 3;
1140 
1141     crtc->offset = 0;
1142 
1143     if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1144         crtc->offset_cntl = 0x00010000;
1145     else
1146         crtc->offset_cntl = 0;
1147 
1148     crtc->vxres = vxres;
1149     crtc->vyres = vyres;
1150     crtc->xoffset = xoffset;
1151     crtc->yoffset = yoffset;
1152     crtc->depth = depth;
1153     crtc->bpp = bpp;
1154 
1155     return 0;
1156 }
1157 
1158 
1159 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1160 {
1161 
1162     /* fill in pixel info */
1163     var->red.msb_right = 0;
1164     var->green.msb_right = 0;
1165     var->blue.offset = 0;
1166     var->blue.msb_right = 0;
1167     var->transp.offset = 0;
1168     var->transp.length = 0;
1169     var->transp.msb_right = 0;
1170     switch (pix_width) {
1171     case CRTC_PIX_WIDTH_8BPP:
1172         var->bits_per_pixel = 8;
1173         var->red.offset = 0;
1174         var->red.length = 8;
1175         var->green.offset = 0;
1176         var->green.length = 8;
1177         var->blue.length = 8;
1178         break;
1179     case CRTC_PIX_WIDTH_15BPP:
1180         var->bits_per_pixel = 16;
1181         var->red.offset = 10;
1182         var->red.length = 5;
1183         var->green.offset = 5;
1184         var->green.length = 5;
1185         var->blue.length = 5;
1186         break;
1187     case CRTC_PIX_WIDTH_16BPP:
1188         var->bits_per_pixel = 16;
1189         var->red.offset = 11;
1190         var->red.length = 5;
1191         var->green.offset = 5;
1192         var->green.length = 6;
1193         var->blue.length = 5;
1194         break;
1195     case CRTC_PIX_WIDTH_24BPP:
1196         var->bits_per_pixel = 24;
1197         var->red.offset = 16;
1198         var->red.length = 8;
1199         var->green.offset = 8;
1200         var->green.length = 8;
1201         var->blue.length = 8;
1202         break;
1203     case CRTC_PIX_WIDTH_32BPP:
1204         var->bits_per_pixel = 32;
1205         var->red.offset = 16;
1206         var->red.length = 8;
1207         var->green.offset = 8;
1208         var->green.length = 8;
1209         var->blue.length = 8;
1210         var->transp.offset = 24;
1211         var->transp.length = 8;
1212         break;
1213     default:
1214         printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1215         return -EINVAL;
1216     }
1217 
1218     return 0;
1219 }
1220 
1221 
1222 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1223                   struct fb_var_screeninfo *var)
1224 {
1225     u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1226     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1227     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1228     u32 pix_width;
1229 
1230     /* fun with masking */
1231     h_total     = crtc->h_total & 0x1ff;
1232     h_disp      = (crtc->h_total >> 16) & 0xff;
1233     h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1234     h_sync_dly  = crtc->h_sync_strt_wid & 0x7;
1235     h_sync_wid  = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1236     h_sync_pol  = (crtc->h_sync_strt_wid >> 23) & 0x1;
1237     v_total     = crtc->v_total & 0x7ff;
1238     v_disp      = (crtc->v_total >> 16) & 0x7ff;
1239     v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1240     v_sync_wid  = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1241     v_sync_pol  = (crtc->v_sync_strt_wid >> 23) & 0x1;
1242     c_sync      = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1243     pix_width   = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1244 
1245     /* do conversions */
1246     xres  = (h_disp + 1) << 3;
1247     yres  = v_disp + 1;
1248     left  = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1249     right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1250     hslen = h_sync_wid << 3;
1251     upper = v_total - v_sync_strt - v_sync_wid;
1252     lower = v_sync_strt - v_disp;
1253     vslen = v_sync_wid;
1254     sync  = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1255         (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1256         (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1257 
1258     aty128_pix_width_to_var(pix_width, var);
1259 
1260     var->xres = xres;
1261     var->yres = yres;
1262     var->xres_virtual = crtc->vxres;
1263     var->yres_virtual = crtc->vyres;
1264     var->xoffset = crtc->xoffset;
1265     var->yoffset = crtc->yoffset;
1266     var->left_margin  = left;
1267     var->right_margin = right;
1268     var->upper_margin = upper;
1269     var->lower_margin = lower;
1270     var->hsync_len = hslen;
1271     var->vsync_len = vslen;
1272     var->sync  = sync;
1273     var->vmode = FB_VMODE_NONINTERLACED;
1274 
1275     return 0;
1276 }
1277 
1278 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1279 {
1280     if (on) {
1281         aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1282                 CRT_CRTC_ON);
1283         aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1284                 DAC_PALETTE2_SNOOP_EN));
1285     } else
1286         aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1287                 ~CRT_CRTC_ON);
1288 }
1289 
1290 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1291 {
1292     u32 reg;
1293 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1294     struct fb_info *info = pci_get_drvdata(par->pdev);
1295 #endif
1296 
1297     if (on) {
1298         reg = aty_ld_le32(LVDS_GEN_CNTL);
1299         reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1300         reg &= ~LVDS_DISPLAY_DIS;
1301         aty_st_le32(LVDS_GEN_CNTL, reg);
1302 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1303         aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1304 #endif  
1305     } else {
1306 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1307         aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1308 #endif  
1309         reg = aty_ld_le32(LVDS_GEN_CNTL);
1310         reg |= LVDS_DISPLAY_DIS;
1311         aty_st_le32(LVDS_GEN_CNTL, reg);
1312         mdelay(100);
1313         reg &= ~(LVDS_ON /*| LVDS_EN*/);
1314         aty_st_le32(LVDS_GEN_CNTL, reg);
1315     }
1316 }
1317 
1318 static void aty128_set_pll(struct aty128_pll *pll,
1319                const struct aty128fb_par *par)
1320 {
1321     u32 div3;
1322 
1323     /* register values for post dividers */
1324     static const unsigned char post_conv[] = {
1325         2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7
1326     };
1327 
1328     /* select PPLL_DIV_3 */
1329     aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1330 
1331     /* reset PLL */
1332     aty_st_pll(PPLL_CNTL,
1333            aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1334 
1335     /* write the reference divider */
1336     aty_pll_wait_readupdate(par);
1337     aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1338     aty_pll_writeupdate(par);
1339 
1340     div3 = aty_ld_pll(PPLL_DIV_3);
1341     div3 &= ~PPLL_FB3_DIV_MASK;
1342     div3 |= pll->feedback_divider;
1343     div3 &= ~PPLL_POST3_DIV_MASK;
1344     div3 |= post_conv[pll->post_divider] << 16;
1345 
1346     /* write feedback and post dividers */
1347     aty_pll_wait_readupdate(par);
1348     aty_st_pll(PPLL_DIV_3, div3);
1349     aty_pll_writeupdate(par);
1350 
1351     aty_pll_wait_readupdate(par);
1352     aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1353     aty_pll_writeupdate(par);
1354 
1355     /* clear the reset, just in case */
1356     aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1357 }
1358 
1359 
1360 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1361                  const struct aty128fb_par *par)
1362 {
1363     const struct aty128_constants c = par->constants;
1364     static const unsigned char post_dividers[] = { 1, 2, 4, 8, 3, 6, 12 };
1365     u32 output_freq;
1366     u32 vclk;        /* in .01 MHz */
1367     int i = 0;
1368     u32 n, d;
1369 
1370     vclk = 100000000 / period_in_ps;    /* convert units to 10 kHz */
1371 
1372     /* adjust pixel clock if necessary */
1373     if (vclk > c.ppll_max)
1374         vclk = c.ppll_max;
1375     if (vclk * 12 < c.ppll_min)
1376         vclk = c.ppll_min/12;
1377 
1378     /* now, find an acceptable divider */
1379     for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1380         output_freq = post_dividers[i] * vclk;
1381         if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1382             pll->post_divider = post_dividers[i];
1383             break;
1384         }
1385     }
1386 
1387     if (i == ARRAY_SIZE(post_dividers))
1388         return -EINVAL;
1389 
1390     /* calculate feedback divider */
1391     n = c.ref_divider * output_freq;
1392     d = c.ref_clk;
1393 
1394     pll->feedback_divider = round_div(n, d);
1395     pll->vclk = vclk;
1396 
1397     DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1398         "vclk_per: %d\n", pll->post_divider,
1399         pll->feedback_divider, vclk, output_freq,
1400         c.ref_divider, period_in_ps);
1401 
1402     return 0;
1403 }
1404 
1405 
1406 static int aty128_pll_to_var(const struct aty128_pll *pll,
1407                  struct fb_var_screeninfo *var)
1408 {
1409     var->pixclock = 100000000 / pll->vclk;
1410 
1411     return 0;
1412 }
1413 
1414 
1415 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1416                 const struct aty128fb_par *par)
1417 {
1418     aty_st_le32(DDA_CONFIG, dsp->dda_config);
1419     aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1420 }
1421 
1422 
1423 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1424               const struct aty128_pll *pll,
1425               u32 depth,
1426               const struct aty128fb_par *par)
1427 {
1428     const struct aty128_meminfo *m = par->mem;
1429     u32 xclk = par->constants.xclk;
1430     u32 fifo_width = par->constants.fifo_width;
1431     u32 fifo_depth = par->constants.fifo_depth;
1432     s32 x, b, p, ron, roff;
1433     u32 n, d, bpp;
1434 
1435     /* round up to multiple of 8 */
1436     bpp = (depth+7) & ~7;
1437 
1438     n = xclk * fifo_width;
1439     d = pll->vclk * bpp;
1440     x = round_div(n, d);
1441 
1442     ron = 4 * m->MB +
1443         3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1444         2 * m->Trp +
1445         m->Twr +
1446         m->CL +
1447         m->Tr2w +
1448         x;
1449 
1450     DBG("x %x\n", x);
1451 
1452     b = 0;
1453     while (x) {
1454         x >>= 1;
1455         b++;
1456     }
1457     p = b + 1;
1458 
1459     ron <<= (11 - p);
1460 
1461     n <<= (11 - p);
1462     x = round_div(n, d);
1463     roff = x * (fifo_depth - 4);
1464 
1465     if ((ron + m->Rloop) >= roff) {
1466         printk(KERN_ERR "aty128fb: Mode out of range!\n");
1467         return -EINVAL;
1468     }
1469 
1470     DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1471         p, m->Rloop, x, ron, roff);
1472 
1473     dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1474     dsp->dda_on_off = ron << 16 | roff;
1475 
1476     return 0;
1477 }
1478 
1479 
1480 /*
1481  * This actually sets the video mode.
1482  */
1483 static int aty128fb_set_par(struct fb_info *info)
1484 { 
1485     struct aty128fb_par *par = info->par;
1486     u32 config;
1487     int err;
1488 
1489     if ((err = aty128_decode_var(&info->var, par)) != 0)
1490         return err;
1491 
1492     if (par->blitter_may_be_busy)
1493         wait_for_idle(par);
1494 
1495     /* clear all registers that may interfere with mode setting */
1496     aty_st_le32(OVR_CLR, 0);
1497     aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1498     aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1499     aty_st_le32(OV0_SCALE_CNTL, 0);
1500     aty_st_le32(MPP_TB_CONFIG, 0);
1501     aty_st_le32(MPP_GP_CONFIG, 0);
1502     aty_st_le32(SUBPIC_CNTL, 0);
1503     aty_st_le32(VIPH_CONTROL, 0);
1504     aty_st_le32(I2C_CNTL_1, 0);         /* turn off i2c */
1505     aty_st_le32(GEN_INT_CNTL, 0);   /* turn off interrupts */
1506     aty_st_le32(CAP0_TRIG_CNTL, 0);
1507     aty_st_le32(CAP1_TRIG_CNTL, 0);
1508 
1509     aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1510 
1511     aty128_set_crtc(&par->crtc, par);
1512     aty128_set_pll(&par->pll, par);
1513     aty128_set_fifo(&par->fifo_reg, par);
1514 
1515     config = aty_ld_le32(CNFG_CNTL) & ~3;
1516 
1517 #if defined(__BIG_ENDIAN)
1518     if (par->crtc.bpp == 32)
1519         config |= 2;    /* make aperture do 32 bit swapping */
1520     else if (par->crtc.bpp == 16)
1521         config |= 1;    /* make aperture do 16 bit swapping */
1522 #endif
1523 
1524     aty_st_le32(CNFG_CNTL, config);
1525     aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1526 
1527     info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1528     info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1529         : FB_VISUAL_DIRECTCOLOR;
1530 
1531     if (par->chip_gen == rage_M3) {
1532         aty128_set_crt_enable(par, par->crt_on);
1533         aty128_set_lcd_enable(par, par->lcd_on);
1534     }
1535     if (par->accel_flags & FB_ACCELF_TEXT)
1536         aty128_init_engine(par);
1537 
1538 #ifdef CONFIG_BOOTX_TEXT
1539     btext_update_display(info->fix.smem_start,
1540                  (((par->crtc.h_total>>16) & 0xff)+1)*8,
1541                  ((par->crtc.v_total>>16) & 0x7ff)+1,
1542                  par->crtc.bpp,
1543                  par->crtc.vxres*par->crtc.bpp/8);
1544 #endif /* CONFIG_BOOTX_TEXT */
1545 
1546     return 0;
1547 }
1548 
1549 /*
1550  *  encode/decode the User Defined Part of the Display
1551  */
1552 
1553 static int aty128_decode_var(struct fb_var_screeninfo *var,
1554                  struct aty128fb_par *par)
1555 {
1556     int err;
1557     struct aty128_crtc crtc;
1558     struct aty128_pll pll;
1559     struct aty128_ddafifo fifo_reg;
1560 
1561     if ((err = aty128_var_to_crtc(var, &crtc, par)))
1562         return err;
1563 
1564     if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1565         return err;
1566 
1567     if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1568         return err;
1569 
1570     par->crtc = crtc;
1571     par->pll = pll;
1572     par->fifo_reg = fifo_reg;
1573     par->accel_flags = var->accel_flags;
1574 
1575     return 0;
1576 }
1577 
1578 
1579 static int aty128_encode_var(struct fb_var_screeninfo *var,
1580                  const struct aty128fb_par *par)
1581 {
1582     int err;
1583 
1584     if ((err = aty128_crtc_to_var(&par->crtc, var)))
1585         return err;
1586 
1587     if ((err = aty128_pll_to_var(&par->pll, var)))
1588         return err;
1589 
1590     var->nonstd = 0;
1591     var->activate = 0;
1592 
1593     var->height = -1;
1594     var->width = -1;
1595     var->accel_flags = par->accel_flags;
1596 
1597     return 0;
1598 }           
1599 
1600 
1601 static int aty128fb_check_var(struct fb_var_screeninfo *var,
1602                   struct fb_info *info)
1603 {
1604     struct aty128fb_par par;
1605     int err;
1606 
1607     par = *(struct aty128fb_par *)info->par;
1608     if ((err = aty128_decode_var(var, &par)) != 0)
1609         return err;
1610     aty128_encode_var(var, &par);
1611     return 0;
1612 }
1613 
1614 
1615 /*
1616  *  Pan or Wrap the Display
1617  */
1618 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1619                 struct fb_info *fb)
1620 {
1621     struct aty128fb_par *par = fb->par;
1622     u32 xoffset, yoffset;
1623     u32 offset;
1624     u32 xres, yres;
1625 
1626     xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1627     yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1628 
1629     xoffset = (var->xoffset +7) & ~7;
1630     yoffset = var->yoffset;
1631 
1632     if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1633         return -EINVAL;
1634 
1635     par->crtc.xoffset = xoffset;
1636     par->crtc.yoffset = yoffset;
1637 
1638     offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1639                                       & ~7;
1640 
1641     if (par->crtc.bpp == 24)
1642         offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1643 
1644     aty_st_le32(CRTC_OFFSET, offset);
1645 
1646     return 0;
1647 }
1648 
1649 
1650 /*
1651  *  Helper function to store a single palette register
1652  */
1653 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1654               struct aty128fb_par *par)
1655 {
1656     if (par->chip_gen == rage_M3) {
1657         aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1658                 ~DAC_PALETTE_ACCESS_CNTL);
1659     }
1660 
1661     aty_st_8(PALETTE_INDEX, regno);
1662     aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1663 }
1664 
1665 static int aty128fb_sync(struct fb_info *info)
1666 {
1667     struct aty128fb_par *par = info->par;
1668 
1669     if (par->blitter_may_be_busy)
1670         wait_for_idle(par);
1671     return 0;
1672 }
1673 
1674 #ifndef MODULE
1675 static int aty128fb_setup(char *options)
1676 {
1677     char *this_opt;
1678 
1679     if (!options || !*options)
1680         return 0;
1681 
1682     while ((this_opt = strsep(&options, ",")) != NULL) {
1683         if (!strncmp(this_opt, "lcd:", 4)) {
1684             default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1685             continue;
1686         } else if (!strncmp(this_opt, "crt:", 4)) {
1687             default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1688             continue;
1689         } else if (!strncmp(this_opt, "backlight:", 10)) {
1690 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1691             backlight = simple_strtoul(this_opt+10, NULL, 0);
1692 #endif
1693             continue;
1694         }
1695         if(!strncmp(this_opt, "nomtrr", 6)) {
1696             mtrr = false;
1697             continue;
1698         }
1699 #ifdef CONFIG_PPC_PMAC
1700         /* vmode and cmode deprecated */
1701         if (!strncmp(this_opt, "vmode:", 6)) {
1702             unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1703             if (vmode > 0 && vmode <= VMODE_MAX)
1704                 default_vmode = vmode;
1705             continue;
1706         } else if (!strncmp(this_opt, "cmode:", 6)) {
1707             unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1708             switch (cmode) {
1709             case 0:
1710             case 8:
1711                 default_cmode = CMODE_8;
1712                 break;
1713             case 15:
1714             case 16:
1715                 default_cmode = CMODE_16;
1716                 break;
1717             case 24:
1718             case 32:
1719                 default_cmode = CMODE_32;
1720                 break;
1721             }
1722             continue;
1723         }
1724 #endif /* CONFIG_PPC_PMAC */
1725         mode_option = this_opt;
1726     }
1727     return 0;
1728 }
1729 #endif  /*  MODULE  */
1730 
1731 /* Backlight */
1732 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1733 #define MAX_LEVEL 0xFF
1734 
1735 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1736         int level)
1737 {
1738     struct fb_info *info = pci_get_drvdata(par->pdev);
1739     int atylevel;
1740 
1741     /* Get and convert the value */
1742     /* No locking of bl_curve since we read a single value */
1743     atylevel = MAX_LEVEL -
1744         (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1745 
1746     if (atylevel < 0)
1747         atylevel = 0;
1748     else if (atylevel > MAX_LEVEL)
1749         atylevel = MAX_LEVEL;
1750 
1751     return atylevel;
1752 }
1753 
1754 /* We turn off the LCD completely instead of just dimming the backlight.
1755  * This provides greater power saving and the display is useless without
1756  * backlight anyway
1757  */
1758 #define BACKLIGHT_LVDS_OFF
1759 /* That one prevents proper CRT output with LCD off */
1760 #undef BACKLIGHT_DAC_OFF
1761 
1762 static int aty128_bl_update_status(struct backlight_device *bd)
1763 {
1764     struct aty128fb_par *par = bl_get_data(bd);
1765     unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1766     int level;
1767 
1768     if (bd->props.power != FB_BLANK_UNBLANK ||
1769         bd->props.fb_blank != FB_BLANK_UNBLANK ||
1770         !par->lcd_on)
1771         level = 0;
1772     else
1773         level = bd->props.brightness;
1774 
1775     reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1776     if (level > 0) {
1777         reg |= LVDS_DIGION;
1778         if (!(reg & LVDS_ON)) {
1779             reg &= ~LVDS_BLON;
1780             aty_st_le32(LVDS_GEN_CNTL, reg);
1781             aty_ld_le32(LVDS_GEN_CNTL);
1782             mdelay(10);
1783             reg |= LVDS_BLON;
1784             aty_st_le32(LVDS_GEN_CNTL, reg);
1785         }
1786         reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1787         reg |= (aty128_bl_get_level_brightness(par, level) <<
1788             LVDS_BL_MOD_LEVEL_SHIFT);
1789 #ifdef BACKLIGHT_LVDS_OFF
1790         reg |= LVDS_ON | LVDS_EN;
1791         reg &= ~LVDS_DISPLAY_DIS;
1792 #endif
1793         aty_st_le32(LVDS_GEN_CNTL, reg);
1794 #ifdef BACKLIGHT_DAC_OFF
1795         aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1796 #endif
1797     } else {
1798         reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1799         reg |= (aty128_bl_get_level_brightness(par, 0) <<
1800             LVDS_BL_MOD_LEVEL_SHIFT);
1801 #ifdef BACKLIGHT_LVDS_OFF
1802         reg |= LVDS_DISPLAY_DIS;
1803         aty_st_le32(LVDS_GEN_CNTL, reg);
1804         aty_ld_le32(LVDS_GEN_CNTL);
1805         udelay(10);
1806         reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1807 #endif
1808         aty_st_le32(LVDS_GEN_CNTL, reg);
1809 #ifdef BACKLIGHT_DAC_OFF
1810         aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1811 #endif
1812     }
1813 
1814     return 0;
1815 }
1816 
1817 static const struct backlight_ops aty128_bl_data = {
1818     .update_status  = aty128_bl_update_status,
1819 };
1820 
1821 static void aty128_bl_set_power(struct fb_info *info, int power)
1822 {
1823     if (info->bl_dev) {
1824         info->bl_dev->props.power = power;
1825         backlight_update_status(info->bl_dev);
1826     }
1827 }
1828 
1829 static void aty128_bl_init(struct aty128fb_par *par)
1830 {
1831     struct backlight_properties props;
1832     struct fb_info *info = pci_get_drvdata(par->pdev);
1833     struct backlight_device *bd;
1834     char name[12];
1835 
1836     /* Could be extended to Rage128Pro LVDS output too */
1837     if (par->chip_gen != rage_M3)
1838         return;
1839 
1840 #ifdef CONFIG_PMAC_BACKLIGHT
1841     if (!pmac_has_backlight_type("ati"))
1842         return;
1843 #endif
1844 
1845     snprintf(name, sizeof(name), "aty128bl%d", info->node);
1846 
1847     memset(&props, 0, sizeof(struct backlight_properties));
1848     props.type = BACKLIGHT_RAW;
1849     props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1850     bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1851                        &props);
1852     if (IS_ERR(bd)) {
1853         info->bl_dev = NULL;
1854         printk(KERN_WARNING "aty128: Backlight registration failed\n");
1855         goto error;
1856     }
1857 
1858     info->bl_dev = bd;
1859     fb_bl_default_curve(info, 0,
1860          63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1861         219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1862 
1863     bd->props.brightness = bd->props.max_brightness;
1864     bd->props.power = FB_BLANK_UNBLANK;
1865     backlight_update_status(bd);
1866 
1867     printk("aty128: Backlight initialized (%s)\n", name);
1868 
1869     return;
1870 
1871 error:
1872     return;
1873 }
1874 
1875 static void aty128_bl_exit(struct backlight_device *bd)
1876 {
1877     backlight_device_unregister(bd);
1878     printk("aty128: Backlight unloaded\n");
1879 }
1880 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1881 
1882 /*
1883  *  Initialisation
1884  */
1885 
1886 #ifdef CONFIG_PPC_PMAC__disabled
1887 static void aty128_early_resume(void *data)
1888 {
1889         struct aty128fb_par *par = data;
1890 
1891     if (!console_trylock())
1892         return;
1893     pci_restore_state(par->pdev);
1894     aty128_do_resume(par->pdev);
1895     console_unlock();
1896 }
1897 #endif /* CONFIG_PPC_PMAC */
1898 
1899 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1900 {
1901     struct fb_info *info = pci_get_drvdata(pdev);
1902     struct aty128fb_par *par = info->par;
1903     struct fb_var_screeninfo var;
1904     char video_card[50];
1905     u8 chip_rev;
1906     u32 dac;
1907 
1908     /* Get the chip revision */
1909     chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1910 
1911     strcpy(video_card, "Rage128 XX ");
1912     video_card[8] = ent->device >> 8;
1913     video_card[9] = ent->device & 0xFF;
1914 
1915     /* range check to make sure */
1916     if (ent->driver_data < ARRAY_SIZE(r128_family))
1917         strlcat(video_card, r128_family[ent->driver_data],
1918             sizeof(video_card));
1919 
1920     printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1921 
1922     if (par->vram_size % (1024 * 1024) == 0)
1923         printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1924     else
1925         printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1926 
1927     par->chip_gen = ent->driver_data;
1928 
1929     /* fill in info */
1930     info->fbops = &aty128fb_ops;
1931     info->flags = FBINFO_FLAG_DEFAULT;
1932 
1933     par->lcd_on = default_lcd_on;
1934     par->crt_on = default_crt_on;
1935 
1936     var = default_var;
1937 #ifdef CONFIG_PPC_PMAC
1938     if (machine_is(powermac)) {
1939         /* Indicate sleep capability */
1940         if (par->chip_gen == rage_M3) {
1941             pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1942 #if 0 /* Disable the early video resume hack for now as it's causing problems,
1943        * among others we now rely on the PCI core restoring the config space
1944        * for us, which isn't the case with that hack, and that code path causes
1945        * various things to be called with interrupts off while they shouldn't.
1946        * I'm leaving the code in as it can be useful for debugging purposes
1947        */
1948             pmac_set_early_video_resume(aty128_early_resume, par);
1949 #endif
1950         }
1951 
1952         /* Find default mode */
1953         if (mode_option) {
1954             if (!mac_find_mode(&var, info, mode_option, 8))
1955                 var = default_var;
1956         } else {
1957             if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1958                 default_vmode = VMODE_1024_768_60;
1959 
1960             /* iMacs need that resolution
1961              * PowerMac2,1 first r128 iMacs
1962              * PowerMac2,2 summer 2000 iMacs
1963              * PowerMac4,1 january 2001 iMacs "flower power"
1964              */
1965             if (of_machine_is_compatible("PowerMac2,1") ||
1966                 of_machine_is_compatible("PowerMac2,2") ||
1967                 of_machine_is_compatible("PowerMac4,1"))
1968                 default_vmode = VMODE_1024_768_75;
1969 
1970             /* iBook SE */
1971             if (of_machine_is_compatible("PowerBook2,2"))
1972                 default_vmode = VMODE_800_600_60;
1973 
1974             /* PowerBook Firewire (Pismo), iBook Dual USB */
1975             if (of_machine_is_compatible("PowerBook3,1") ||
1976                 of_machine_is_compatible("PowerBook4,1"))
1977                 default_vmode = VMODE_1024_768_60;
1978 
1979             /* PowerBook Titanium */
1980             if (of_machine_is_compatible("PowerBook3,2"))
1981                 default_vmode = VMODE_1152_768_60;
1982     
1983             if (default_cmode > 16) 
1984                 default_cmode = CMODE_32;
1985             else if (default_cmode > 8) 
1986                 default_cmode = CMODE_16;
1987             else 
1988                 default_cmode = CMODE_8;
1989 
1990             if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1991                 var = default_var;
1992         }
1993     } else
1994 #endif /* CONFIG_PPC_PMAC */
1995     {
1996         if (mode_option)
1997             if (fb_find_mode(&var, info, mode_option, NULL, 
1998                      0, &defaultmode, 8) == 0)
1999                 var = default_var;
2000     }
2001 
2002     var.accel_flags &= ~FB_ACCELF_TEXT;
2003 //  var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
2004 
2005     if (aty128fb_check_var(&var, info)) {
2006         printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2007         return 0;
2008     }
2009 
2010     /* setup the DAC the way we like it */
2011     dac = aty_ld_le32(DAC_CNTL);
2012     dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2013     dac |= DAC_MASK;
2014     if (par->chip_gen == rage_M3)
2015         dac |= DAC_PALETTE2_SNOOP_EN;
2016     aty_st_le32(DAC_CNTL, dac);
2017 
2018     /* turn off bus mastering, just in case */
2019     aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2020 
2021     info->var = var;
2022     fb_alloc_cmap(&info->cmap, 256, 0);
2023 
2024     var.activate = FB_ACTIVATE_NOW;
2025 
2026     aty128_init_engine(par);
2027 
2028     par->pdev = pdev;
2029     par->asleep = 0;
2030     par->lock_blank = 0;
2031 
2032 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2033     if (backlight)
2034         aty128_bl_init(par);
2035 #endif
2036 
2037     if (register_framebuffer(info) < 0)
2038         return 0;
2039 
2040     fb_info(info, "%s frame buffer device on %s\n",
2041         info->fix.id, video_card);
2042 
2043     return 1;   /* success! */
2044 }
2045 
2046 #ifdef CONFIG_PCI
2047 /* register a card    ++ajoshi */
2048 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2049 {
2050     unsigned long fb_addr, reg_addr;
2051     struct aty128fb_par *par;
2052     struct fb_info *info;
2053     int err;
2054 #ifndef __sparc__
2055     void __iomem *bios = NULL;
2056 #endif
2057 
2058     /* Enable device in PCI config */
2059     if ((err = pci_enable_device(pdev))) {
2060         printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2061                 err);
2062         return -ENODEV;
2063     }
2064 
2065     fb_addr = pci_resource_start(pdev, 0);
2066     if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2067                 "aty128fb FB")) {
2068         printk(KERN_ERR "aty128fb: cannot reserve frame "
2069                 "buffer memory\n");
2070         return -ENODEV;
2071     }
2072 
2073     reg_addr = pci_resource_start(pdev, 2);
2074     if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2075                 "aty128fb MMIO")) {
2076         printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2077         goto err_free_fb;
2078     }
2079 
2080     /* We have the resources. Now virtualize them */
2081     info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2082     if (!info)
2083         goto err_free_mmio;
2084 
2085     par = info->par;
2086 
2087     info->pseudo_palette = par->pseudo_palette;
2088 
2089     /* Virtualize mmio region */
2090     info->fix.mmio_start = reg_addr;
2091     par->regbase = pci_ioremap_bar(pdev, 2);
2092     if (!par->regbase)
2093         goto err_free_info;
2094 
2095     /* Grab memory size from the card */
2096     // How does this relate to the resource length from the PCI hardware?
2097     par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2098 
2099     /* Virtualize the framebuffer */
2100     info->screen_base = ioremap_wc(fb_addr, par->vram_size);
2101     if (!info->screen_base)
2102         goto err_unmap_out;
2103 
2104     /* Set up info->fix */
2105     info->fix = aty128fb_fix;
2106     info->fix.smem_start = fb_addr;
2107     info->fix.smem_len = par->vram_size;
2108     info->fix.mmio_start = reg_addr;
2109 
2110     /* If we can't test scratch registers, something is seriously wrong */
2111     if (!register_test(par)) {
2112         printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2113         goto err_out;
2114     }
2115 
2116 #ifndef __sparc__
2117     bios = aty128_map_ROM(par, pdev);
2118 #ifdef CONFIG_X86
2119     if (bios == NULL)
2120         bios = aty128_find_mem_vbios(par);
2121 #endif
2122     if (bios == NULL)
2123         printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2124     else {
2125         printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2126         aty128_get_pllinfo(par, bios);
2127         pci_unmap_rom(pdev, bios);
2128     }
2129 #endif /* __sparc__ */
2130 
2131     aty128_timings(par);
2132     pci_set_drvdata(pdev, info);
2133 
2134     if (!aty128_init(pdev, ent))
2135         goto err_out;
2136 
2137     if (mtrr)
2138         par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
2139                           par->vram_size);
2140     return 0;
2141 
2142 err_out:
2143     iounmap(info->screen_base);
2144 err_unmap_out:
2145     iounmap(par->regbase);
2146 err_free_info:
2147     framebuffer_release(info);
2148 err_free_mmio:
2149     release_mem_region(pci_resource_start(pdev, 2),
2150             pci_resource_len(pdev, 2));
2151 err_free_fb:
2152     release_mem_region(pci_resource_start(pdev, 0),
2153             pci_resource_len(pdev, 0));
2154     return -ENODEV;
2155 }
2156 
2157 static void aty128_remove(struct pci_dev *pdev)
2158 {
2159     struct fb_info *info = pci_get_drvdata(pdev);
2160     struct aty128fb_par *par;
2161 
2162     if (!info)
2163         return;
2164 
2165     par = info->par;
2166 
2167     unregister_framebuffer(info);
2168 
2169 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2170     aty128_bl_exit(info->bl_dev);
2171 #endif
2172 
2173     arch_phys_wc_del(par->wc_cookie);
2174     iounmap(par->regbase);
2175     iounmap(info->screen_base);
2176 
2177     release_mem_region(pci_resource_start(pdev, 0),
2178                pci_resource_len(pdev, 0));
2179     release_mem_region(pci_resource_start(pdev, 2),
2180                pci_resource_len(pdev, 2));
2181     framebuffer_release(info);
2182 }
2183 #endif /* CONFIG_PCI */
2184 
2185 
2186 
2187     /*
2188      *  Blank the display.
2189      */
2190 static int aty128fb_blank(int blank, struct fb_info *fb)
2191 {
2192     struct aty128fb_par *par = fb->par;
2193     u8 state;
2194 
2195     if (par->lock_blank || par->asleep)
2196         return 0;
2197 
2198     switch (blank) {
2199     case FB_BLANK_NORMAL:
2200         state = 4;
2201         break;
2202     case FB_BLANK_VSYNC_SUSPEND:
2203         state = 6;
2204         break;
2205     case FB_BLANK_HSYNC_SUSPEND:
2206         state = 5;
2207         break;
2208     case FB_BLANK_POWERDOWN:
2209         state = 7;
2210         break;
2211     case FB_BLANK_UNBLANK:
2212     default:
2213         state = 0;
2214         break;
2215     }
2216     aty_st_8(CRTC_EXT_CNTL+1, state);
2217 
2218     if (par->chip_gen == rage_M3) {
2219         aty128_set_crt_enable(par, par->crt_on && !blank);
2220         aty128_set_lcd_enable(par, par->lcd_on && !blank);
2221     }
2222 
2223     return 0;
2224 }
2225 
2226 /*
2227  *  Set a single color register. The values supplied are already
2228  *  rounded down to the hardware's capabilities (according to the
2229  *  entries in the var structure). Return != 0 for invalid regno.
2230  */
2231 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2232                   u_int transp, struct fb_info *info)
2233 {
2234     struct aty128fb_par *par = info->par;
2235 
2236     if (regno > 255
2237         || (par->crtc.depth == 16 && regno > 63)
2238         || (par->crtc.depth == 15 && regno > 31))
2239         return 1;
2240 
2241     red >>= 8;
2242     green >>= 8;
2243     blue >>= 8;
2244 
2245     if (regno < 16) {
2246         int i;
2247         u32 *pal = info->pseudo_palette;
2248 
2249         switch (par->crtc.depth) {
2250         case 15:
2251             pal[regno] = (regno << 10) | (regno << 5) | regno;
2252             break;
2253         case 16:
2254             pal[regno] = (regno << 11) | (regno << 6) | regno;
2255             break;
2256         case 24:
2257             pal[regno] = (regno << 16) | (regno << 8) | regno;
2258             break;
2259         case 32:
2260             i = (regno << 8) | regno;
2261             pal[regno] = (i << 16) | i;
2262             break;
2263         }
2264     }
2265 
2266     if (par->crtc.depth == 16 && regno > 0) {
2267         /*
2268          * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2269          * have 32 slots for R and B values but 64 slots for G values.
2270          * Thus the R and B values go in one slot but the G value
2271          * goes in a different slot, and we have to avoid disturbing
2272          * the other fields in the slots we touch.
2273          */
2274         par->green[regno] = green;
2275         if (regno < 32) {
2276             par->red[regno] = red;
2277             par->blue[regno] = blue;
2278             aty128_st_pal(regno * 8, red, par->green[regno*2],
2279                       blue, par);
2280         }
2281         red = par->red[regno/2];
2282         blue = par->blue[regno/2];
2283         regno <<= 2;
2284     } else if (par->crtc.bpp == 16)
2285         regno <<= 3;
2286     aty128_st_pal(regno, red, green, blue, par);
2287 
2288     return 0;
2289 }
2290 
2291 #define ATY_MIRROR_LCD_ON   0x00000001
2292 #define ATY_MIRROR_CRT_ON   0x00000002
2293 
2294 /* out param: u32*  backlight value: 0 to 15 */
2295 #define FBIO_ATY128_GET_MIRROR  _IOR('@', 1, __u32)
2296 /* in param: u32*   backlight value: 0 to 15 */
2297 #define FBIO_ATY128_SET_MIRROR  _IOW('@', 2, __u32)
2298 
2299 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2300 {
2301     struct aty128fb_par *par = info->par;
2302     u32 value;
2303     int rc;
2304     
2305     switch (cmd) {
2306     case FBIO_ATY128_SET_MIRROR:
2307         if (par->chip_gen != rage_M3)
2308             return -EINVAL;
2309         rc = get_user(value, (__u32 __user *)arg);
2310         if (rc)
2311             return rc;
2312         par->lcd_on = (value & 0x01) != 0;
2313         par->crt_on = (value & 0x02) != 0;
2314         if (!par->crt_on && !par->lcd_on)
2315             par->lcd_on = 1;
2316         aty128_set_crt_enable(par, par->crt_on);    
2317         aty128_set_lcd_enable(par, par->lcd_on);    
2318         return 0;
2319     case FBIO_ATY128_GET_MIRROR:
2320         if (par->chip_gen != rage_M3)
2321             return -EINVAL;
2322         value = (par->crt_on << 1) | par->lcd_on;
2323         return put_user(value, (__u32 __user *)arg);
2324     }
2325     return -EINVAL;
2326 }
2327 
2328 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2329 {
2330     u32 pmgt;
2331 
2332     if (!par->pdev->pm_cap)
2333         return;
2334         
2335     /* Set the chip into the appropriate suspend mode (we use D2,
2336      * D3 would require a complete re-initialisation of the chip,
2337      * including PCI config registers, clocks, AGP configuration, ...)
2338      *
2339      * For resume, the core will have already brought us back to D0
2340      */
2341     if (suspend) {
2342         /* Make sure CRTC2 is reset. Remove that the day we decide to
2343          * actually use CRTC2 and replace it with real code for disabling
2344          * the CRTC2 output during sleep
2345          */
2346         aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2347             ~(CRTC2_EN));
2348 
2349         /* Set the power management mode to be PCI based */
2350         /* Use this magic value for now */
2351         pmgt = 0x0c005407;
2352         aty_st_pll(POWER_MANAGEMENT, pmgt);
2353         (void)aty_ld_pll(POWER_MANAGEMENT);
2354         aty_st_le32(BUS_CNTL1, 0x00000010);
2355         aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2356         msleep(100);
2357     }
2358 }
2359 
2360 static int aty128_pci_suspend_late(struct device *dev, pm_message_t state)
2361 {
2362     struct pci_dev *pdev = to_pci_dev(dev);
2363     struct fb_info *info = pci_get_drvdata(pdev);
2364     struct aty128fb_par *par = info->par;
2365 
2366     /* We don't do anything but D2, for now we return 0, but
2367      * we may want to change that. How do we know if the BIOS
2368      * can properly take care of D3 ? Also, with swsusp, we
2369      * know we'll be rebooted, ...
2370      */
2371 #ifndef CONFIG_PPC_PMAC
2372     /* HACK ALERT ! Once I find a proper way to say to each driver
2373      * individually what will happen with it's PCI slot, I'll change
2374      * that. On laptops, the AGP slot is just unclocked, so D2 is
2375      * expected, while on desktops, the card is powered off
2376      */
2377     return 0;
2378 #endif /* CONFIG_PPC_PMAC */
2379      
2380     if (state.event == pdev->dev.power.power_state.event)
2381         return 0;
2382 
2383     printk(KERN_DEBUG "aty128fb: suspending...\n");
2384     
2385     console_lock();
2386 
2387     fb_set_suspend(info, 1);
2388 
2389     /* Make sure engine is reset */
2390     wait_for_idle(par);
2391     aty128_reset_engine(par);
2392     wait_for_idle(par);
2393 
2394     /* Blank display and LCD */
2395     aty128fb_blank(FB_BLANK_POWERDOWN, info);
2396 
2397     /* Sleep */
2398     par->asleep = 1;
2399     par->lock_blank = 1;
2400 
2401 #ifdef CONFIG_PPC_PMAC
2402     /* On powermac, we have hooks to properly suspend/resume AGP now,
2403      * use them here. We'll ultimately need some generic support here,
2404      * but the generic code isn't quite ready for that yet
2405      */
2406     pmac_suspend_agp_for_card(pdev);
2407 #endif /* CONFIG_PPC_PMAC */
2408 
2409     /* We need a way to make sure the fbdev layer will _not_ touch the
2410      * framebuffer before we put the chip to suspend state. On 2.4, I
2411      * used dummy fb ops, 2.5 need proper support for this at the
2412      * fbdev level
2413      */
2414     if (state.event != PM_EVENT_ON)
2415         aty128_set_suspend(par, 1);
2416 
2417     console_unlock();
2418 
2419     pdev->dev.power.power_state = state;
2420 
2421     return 0;
2422 }
2423 
2424 static int __maybe_unused aty128_pci_suspend(struct device *dev)
2425 {
2426     return aty128_pci_suspend_late(dev, PMSG_SUSPEND);
2427 }
2428 
2429 static int __maybe_unused aty128_pci_hibernate(struct device *dev)
2430 {
2431     return aty128_pci_suspend_late(dev, PMSG_HIBERNATE);
2432 }
2433 
2434 static int __maybe_unused aty128_pci_freeze(struct device *dev)
2435 {
2436     return aty128_pci_suspend_late(dev, PMSG_FREEZE);
2437 }
2438 
2439 static int aty128_do_resume(struct pci_dev *pdev)
2440 {
2441     struct fb_info *info = pci_get_drvdata(pdev);
2442     struct aty128fb_par *par = info->par;
2443 
2444     if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2445         return 0;
2446 
2447     /* PCI state will have been restored by the core, so
2448      * we should be in D0 now with our config space fully
2449      * restored
2450      */
2451 
2452     /* Wakeup chip */
2453     aty128_set_suspend(par, 0);
2454     par->asleep = 0;
2455 
2456     /* Restore display & engine */
2457     aty128_reset_engine(par);
2458     wait_for_idle(par);
2459     aty128fb_set_par(info);
2460     fb_pan_display(info, &info->var);
2461     fb_set_cmap(&info->cmap, info);
2462 
2463     /* Refresh */
2464     fb_set_suspend(info, 0);
2465 
2466     /* Unblank */
2467     par->lock_blank = 0;
2468     aty128fb_blank(0, info);
2469 
2470 #ifdef CONFIG_PPC_PMAC
2471     /* On powermac, we have hooks to properly suspend/resume AGP now,
2472      * use them here. We'll ultimately need some generic support here,
2473      * but the generic code isn't quite ready for that yet
2474      */
2475     pmac_resume_agp_for_card(pdev);
2476 #endif /* CONFIG_PPC_PMAC */
2477 
2478     pdev->dev.power.power_state = PMSG_ON;
2479 
2480     printk(KERN_DEBUG "aty128fb: resumed !\n");
2481 
2482     return 0;
2483 }
2484 
2485 static int __maybe_unused aty128_pci_resume(struct device *dev)
2486 {
2487     int rc;
2488 
2489     console_lock();
2490     rc = aty128_do_resume(to_pci_dev(dev));
2491     console_unlock();
2492 
2493     return rc;
2494 }
2495 
2496 
2497 static int aty128fb_init(void)
2498 {
2499 #ifndef MODULE
2500     char *option = NULL;
2501 
2502     if (fb_get_options("aty128fb", &option))
2503         return -ENODEV;
2504     aty128fb_setup(option);
2505 #endif
2506 
2507     return pci_register_driver(&aty128fb_driver);
2508 }
2509 
2510 static void __exit aty128fb_exit(void)
2511 {
2512     pci_unregister_driver(&aty128fb_driver);
2513 }
2514 
2515 module_init(aty128fb_init);
2516 
2517 module_exit(aty128fb_exit);
2518 
2519 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2520 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2521 MODULE_LICENSE("GPL");
2522 module_param(mode_option, charp, 0);
2523 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2524 module_param_named(nomtrr, mtrr, invbool, 0);
2525 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
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