video/fbdev/acornfb.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/drivers/video/acornfb.h
0004  *
0005  *  Copyright (C) 1998,1999 Russell King
0006  *
0007  *  Frame buffer code for Acorn platforms
0008  */
0009 #if defined(HAS_VIDC20)
0010 #include <asm/hardware/iomd.h>
0011 #define VIDC_PALETTE_SIZE   256
0012 #define VIDC_NAME       "VIDC20"
0013 #endif
0014
0015 #define EXTEND8(x) ((x)|(x)<<8)
0016 #define EXTEND4(x) ((x)|(x)<<4|(x)<<8|(x)<<12)
0017
0018 struct vidc20_palette {
0019     u_int red:8;
0020     u_int green:8;
0021     u_int blue:8;
0022     u_int ext:4;
0023     u_int unused:4;
0024 };
0025
0026 struct vidc_palette {
0027     u_int red:4;
0028     u_int green:4;
0029     u_int blue:4;
0030     u_int trans:1;
0031     u_int sbz1:13;
0032     u_int reg:4;
0033     u_int sbz2:2;
0034 };
0035
0036 union palette {
0037     struct vidc20_palette   vidc20;
0038     struct vidc_palette vidc;
0039     u_int   p;
0040 };
0041
0042 struct acornfb_par {
0043     struct device   *dev;
0044     unsigned long   screen_end;
0045     unsigned int    dram_size;
0046     unsigned int    vram_half_sam;
0047     unsigned int    palette_size;
0048       signed int    montype;
0049     unsigned int    using_vram  : 1;
0050     unsigned int    dpms        : 1;
0051
0052     union palette palette[VIDC_PALETTE_SIZE];
0053
0054     u32     pseudo_palette[16];
0055 };
0056
0057 struct vidc_timing {
0058     u_int   h_cycle;
0059     u_int   h_sync_width;
0060     u_int   h_border_start;
0061     u_int   h_display_start;
0062     u_int   h_display_end;
0063     u_int   h_border_end;
0064     u_int   h_interlace;
0065
0066     u_int   v_cycle;
0067     u_int   v_sync_width;
0068     u_int   v_border_start;
0069     u_int   v_display_start;
0070     u_int   v_display_end;
0071     u_int   v_border_end;
0072
0073     u_int   control;
0074
0075     /* VIDC20 only */
0076     u_int   pll_ctl;
0077 };
0078
0079 struct modey_params {
0080     u_int   y_res;
0081     u_int   u_margin;
0082     u_int   b_margin;
0083     u_int   vsync_len;
0084     u_int   vf;
0085 };
0086
0087 struct modex_params {
0088     u_int   x_res;
0089     u_int   l_margin;
0090     u_int   r_margin;
0091     u_int   hsync_len;
0092     u_int   clock;
0093     u_int   hf;
0094     const struct modey_params *modey;
0095 };
0096
0097 #ifdef HAS_VIDC20
0098 /*
0099  * VIDC20 registers
0100  */
0101 #define VIDC20_CTRL     0xe0000000
0102 #define VIDC20_CTRL_PIX_VCLK    (0 << 0)
0103 #define VIDC20_CTRL_PIX_HCLK    (1 << 0)
0104 #define VIDC20_CTRL_PIX_RCLK    (2 << 0)
0105 #define VIDC20_CTRL_PIX_CK  (0 << 2)
0106 #define VIDC20_CTRL_PIX_CK2 (1 << 2)
0107 #define VIDC20_CTRL_PIX_CK3 (2 << 2)
0108 #define VIDC20_CTRL_PIX_CK4 (3 << 2)
0109 #define VIDC20_CTRL_PIX_CK5 (4 << 2)
0110 #define VIDC20_CTRL_PIX_CK6 (5 << 2)
0111 #define VIDC20_CTRL_PIX_CK7 (6 << 2)
0112 #define VIDC20_CTRL_PIX_CK8 (7 << 2)
0113 #define VIDC20_CTRL_1BPP    (0 << 5)
0114 #define VIDC20_CTRL_2BPP    (1 << 5)
0115 #define VIDC20_CTRL_4BPP    (2 << 5)
0116 #define VIDC20_CTRL_8BPP    (3 << 5)
0117 #define VIDC20_CTRL_16BPP   (4 << 5)
0118 #define VIDC20_CTRL_32BPP   (6 << 5)
0119 #define VIDC20_CTRL_FIFO_NS (0 << 8)
0120 #define VIDC20_CTRL_FIFO_4  (1 << 8)
0121 #define VIDC20_CTRL_FIFO_8  (2 << 8)
0122 #define VIDC20_CTRL_FIFO_12 (3 << 8)
0123 #define VIDC20_CTRL_FIFO_16 (4 << 8)
0124 #define VIDC20_CTRL_FIFO_20 (5 << 8)
0125 #define VIDC20_CTRL_FIFO_24 (6 << 8)
0126 #define VIDC20_CTRL_FIFO_28 (7 << 8)
0127 #define VIDC20_CTRL_INT     (1 << 12)
0128 #define VIDC20_CTRL_DUP     (1 << 13)
0129 #define VIDC20_CTRL_PDOWN   (1 << 14)
0130
0131 #define VIDC20_ECTL     0xc0000000
0132 #define VIDC20_ECTL_REG(x)  ((x) & 0xf3)
0133 #define VIDC20_ECTL_ECK     (1 << 2)
0134 #define VIDC20_ECTL_REDPED  (1 << 8)
0135 #define VIDC20_ECTL_GREENPED    (1 << 9)
0136 #define VIDC20_ECTL_BLUEPED (1 << 10)
0137 #define VIDC20_ECTL_DAC     (1 << 12)
0138 #define VIDC20_ECTL_LCDGS   (1 << 13)
0139 #define VIDC20_ECTL_HRM     (1 << 14)
0140
0141 #define VIDC20_ECTL_HS_MASK (3 << 16)
0142 #define VIDC20_ECTL_HS_HSYNC    (0 << 16)
0143 #define VIDC20_ECTL_HS_NHSYNC   (1 << 16)
0144 #define VIDC20_ECTL_HS_CSYNC    (2 << 16)
0145 #define VIDC20_ECTL_HS_NCSYNC   (3 << 16)
0146
0147 #define VIDC20_ECTL_VS_MASK (3 << 18)
0148 #define VIDC20_ECTL_VS_VSYNC    (0 << 18)
0149 #define VIDC20_ECTL_VS_NVSYNC   (1 << 18)
0150 #define VIDC20_ECTL_VS_CSYNC    (2 << 18)
0151 #define VIDC20_ECTL_VS_NCSYNC   (3 << 18)
0152
0153 #define VIDC20_DCTL     0xf0000000
0154 /* 0-9 = number of words in scanline */
0155 #define VIDC20_DCTL_SNA     (1 << 12)
0156 #define VIDC20_DCTL_HDIS    (1 << 13)
0157 #define VIDC20_DCTL_BUS_NS  (0 << 16)
0158 #define VIDC20_DCTL_BUS_D31_0   (1 << 16)
0159 #define VIDC20_DCTL_BUS_D63_32  (2 << 16)
0160 #define VIDC20_DCTL_BUS_D63_0   (3 << 16)
0161 #define VIDC20_DCTL_VRAM_DIS    (0 << 18)
0162 #define VIDC20_DCTL_VRAM_PXCLK  (1 << 18)
0163 #define VIDC20_DCTL_VRAM_PXCLK2 (2 << 18)
0164 #define VIDC20_DCTL_VRAM_PXCLK4 (3 << 18)
0165
0166 #endif