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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * (C) Copyright 2008
0004  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
0005  *
0006  * This driver implements a lcd device for the ILITEK 922x display
0007  * controller. The interface to the display is SPI and the display's
0008  * memory is cyclically updated over the RGB interface.
0009  */
0010 
0011 #include <linux/fb.h>
0012 #include <linux/delay.h>
0013 #include <linux/errno.h>
0014 #include <linux/init.h>
0015 #include <linux/kernel.h>
0016 #include <linux/lcd.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/slab.h>
0020 #include <linux/spi/spi.h>
0021 #include <linux/string.h>
0022 
0023 /* Register offset, see manual section 8.2 */
0024 #define REG_START_OSCILLATION           0x00
0025 #define REG_DRIVER_CODE_READ            0x00
0026 #define REG_DRIVER_OUTPUT_CONTROL       0x01
0027 #define REG_LCD_AC_DRIVEING_CONTROL     0x02
0028 #define REG_ENTRY_MODE              0x03
0029 #define REG_COMPARE_1               0x04
0030 #define REG_COMPARE_2               0x05
0031 #define REG_DISPLAY_CONTROL_1           0x07
0032 #define REG_DISPLAY_CONTROL_2           0x08
0033 #define REG_DISPLAY_CONTROL_3           0x09
0034 #define REG_FRAME_CYCLE_CONTROL         0x0B
0035 #define REG_EXT_INTF_CONTROL            0x0C
0036 #define REG_POWER_CONTROL_1         0x10
0037 #define REG_POWER_CONTROL_2         0x11
0038 #define REG_POWER_CONTROL_3         0x12
0039 #define REG_POWER_CONTROL_4         0x13
0040 #define REG_RAM_ADDRESS_SET         0x21
0041 #define REG_WRITE_DATA_TO_GRAM          0x22
0042 #define REG_RAM_WRITE_MASK1         0x23
0043 #define REG_RAM_WRITE_MASK2         0x24
0044 #define REG_GAMMA_CONTROL_1         0x30
0045 #define REG_GAMMA_CONTROL_2         0x31
0046 #define REG_GAMMA_CONTROL_3         0x32
0047 #define REG_GAMMA_CONTROL_4         0x33
0048 #define REG_GAMMA_CONTROL_5         0x34
0049 #define REG_GAMMA_CONTROL_6         0x35
0050 #define REG_GAMMA_CONTROL_7         0x36
0051 #define REG_GAMMA_CONTROL_8         0x37
0052 #define REG_GAMMA_CONTROL_9         0x38
0053 #define REG_GAMMA_CONTROL_10            0x39
0054 #define REG_GATE_SCAN_CONTROL           0x40
0055 #define REG_VERT_SCROLL_CONTROL         0x41
0056 #define REG_FIRST_SCREEN_DRIVE_POS      0x42
0057 #define REG_SECOND_SCREEN_DRIVE_POS     0x43
0058 #define REG_RAM_ADDR_POS_H          0x44
0059 #define REG_RAM_ADDR_POS_V          0x45
0060 #define REG_OSCILLATOR_CONTROL          0x4F
0061 #define REG_GPIO                0x60
0062 #define REG_OTP_VCM_PROGRAMMING         0x61
0063 #define REG_OTP_VCM_STATUS_ENABLE       0x62
0064 #define REG_OTP_PROGRAMMING_ID_KEY      0x65
0065 
0066 /*
0067  * maximum frequency for register access
0068  * (not for the GRAM access)
0069  */
0070 #define ILITEK_MAX_FREQ_REG 4000000
0071 
0072 /*
0073  * Device ID as found in the datasheet (supports 9221 and 9222)
0074  */
0075 #define ILITEK_DEVICE_ID    0x9220
0076 #define ILITEK_DEVICE_ID_MASK   0xFFF0
0077 
0078 /* Last two bits in the START BYTE */
0079 #define START_RS_INDEX      0
0080 #define START_RS_REG        1
0081 #define START_RW_WRITE      0
0082 #define START_RW_READ       1
0083 
0084 /**
0085  * START_BYTE(id, rs, rw)
0086  *
0087  * Set the start byte according to the required operation.
0088  * The start byte is defined as:
0089  *   ----------------------------------
0090  *  | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
0091  *   ----------------------------------
0092  * @id: display's id as set by the manufacturer
0093  * @rs: operation type bit, one of:
0094  *    - START_RS_INDEX  set the index register
0095  *    - START_RS_REG    write/read registers/GRAM
0096  * @rw: read/write operation
0097  *   - START_RW_WRITE   write
0098  *   - START_RW_READ    read
0099  */
0100 #define START_BYTE(id, rs, rw)  \
0101     (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
0102 
0103 /**
0104  * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
0105  *  for the SPI transfer. According to the datasheet, the controller
0106  *  accept higher frequency for the GRAM transfer, but it requires
0107  *  lower frequency when the registers are read/written.
0108  *  The macro sets the frequency in the spi_transfer structure if
0109  *  the frequency exceeds the maximum value.
0110  * @s: pointer to an SPI device
0111  * @x: pointer to the read/write buffer pair
0112  */
0113 #define CHECK_FREQ_REG(s, x)    \
0114     do {            \
0115         if (s->max_speed_hz > ILITEK_MAX_FREQ_REG)  \
0116             ((struct spi_transfer *)x)->speed_hz =  \
0117                     ILITEK_MAX_FREQ_REG;    \
0118     } while (0)
0119 
0120 #define CMD_BUFSIZE     16
0121 
0122 #define POWER_IS_ON(pwr)    ((pwr) <= FB_BLANK_NORMAL)
0123 
0124 #define set_tx_byte(b)      (tx_invert ? ~(b) : b)
0125 
0126 /*
0127  * ili922x_id - id as set by manufacturer
0128  */
0129 static int ili922x_id = 1;
0130 module_param(ili922x_id, int, 0);
0131 
0132 static int tx_invert;
0133 module_param(tx_invert, int, 0);
0134 
0135 /*
0136  * driver's private structure
0137  */
0138 struct ili922x {
0139     struct spi_device *spi;
0140     struct lcd_device *ld;
0141     int power;
0142 };
0143 
0144 /**
0145  * ili922x_read_status - read status register from display
0146  * @spi: spi device
0147  * @rs:  output value
0148  */
0149 static int ili922x_read_status(struct spi_device *spi, u16 *rs)
0150 {
0151     struct spi_message msg;
0152     struct spi_transfer xfer;
0153     unsigned char tbuf[CMD_BUFSIZE];
0154     unsigned char rbuf[CMD_BUFSIZE];
0155     int ret, i;
0156 
0157     memset(&xfer, 0, sizeof(struct spi_transfer));
0158     spi_message_init(&msg);
0159     xfer.tx_buf = tbuf;
0160     xfer.rx_buf = rbuf;
0161     xfer.cs_change = 1;
0162     CHECK_FREQ_REG(spi, &xfer);
0163 
0164     tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
0165                      START_RW_READ));
0166     /*
0167      * we need 4-byte xfer here due to invalid dummy byte
0168      * received after start byte
0169      */
0170     for (i = 1; i < 4; i++)
0171         tbuf[i] = set_tx_byte(0);   /* dummy */
0172 
0173     xfer.bits_per_word = 8;
0174     xfer.len = 4;
0175     spi_message_add_tail(&xfer, &msg);
0176     ret = spi_sync(spi, &msg);
0177     if (ret < 0) {
0178         dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
0179         return ret;
0180     }
0181 
0182     *rs = (rbuf[2] << 8) + rbuf[3];
0183     return 0;
0184 }
0185 
0186 /**
0187  * ili922x_read - read register from display
0188  * @spi: spi device
0189  * @reg: offset of the register to be read
0190  * @rx:  output value
0191  */
0192 static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
0193 {
0194     struct spi_message msg;
0195     struct spi_transfer xfer_regindex, xfer_regvalue;
0196     unsigned char tbuf[CMD_BUFSIZE];
0197     unsigned char rbuf[CMD_BUFSIZE];
0198     int ret, len = 0, send_bytes;
0199 
0200     memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
0201     memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
0202     spi_message_init(&msg);
0203     xfer_regindex.tx_buf = tbuf;
0204     xfer_regindex.rx_buf = rbuf;
0205     xfer_regindex.cs_change = 1;
0206     CHECK_FREQ_REG(spi, &xfer_regindex);
0207 
0208     tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
0209                      START_RW_WRITE));
0210     tbuf[1] = set_tx_byte(0);
0211     tbuf[2] = set_tx_byte(reg);
0212     xfer_regindex.bits_per_word = 8;
0213     len = xfer_regindex.len = 3;
0214     spi_message_add_tail(&xfer_regindex, &msg);
0215 
0216     send_bytes = len;
0217 
0218     tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
0219                          START_RW_READ));
0220     tbuf[len++] = set_tx_byte(0);
0221     tbuf[len] = set_tx_byte(0);
0222 
0223     xfer_regvalue.cs_change = 1;
0224     xfer_regvalue.len = 3;
0225     xfer_regvalue.tx_buf = &tbuf[send_bytes];
0226     xfer_regvalue.rx_buf = &rbuf[send_bytes];
0227     CHECK_FREQ_REG(spi, &xfer_regvalue);
0228 
0229     spi_message_add_tail(&xfer_regvalue, &msg);
0230     ret = spi_sync(spi, &msg);
0231     if (ret < 0) {
0232         dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
0233         return ret;
0234     }
0235 
0236     *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
0237     return 0;
0238 }
0239 
0240 /**
0241  * ili922x_write - write a controller register
0242  * @spi: struct spi_device *
0243  * @reg: offset of the register to be written
0244  * @value: value to be written
0245  */
0246 static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
0247 {
0248     struct spi_message msg;
0249     struct spi_transfer xfer_regindex, xfer_regvalue;
0250     unsigned char tbuf[CMD_BUFSIZE];
0251     unsigned char rbuf[CMD_BUFSIZE];
0252     int ret;
0253 
0254     memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
0255     memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
0256 
0257     spi_message_init(&msg);
0258     xfer_regindex.tx_buf = tbuf;
0259     xfer_regindex.rx_buf = rbuf;
0260     xfer_regindex.cs_change = 1;
0261     CHECK_FREQ_REG(spi, &xfer_regindex);
0262 
0263     tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
0264                      START_RW_WRITE));
0265     tbuf[1] = set_tx_byte(0);
0266     tbuf[2] = set_tx_byte(reg);
0267     xfer_regindex.bits_per_word = 8;
0268     xfer_regindex.len = 3;
0269     spi_message_add_tail(&xfer_regindex, &msg);
0270 
0271     ret = spi_sync(spi, &msg);
0272 
0273     spi_message_init(&msg);
0274     tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
0275                      START_RW_WRITE));
0276     tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
0277     tbuf[2] = set_tx_byte(value & 0x00FF);
0278 
0279     xfer_regvalue.cs_change = 1;
0280     xfer_regvalue.len = 3;
0281     xfer_regvalue.tx_buf = tbuf;
0282     xfer_regvalue.rx_buf = rbuf;
0283     CHECK_FREQ_REG(spi, &xfer_regvalue);
0284 
0285     spi_message_add_tail(&xfer_regvalue, &msg);
0286 
0287     ret = spi_sync(spi, &msg);
0288     if (ret < 0) {
0289         dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
0290         return ret;
0291     }
0292     return 0;
0293 }
0294 
0295 #ifdef DEBUG
0296 /**
0297  * ili922x_reg_dump - dump all registers
0298  *
0299  * @spi: pointer to an SPI device
0300  */
0301 static void ili922x_reg_dump(struct spi_device *spi)
0302 {
0303     u8 reg;
0304     u16 rx;
0305 
0306     dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
0307     for (reg = REG_START_OSCILLATION;
0308          reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
0309         ili922x_read(spi, reg, &rx);
0310         dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
0311     }
0312 }
0313 #else
0314 static inline void ili922x_reg_dump(struct spi_device *spi) {}
0315 #endif
0316 
0317 /**
0318  * set_write_to_gram_reg - initialize the display to write the GRAM
0319  * @spi: spi device
0320  */
0321 static void set_write_to_gram_reg(struct spi_device *spi)
0322 {
0323     struct spi_message msg;
0324     struct spi_transfer xfer;
0325     unsigned char tbuf[CMD_BUFSIZE];
0326 
0327     memset(&xfer, 0, sizeof(struct spi_transfer));
0328 
0329     spi_message_init(&msg);
0330     xfer.tx_buf = tbuf;
0331     xfer.rx_buf = NULL;
0332     xfer.cs_change = 1;
0333 
0334     tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
0335     tbuf[1] = 0;
0336     tbuf[2] = REG_WRITE_DATA_TO_GRAM;
0337 
0338     xfer.bits_per_word = 8;
0339     xfer.len = 3;
0340     spi_message_add_tail(&xfer, &msg);
0341     spi_sync(spi, &msg);
0342 }
0343 
0344 /**
0345  * ili922x_poweron - turn the display on
0346  * @spi: spi device
0347  *
0348  * The sequence to turn on the display is taken from
0349  * the datasheet and/or the example code provided by the
0350  * manufacturer.
0351  */
0352 static int ili922x_poweron(struct spi_device *spi)
0353 {
0354     int ret;
0355 
0356     /* Power on */
0357     ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
0358     usleep_range(10000, 10500);
0359     ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
0360     ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
0361     msleep(40);
0362     ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
0363     msleep(40);
0364     /* register 0x56 is not documented in the datasheet */
0365     ret += ili922x_write(spi, 0x56, 0x080F);
0366     ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
0367     usleep_range(10000, 10500);
0368     ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
0369     ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
0370     msleep(40);
0371     ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
0372     msleep(40);
0373 
0374     return ret;
0375 }
0376 
0377 /**
0378  * ili922x_poweroff - turn the display off
0379  * @spi: spi device
0380  */
0381 static int ili922x_poweroff(struct spi_device *spi)
0382 {
0383     int ret;
0384 
0385     /* Power off */
0386     ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
0387     usleep_range(10000, 10500);
0388     ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
0389     ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
0390     msleep(40);
0391     ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
0392     msleep(40);
0393 
0394     return ret;
0395 }
0396 
0397 /**
0398  * ili922x_display_init - initialize the display by setting
0399  *            the configuration registers
0400  * @spi: spi device
0401  */
0402 static void ili922x_display_init(struct spi_device *spi)
0403 {
0404     ili922x_write(spi, REG_START_OSCILLATION, 1);
0405     usleep_range(10000, 10500);
0406     ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
0407     ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
0408     ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
0409     ili922x_write(spi, REG_COMPARE_1, 0x0000);
0410     ili922x_write(spi, REG_COMPARE_2, 0x0000);
0411     ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
0412     ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
0413     ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
0414     ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
0415 
0416     /* Set RGB interface */
0417     ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
0418 
0419     ili922x_poweron(spi);
0420 
0421     ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
0422     ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
0423     ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
0424     ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
0425     ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
0426     ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
0427     ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
0428     ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
0429     ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
0430     ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
0431     ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
0432     ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
0433     ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
0434     ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
0435     ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
0436     ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
0437     ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
0438     ili922x_reg_dump(spi);
0439     set_write_to_gram_reg(spi);
0440 }
0441 
0442 static int ili922x_lcd_power(struct ili922x *lcd, int power)
0443 {
0444     int ret = 0;
0445 
0446     if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
0447         ret = ili922x_poweron(lcd->spi);
0448     else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
0449         ret = ili922x_poweroff(lcd->spi);
0450 
0451     if (!ret)
0452         lcd->power = power;
0453 
0454     return ret;
0455 }
0456 
0457 static int ili922x_set_power(struct lcd_device *ld, int power)
0458 {
0459     struct ili922x *ili = lcd_get_data(ld);
0460 
0461     return ili922x_lcd_power(ili, power);
0462 }
0463 
0464 static int ili922x_get_power(struct lcd_device *ld)
0465 {
0466     struct ili922x *ili = lcd_get_data(ld);
0467 
0468     return ili->power;
0469 }
0470 
0471 static struct lcd_ops ili922x_ops = {
0472     .get_power = ili922x_get_power,
0473     .set_power = ili922x_set_power,
0474 };
0475 
0476 static int ili922x_probe(struct spi_device *spi)
0477 {
0478     struct ili922x *ili;
0479     struct lcd_device *lcd;
0480     int ret;
0481     u16 reg = 0;
0482 
0483     ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
0484     if (!ili)
0485         return -ENOMEM;
0486 
0487     ili->spi = spi;
0488     spi_set_drvdata(spi, ili);
0489 
0490     /* check if the device is connected */
0491     ret = ili922x_read(spi, REG_DRIVER_CODE_READ, &reg);
0492     if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
0493         dev_err(&spi->dev,
0494             "no LCD found: Chip ID 0x%x, ret %d\n",
0495             reg, ret);
0496         return -ENODEV;
0497     }
0498 
0499     dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
0500          reg, spi->max_speed_hz, spi->mode);
0501 
0502     ret = ili922x_read_status(spi, &reg);
0503     if (ret) {
0504         dev_err(&spi->dev, "reading RS failed...\n");
0505         return ret;
0506     }
0507 
0508     dev_dbg(&spi->dev, "status: 0x%x\n", reg);
0509 
0510     ili922x_display_init(spi);
0511 
0512     ili->power = FB_BLANK_POWERDOWN;
0513 
0514     lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
0515                     &ili922x_ops);
0516     if (IS_ERR(lcd)) {
0517         dev_err(&spi->dev, "cannot register LCD\n");
0518         return PTR_ERR(lcd);
0519     }
0520 
0521     ili->ld = lcd;
0522     spi_set_drvdata(spi, ili);
0523 
0524     ili922x_lcd_power(ili, FB_BLANK_UNBLANK);
0525 
0526     return 0;
0527 }
0528 
0529 static void ili922x_remove(struct spi_device *spi)
0530 {
0531     ili922x_poweroff(spi);
0532 }
0533 
0534 static struct spi_driver ili922x_driver = {
0535     .driver = {
0536         .name = "ili922x",
0537     },
0538     .probe = ili922x_probe,
0539     .remove = ili922x_remove,
0540 };
0541 
0542 module_spi_driver(ili922x_driver);
0543 
0544 MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
0545 MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
0546 MODULE_LICENSE("GPL");
0547 MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
0548 MODULE_PARM_DESC(tx_invert, "invert bytes before sending");
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